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Scaling of High Aspect Ratio Current
Limiters for the Individual Ballasting of
Large Arrays of Field Emitters
Stephen A. Guerrera
Luis F. Velasquez-GarciaAkintunde I. Akinwande
RQE Presentation11/01/2011
mailto:[email protected]:[email protected]:[email protected] -
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Overview
Introduction and Motivation
Modeling and Simulation Device Fabrication
Device Characterization and Analysis Conclusions
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RQE - 11/1/2011
Overview
Introduction and Motivation
Modeling and Simulation Device Fabrication
Device Characterization and Analysis Conclusions
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Motivation Many applications require compact, efficient electron sources
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!"#$ %& ()*+ ,-.+ /0001,2,+ 1345 63+ 7889
5* :;()%+ ?* #@ A)(=B#C
D$%)> 3E$==$#F !#;G#;(&$#FCCC*%H%(E>%I$J%=*J#E
Multi e-beam lithography Portable Vacuum Sources X-rays
Displays Terahertz Devices Ionizers/Neutralizers
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Physics of Electron
Sources
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EF
e-
metal vacuum
EF
e-
metal vacuum
Ex
x V(x>0) = -qFx
(a) (b)
W
00
Ex
Ex
x= 0 x
Thermionic or Photoemisssion Field Emisssion
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Physics of Electron
Sources
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EF
e-
metal vacuum
EF
e-
metal vacuum
Ex
x V(x>0) = -qFx
(a) (b)
W
00
Ex
Ex
x= 0 x
Thermionic or Photoemisssion Field Emisssion
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Field Emission Physics:
A two step process
Spindt Approximations to the Fowler-Nordheim Model:
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2D Fermi sea of electrons
J=qnv F
Ef e-Ec
Flux of electrons
to the surface
Transmission ofelectrons through
the barrier
!
J = q N(Ex )D(F,Ex )EC
!
" dEx
J =AF
2
1.1!exp
B !1.14"107
!1/2
#
$%
&
'(exp )
0.95 !B !!3/2
F
#
$%
&
'(
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Schematic Cross-section of a
Microfabricated Field Emitter
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Sharp emitter tips arerequired for emission becauseof the large electric fields
required for field emission
Field enhancement results atthe tip from solutions toLaplaces equation
In general, a self-alignedstructure is preferred formaximum transmission
EmitterCone
Si
Substrate
Poly-Siextraction
gate
Anode
Emitted
Electrons
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Ball-In-Sphere
Electrostatics Model
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Simple analytical model to describe the
electrostatics of a field emitter with a
proximal gate
Boundary value problem readily evaluated
in spherical coordinates to obtain the
magnitude of the electric field:
From this, an expression for the fieldfactor, !, is obtained:
Emitter
Cone
D
R
Poly-Si
extraction
gate
F(r) =V0D !R
D"R
1
r2
! =D
D! R
1
R
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Scaling
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All dimensions reduced by
scaling factor s
Assume current density
constant
Cross-sectional area
decreases
Packing density increases bysame amount
To first order, no net change
in current density for the
array
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Benefits of Scaling
FEA Dimensions Denser packing of field emitters
More redundancy for a given array size
Higher current density and overall emissioncurrent possible by increasing doping
More uniform emission current
Smaller aperture, allowing for higher fieldfactor, lower turn on voltage
Smaller energy distribution
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Tip Radii Statistical
Distribution
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0 100 200 300 400 500
1014
1012
1010
108
GatetoEmitter Voltage, VGE
[Volts]
EmissionCurrent,IE[A]
Burn out limit
ro=40 nm
M. Ding et al, TED 2002
Tip radii follow a log-normal or Gaussian
distribution (long tails)
Array sub-utilization anddamage due to Jouleheating and burnout
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Tip Radii Statistical
Distribution
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M. Ding et al, TED 2002
0 100 200 300 400 500
1014
1012
1010
108
GatetoEmitter Voltage, VGE
[Volts]
EmissionCurrent,IE[A]
Burn out limit
ro=10 nm
Tip radii follow a log-normal or Gaussian
distribution (long tails)
Array sub-utilization anddamage due to Jouleheating and burnout
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Individual Current Limiters
Allow Higher Overall Current
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Load-Line Analysis of
Supply Control
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tip radius: r1< r
2< r
3
V
I
I
V
I
V
I
Passive Resistance Dynamic Resistance
tip radius: r1< r
2< r
3
V
I
V
Slope = 1 / R
Slope = 1 / Ro
Pure resistors!Simultaneous high current and low currentdispersion not possible (or at least very hard)
Current sources!Simultaneous high current and low current
dispersion possible
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V
I
V
I
I
Passive Resistance Dynamic Resistance
V
I
V V
I
Scaling
Load-Line Analysis of
Supply Control
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Pure resistors!Simultaneous high current and low currentdispersion not possible (or at least very hard)
Current sources!Simultaneous high current and low current
dispersion possible
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Individually Ballasted
FEA-FET Structure
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VCT
n-Silicon Substrate VG= VGE+ VDS
Si Pillar
UngatedFET
Si FieldEmitter
D
S
VGE
VDS
E
G
A
Gate
Anode
VGS
VAS
Oxide DielectricFill / Void
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In the linear regime, the potential varies linearly along thelength of the channel
A linear conductance can be defined
Above a critical field, the velocity of electrons saturates, anda depletion region forms at the drain end of the channel
Additional voltage applied is dropped across the depletionregion
Output conductance arises from channel length modulation
RQE - 11/1/2011
Vertical Ungated FET
Operation
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ID =qAnedV(x)
dx
qAneVDS
L
GLIN =qAne
L
Anode
Gate
n-type Silicon Substrate
x = 0
x = L
Sil
iconPillar
Oxide/DielectricFill
Emitter
ID = IDSS[1 + VDS] = IDSS+ GOUTVDS
ID= qA(x)ne
1 +
evsat
2 dV(x)dx
2dV(x)
dx
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Prior Work
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GeometryParameters:
Pillar dimensions:
1!m x 1!m x 100
!m
Pitch: 10!m
Tip radius:
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Overview
Introduction and Motivation
Modeling and Simulation Device Fabrication
Device Characterization and Analysis
Conclusions
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Scaled Vertical Ungated
FET Simulation Results
Geometry: 100 nm x 100 nm x 10 !m ND= 5x1014cm-3
L!"IDSS#, rlin!, ro!
Simulations performed using SILVACOtoolset Full Si Process Simulator (ATHENA) Poisson equation and continuity
equation solver in Silicon (ATLAS)
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Scaled Vertical Ungated
FET Simulation Results
Geometry: 100 nm x 100 nm x 10 !m 100:1 Aspect Ratio
ND!"IDSS!, rlin#, ro#22
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Scaled Vertical Ungated
FET Simulation Results
Doping density: 2x1014cm-3
Aspect ratio: 100:1 (100 nm x 100 nm x 10 !m) Chosen to yield 1 nA/tip Thus 0.1-1.0 A/cm2for 1 um pitch
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Overview
Introduction and Motivation
Modeling and Simulation Device Fabrication
Device Characterization and Analysis
Conclusions
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Fabrication of Si
FEA-FETs
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Photolithographyto define dots
a)
b)
c)
SiO2 Si PR
e)
PR Removal,oxidation sharpening
and oxide removal
d)
Rough tip formation and
pillar formation
Grow oxidehardmask
RIEto pattern hardmask
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Completed FEA-FET
Structure
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100 nm
Pillar Height: 10!m
Pillar Diameter: 0.11!m
Tip Radius: < 10nm
Pitch: 5!m
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Overview
Introduction and Motivation
Modeling and Simulation Device Fabrication
Device Characterization and Analysis
Conclusions
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Current-Voltage Characterizationof Ungated FETs Without Emitters
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Single FET 4M FET Array
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Field Emission
Characterization Setup
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Field Emission I-V
Characterization
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Field Emission I-V
Characterization
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Analysis of Field
Emission Data Array size: 1.36 M emitters !(from 2-D electrostatic simulations of the structure in COMSOL):
1.34x104 cm-1.
Sensitivity analysis: !(spacing reduced to 12.5 !m): 5.84x104cm-1
!(tip radius reduced to 2.5 nm): 1.81x104cm-1
Saturation current (expected), Isat: ~1.3 mA (current of ~1 nA/emitter)
Current saturation voltage, VGSS, extrapolated from F-N curve: ~1.5kV
Upper bound on array burnout current (from failure analysis ofindividual vertical ungated FETs and heating analysis): ~10 A
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Overview
Introduction and Motivation
Modeling and Simulation Device Fabrication
Device Characterization and Analysis
Conclusions
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Conclusions
Successfully demonstrated the fabrication ofvertical ungated FETs with dimensions of100nm x 100nm x 10um with 1 micron pitch
This is the smallest, most dense array ofvertical ungated FETs ever reported
Demonstrated field emission and ballastingfrom Si emitters on top of scaled verticalungated FETs with five micron pitch, withcurrent density greater than 100 !A/cm2.
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Backup Slides
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Future Work
Devices with higher doping density should be built toensure higher currents can be obtained.
Better planarization / trench-filling techniques needto be explored
A process for integrated, self-aligned gates needs tobe adapted and developed for the FET-FEA structure
More complete analysis of the tip radius distribution
Lifetime analysis Adapting the FEA-FET structure to real applications
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Field Emission Requires
Large Electric Fields
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107
108
109
1010
108
106
104
102
100
F [V/cm]
T
ransmissionProbability
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Preliminary Tip Radius
Distribution
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Additional Hi Res Tip
SEMs
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RQE - 11/1/201141
!"#"$%&%# '"()%
!" #$%&%' )*+,
- %& .*
/ !01& 2*3#
4"55 &6#7% 2/
8"55 &6&,9 8
:-4! ;67, 25
: #61? @5
Axisymetric Simulation
of Vertical Ungated FETs
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Thermal Failure
Analysis
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Field Emission
Characterization Setup
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Field Emission
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Electrostatics Simulations:
!for devices with 1"m Pitch
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0
500
1000
1500
2000
2500
3000
3500
0
20004000
6000
8000
10000
1200014000
16000
18000
20000
0 2 4 6 8 10
Distance Above Substrate [microns]
[cm-1
]
Turn on voltage [V]
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COMSOL Field
Enhancement Simulation
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Zero charge / symmetry boundary
+VG
GND
Example Simulation Result
Solving the Laplaceequation
Field emitter: 30 coneangle with 5 nm or
2.5 nm radius Pillar width: 100 nm Pillar height: 10 !m Pitch: 5 !m # of Emitters: 5 Anode separation: 25 nm,
12.5 nm
Maximum field measuredat right-most field
emitter
CO SO
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COMSOL Field
Enhancement Simulation
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Solving the Laplaceequation
Field emitter: 30 coneangle with 5 nm or
2.5 nm radius Pillar width: 100 nm Pillar height: 10 !m Pitch: 5 !m # of Emitters: 5 Anode separation: 25 nm,
12.5 nm
Maximum field measuredat right-most field
emitterTip Meshing Detail
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Energy Distribution of
Emitted Electrons
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!=12.5x105 /r 0.7
ro=30x10-7
dr=3x10-7
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Energy Distribution of
Emitted Electrons
!=62.5x105 /r 0.7
ro=30x10-7
dr=3x10-7