-
Preface, Contents
Product Overview 1Configuration and Elements ofFunction Block Diagram 2
Addressing 3
Bit Logic Instructions 4
Timer Instructions 5
Counter Instructions 6
Integer Math Instructions 7
Floating-Point Math Instructions 8
Comparison Instructions 9Move and ConversionInstructions 10
Word Logic Instructions 11
Shift and Rotate Instructions 12
Data Block Instructions 13
Jump Instructions 14
Status Bit Instructions 15
Program Control Instructions 16
Appendix
Glossary, Index
10/98C79000-G7076-C566Release 01
Function Block Diagram (FBD)for S7-300 and S7-400Programming
Reference Manual
SIMATIC S7
This reference manual is part of the documentationpackage with the order number:
6ES7810-4CA04-8BR0
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iiFunction Block Diagram (FBD) for S7-300 and S7-400
C 9000 G 0 6 C 66 01
This manual contains notices which you should observe to ensure your own personal safety, as well as toprotect the product and connected equipment. These notices are highlighted in the manual by a warningtriangle and are marked as follows according to the level of danger:
! Dangerindicates that death, severe personal injury or substantial property damage will result if proper precautionsare not taken.
! Warningindicates that death, severe personal injury or substantial property damage can result if proper precautionsare not taken.
! Cautionindicates that minor personal injury or property damage can result if proper precautions are not taken.
Notedraws your attention to particularly important information on the product, handling the product, or to aparticular part of the documentation.
Note the following:
! WarningThis device and its components may only be used for the applications described in the catalog or thetechnical description, and only in connection with devices or components from other manufacturers whichhave been approved or recommended by Siemens.
SIMATIC, SIMATIC HMI and SIMATIC NET are registered trademarks of SIEMENSAG.
Third parties using for their own purposes any other names in this document which refer to trademarks mightinfringe upon the rights of the trademark owners.
We have checked the contents of this manual for agreement with thehardware and software described. Since deviations cannot be precludedentirely, we cannot guarantee full agreement. However, the data in thismanual are reviewed regularly and any necessary corrections included insubsequent editions. Suggestions for improvement are welcomed.
Siemens AG 1998Technical data subject to change.
Copyright Siemens AG 1998 All rights reservedThe reproduction, transmission or use of this document or its contents isnot permitted without express written authority. Offenders will be liable fordamages. All rights, including rights created by patent grant or registrationof a utility model or design, are reserved.
Siemens AGBereich Automatisierungs- und AntriebstechnikGeschaeftsgebiet Industrie-AutomatisierungssystemePostfach 4848, D-90327 Nuernberg
Siemens Aktiengesellschaft C79000-G7076-C566
Safety Guidelines
Correct Usage
Trademarks
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iiiFunction Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01
Preface
This manual is your guide to creating user programs in the Function BlockDiagram (FBD) programming language.This manual also includes a reference section that describes the syntax andfunctions of the language elements of Function Block Diagram.
The manual is intended for S7 programmers, operators, andmaintenance/service personnel. A working knowledge of automationprocedures is essential.
This manual is valid for release 5.0 of the STEP 7 programming softwarepackage.
FBD corresponds to the Function Block Diagram language defined in theInternational Electrotechnical Commissions standard IEC 1131-3. Forfurther details, refer to the table of standards in the STEP 7 fileNORM_TBL.WRI.
Purpose of theManual
Audience
Where is thisManual Valid?
Which StandardsDoes the SoftwareComply With?
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ivFunction Block Diagram (FBD) for S7-300 and S7-400
C79000-G7076-C566-01
To use this Function Block Diagram manual effectively, you should alreadybe familiar with the theory behind S7 programs which is documented in theonline help for STEP 7. The language packages also use the STEP 7 standardsoftware, so you should be familiar with handling this software and have readthe accompanying documentation.
Documentation Purpose Order NumberSTEP 7 Basic Information with Working with STEP 7 V5.0, Getting Started
Manual Programming with STEP 7 V5.0 Configuring Hardware and Communication
Connections, STEP 7 V5.0 From S5 to S7, Converter Manual
Basic information for technicalpersonnel describing the methods ofimplementing control tasks withSTEP 7 and the S7-300/400programmable controllers.
6ES7810-4CA04-8BA0
STEP 7 Reference with Ladder Logic (LAD)/Function Block
Diagram (FBD)/Statement List (STL) forS7-300/400 manuals
Standard and System Functions forS7-300/400
Provides reference information anddescribes the programminglanguages LAD, FBD and STL andstandard and system functionsextending the scope of the STEP 7basic information.
6ES7810-4CA04-8BA0
Online Helps Purpose Order NumberHelp on STEP 7 Basic information on programming
and configuring hardware withSTEP 7 in the form of an onlinehelp.
Part of the STEP 7Standard software.
Reference helps on STL/LAD/FBDReference help on SFBs/SFCsReference help on Organization Blocks
Context-sensitive referenceinformation.
Part of the STEP 7Standard software.
You can display the online help in the following ways:
Context-sensitive help about the selected object with the menu commandHelp > Context-Sensitive Help, with the F1 function key, or by clickingthe question mark symbol in the toolbar.
Help on STEP 7 via the menu command Help > Contents.
References to other documentation are indicated by reference numbers inslashes /.../. Using these numbers, you can check the exact title in theReferences section at the end of the manual.
Requirements
Accessing theOnline Help
References
Preface
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vFunction Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01
The SIMATIC Customer Support team offers you substantial additionalinformation about SIMATIC products via its online services:
General current information can be obtained:
on the Internet underhttp://www.ad.siemens.de/simatic/html_00/simatic
via the Fax-Polling number 08765-93 02 77 95 00
Current product information leaflets and downloads which you may finduseful are available:
on the Internet under http://www.ad.siemens.de/support/html_00/
via the Bulletin Board System (BBS) in Nuremberg (SIMATICCustomer Support Mailbox) under the number +49 (911) 895-7100.To dial the mailbox, use a modem with up to V.34 (28.8 Kbps) withthe following parameter settings: 8, N, 1, ANSI; or dial via ISDN(x.75, 64 Kbps).
If you have other questions, please contact the Siemens representative in yourarea. The addresses are listed, for example, in catalogs and in Compuserve(go autforum).Our SIMATIC Basic Hotline is also ready to help:
in Nuremberg, Germany
Monday to Friday 07:00 to 17:00 (local time): telephone:+49 (911) 8957000
or E-mail: [email protected]
in Johnson City (TN), USA Monday to Friday 08:00 to 17:00 (local time): telephone:
+1 423 4612522
or E-mail: [email protected]
in Singapore
Monday to Friday 08:30 to 17:30 (local time): telephone:+65 7407000
or E-mail: [email protected]
The SIMATIC Premium Hotline is available round the clock worldwidewith the SIMATIC card (telephone: +49 (911) 895-7777).
Siemens offers a number of training courses to introduce you to the SIMATICS7 automation system. Please contact your regional training center or thecentral training center in Nuremberg, Germany for details:Telephone: +49 (911) 895-3154.
SIMATIC CustomerSupport OnlineServices
AdditionalAssistance
Courses forSIMATIC Products
Preface
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viFunction Block Diagram (FBD) for S7-300 and S7-400
C79000-G7076-C566-01
To help us to provide the best possible documentation for you and futureSTEP 7 users, we need your support. If you have any comments orsuggestions relating to this manual or the online help, please complete thequestionnaire at the end of the manual and send it to the address shown.Please include your own personal rating of the documentation.
Questionnaires onthe Manual andOnline Help
Preface
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viiFunction Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01
Contents
Preface iii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Product Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Configuration and Elements of Function Block Diagram 2-1. . . . . . . . . . . . . . . . . . .
2.1 Elements and Box Structure 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Boolean Logic and Truth Tables 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Significance of the CPU Registers in Statements 2-9. . . . . . . . . . . . . . . . . . . .
3 Addressing 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Overview 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Types of Addresses 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Bit Logic Instructions 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Overview 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 AND Logic Operation 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 OR Logic Operation 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 AND-before-OR Logic Operation and OR-before-AND Logic Operation 4-5. 4.5 Exclusive OR Logic Operation 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 Insert Binary Input 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 Negate Binary Input 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Assign 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 Midline Output 4-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 Save RLO to BR Memory 4-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 Set Output 4-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 Reset Output 4-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13 Set Counter Value 4-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14 Up Counter Instruction 4-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.15 Down Counter Instruction 4-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16 Pulse Timer Instruction 4-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17 Extended Pulse Timer Instruction 4-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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4.18 On-Delay Timer Instruction 4-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19 Retentive On-Delay Timer Instruction 4-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.20 Off-Delay Timer Instruction 4-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.21 Positive RLO Edge Detection 4-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.22 Negative RLO Edge Detection 4-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23 Address Positive Edge Detection 4-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.24 Address Negative Edge Detection 4-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.25 Set_Reset Flip Flop 4-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.26 Reset_Set Flip Flop 4-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Timer Instructions 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Memory Areas and Components of a Timer 5-2. . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Choosing the Right Timer 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Pulse S5 Timer 5-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Extended Pulse S5 Timer 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 On-Delay S5 Timer 5-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Retentive On-Delay S5 Timer 5-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 Off-Delay S5 Timer 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Counter Instructions 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Memory Address and Components of a Counter 6-2. . . . . . . . . . . . . . . . . . . . . 6.2 Up-Down Counter 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Up Counter 6-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Down Counter 6-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Integer Math Instructions 7-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Add Integer 7-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Add Double Integer 7-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Subtract Integer 7-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Subtract Double Integer 7-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Multiply Integer 7-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 Multiply Double Integer 7-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7 Divide Integer 7-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8 Divide Double Integer 7-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9 Return Fraction Double Integer 7-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.10 Evaluating the Bits of the Status Word with Integer Math Instructions 7-11. . .
Contents
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8 Floating-Point Math Instructions 8-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Overview 8-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Add Real 8-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Subtract Real 8-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Multiply Real 8-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 Divide Real 8-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 Evaluating the Bits of the Status Word with Floating-Point Instructions 8-7. . 8.7 Forming the Absolute Value of a Floating-Point Number 8-8. . . . . . . . . . . . . . 8.8 Forming the Square (SQR) of a Floating-Point Number 8-9. . . . . . . . . . . . . . . 8.9 Forming the Square Root (SQRT) of a Floating-Point Number 8-10. . . . . . . . . 8.10 Forming the Natural Logarithm of a Floating-Point Number 8-11. . . . . . . . . . . . 8.11 Forming the Exponential Value of a Floating-Point Number 8-12. . . . . . . . . . . . 8.12 Forming Trigonometric Functions of Angles as Floating-Point Numbers 8-13.
9 Comparison Instructions 9-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Compare Integer 9-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Compare Double Integer 9-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 Compare Real 9-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 Move and Conversion Instructions 10-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 Assign Value 10-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 BCD to Integer 10-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Integer to BCD 10-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 Integer to Double Integer 10-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 BCD to Double Integer 10-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6 Double Integer to BCD 10-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7 Double Integer to Real 10-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.8 Ones Complement Integer 10-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.9 Ones Complement Double Integer 10-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.10 Twos Complement Integer 10-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.11 Twos Complement Double Integer 10-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.12 Negate Real Number 10-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.13 Round to Double Integer 10-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.14 Truncate Double Integer Part 10-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.15 Ceiling 10-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.16 Floor 10-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
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11 Word Logic Instructions 11-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Overview 11-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 (Word) AND Word 11-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 (Word) AND Double Word 11-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 (Word) OR Word 11-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5 (Word) OR Double Word 11-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6 (Word) Exclusive OR Word 11-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.7 (Word) Exclusive OR Double Word 11-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12 Shift and Rotate Instructions 12-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 Shift Instructions 12-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 Rotate Instructions 12-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13 Data Block Instructions 13-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1 Open Data Block 13-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14 Jump Instructions 14-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1 Overview 14-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 Unconditional Jump in a Block 14-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 Conditional Jump in a Block 14-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4 Jump-If-Not 14-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5 Jump Label 14-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15 Status Bit Instructions 15-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1 Overview 15-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2 Exception Bit Binary Result 15-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3 Result Bits 15-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4 Exception Bit Unordered 15-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5 Exception Bit Overflow 15-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.6 Exception Bit Overflow Stored 15-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16 Program Control Instructions 16-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.1 Calling an FC/SFC without Parameters 16-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2 Calling an FB, FC, SFB, SFC, and Multiple Instances 16-4. . . . . . . . . . . . . . . . 16.3 Return 16-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4 Master Control Relay Instructions 16-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 Master Control Relay Activate/Deactivate 16-10. . . . . . . . . . . . . . . . . . . . . . . . . . . 16.6 Master Control Relay On/Off 16-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Alphabetical Lists of Instructions A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.1 List of Instructions with International Names A-2. . . . . . . . . . . . . . . . . . . . . . . .
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xiFunction Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01
A.2 List of Instructions with International (English) Names and German Equivalents A-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.3 List of Instructions with German SIMATIC Names A-10. . . . . . . . . . . . . . . . . . . . A.4 List of Instructions with German Names and International (English)
Equivalents A-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B Programming Examples B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B.1 Overview B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.2 Bit Logic Instructions B-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3 Timer Instructions B-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.4 Counter and Comparison Instructions B-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.5 Integer Math Instructions B-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.6 Word Logic Instructions B-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C References C-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Glossary Glossary-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index Index-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents
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1-1Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01
Product Overview
FBD stands for Function Block Diagram. FBD is a graphic programminglanguage and uses logic boxes familiar from Boolean algebra to representlogic. Complex functions (for example math functions) can also berepresented directly connected to the logic boxes.
The Function Block Diagram programming language has all the elementsnecessary for creating a complete user program. It contains a wide range ofinstructions. These include the various basic instructions and a wide range ofaddresses and address types. Functions and function blocks allow you tostructure your FBD program clearly.
The FBD programming package is an integral part of the STEP 7 StandardSoftware. This means that following the installation of your STEP 7 software,all the editor functions, compiler functions, and test/debug functions for FBDare available to you.
Using FBD, you can create your own user program. With the IncrementalEditor, the input of the local data structure is made easier with the help oftable editors.
There are three programming languages in the standard software, STL, FBD,and LAD. You can switch from one language to the other almost withoutrestriction and choose the most suitable language for the particular block youare programming.
If you write programs in LAD or FBD, you can always switch over to theSTL representation. If you convert LAD programs into FBD programs andvice versa, program elements that cannot be represented in the destinationlanguage are displayed in STL.
What is FBD?
The FBDProgrammingLanguage
The ProgrammingPackage
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Configuration and Elements of FunctionBlock Diagram
Section Description Page2.1 Elements and Box Structure 2-22.2 Boolean Logic and Truth Tables 2-62.3 Significance of the CPU Registers in Statements 2-9
ChapterOverview
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2.1 Elements and Box Structure
FBD instructions consist of elements and boxes that are connectedgraphically to form networks. The elements and boxes can be classified inthe following groups:
STEP 7 represents some of the FBD instructions as individual elements thatdo not require addresses or parameters (see Table 2-1).
Table 2-1 FBD Instruction as an Element without Address or Parameters
Element Description Section in this Manual
Negate binary input 4.7
STEP 7 represents some of the FBD instructions as boxes for which you mustspecify an address (see Table 2-2). For more detailed information aboutaddressing, refer to Chapter 3.
Table 2-2 FBD Instruction as Box with Address
Element Description Section in this Manual
=
Assign 4.8
STEP 7 represents some of the FBD instructions as boxes for which youspecify an address and a value (for example a timer or counter value, seeTable 2-3).For more detailed information about addressing, refer to Chapter 3.
Table 2-3 FBD Instruction as a Box with Address and Value
Element Description Section in this Manual>
TV
SS
Retentive on-delay timer 4.19
FBD Instructions
Instructions asElements
Instruction as aBox with Address
Instruction as aBox with Addressand Value
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STEP 7 represents some of the FBD instructions as boxes with inputs andoutputs (see Table 2-4). The inputs are on the left of the box and the outputson the right. You specify the input parameters and some of the outputparameters. Most outputs are provided by the STEP 7 software. To assignparameters, you must use the specific notation of the data types.
The parameters of the Enable input (EN) and the Enable output (ENO) aredescribed below. For further information about input and output parameters,refer to the descriptions of the individual instructions in this manual.
Table 2-4 FBD Operation as a Box with Inputs and Outputs
Box Description Section in this Manual
DIV_R
IN1EN
IN2OUTENO
Divide real 8.5
If the Enable input (EN) of an FBD box is activated, the box carries out aspecific function. If the function is executed by the box without errors, theEnable output (ENO) is activated. The parameters EN and ENO of an FBDbox are of the BOOL data type and can be located in the I, Q, M, D, or Lmemory areas (see Table 2-5 and 2-6).How EN and ENO function is described below:
If EN is not activated (its signal state is 0), the box does not execute itsfunction and ENO is not activated (its signal state is also 0).
If EN is activated (its signal state is 1) and if the box executes its functionwithout errors, ENO is also activated (its signal state is also 1).
If EN is activated (its signal state is 1) and if an error occurs during theexecution of the function, ENO is not activated (its signal state remains0).
The majority of the addresses in FBD refer to memory areas. The followingtable shows the types and their functions.
Instruction as Boxwith Parameters
Enable Input andEnable OutputParameters
Memory Areas andFunctions
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Table 2-5 Memory Areas and Their Functions
Access to AreaName of Area Function of Area Using Units of the
Following Size:Abbr.
Process inputimage
At the beginning of the scan cycle, the operating system readsthe inputs from the process and records the values in this area.The program uses these values when it is running cyclically.
Input bitInput byteInput wordInput double word
IIBIWID
Process outputimage
During the scan cycle, the program calculates output values andenters them in this area. At the end of the scan cycle, theoperating system reads the calculated output values from thisarea and sends them to the process outputs.
Output bitOutput byteOutput wordOutput double word
QQBQWQD
Bit memory This area provides memory space for interim results calculatedin the program.
Memory bitMemory byteMemory wordMemory double word
MMBMWMD
I/Os
Ext. inputs
Using this area, your program has direct access to input andoutput modules (peripheral inputs and outputs).
Peripheral input bytePeripheral input wordPeripheral input doubleword
PIBPIWPID
I/Os:
Ext. outputs
Peripheral output bytePeripheral output wordPeripheral output doubleword
PQBPQWPQD
Timers Timers are function elements in FBD. This area providesmemory space for timer cells. In this area, the clock timingaccesses the timer cells and updates them by decrementing thetimer value. Timer operations access these timer cells.
Timer (T) T
Counters Counters are function elements in FBD. This area providesmemory space for counters. Count instructions access the cellsin this area.
Counter (C) C
Data block This area contains data that can be accessed from within anyblock. If it is necessary to open two data blocks at the sametime, you can open one with the OPN DB instruction and theother with the OPN DI instruction. The notation of theaddresses, for example L DBWi and L DIWi identifies the datablock to be accessed.Although you can access any data block with the OPN DIi i hi i i i i l d i d
Data block opened withthe OPN DBinstruction:Data bitData byteData wordData double word
DBXDBBDBWDBD
instruction, this instruction is mainly used to open instance datablocks that are assigned to function blocks (FBs) and systemfunction blocks (SFBs). For more detailed information aboutFBs and SFBs, refer to the STEP 7 Online Help.
Data block opened withthe OPN DIinstruction:Data bitData byteData wordData double word
DIXDIBDIWDID
Local data This area contains temporary local data belonging to a logicblock (FB or FC). This type of data is also called dynamic localdata. This area is used as a buffer. When the logic block isclosed, the data are lost. These data are located in the local datastack (L stack).
Temporary local data bitTemporary local databyteTemporary local datawordTemporary local datadouble word
LLB
LW
LD
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Table 2-6 lists the maximum address ranges for the various memory areas.For more detailed information about the address ranges on your CPU, refer tothe corresponding manual /70/ or /101/.
Table 2-6 Memory Areas and Their Address Ranges
Name of AreaAccess Using
M i Add RName of Area Units of the Following Sizes: Abbr. Maximum Address Range
Process input image Input bitInput byteInput wordInput double word
IIBIWID
0.0 to 65 535.70 to 65 5350 to 65 5340 to 65 532
Process outputimage
Output bitOutput byteOutput wordOutput double word
QQBQWQD
0.0 to 65 535.70 to 65 5350 to 65 5340 to 65 532
Bit memory Memory bitMemory byteMemory wordMemory double word
MMBMWMD
0.0 to 255.70 to 2550 to 2540 to 252
I/Os:External inputs
Peripheral input bytePeripheral input wordPeripheral input double word
PIBPIWPID
0 to 65 5350 to 65 5340 to 65 532
I/Os:External outputs
Peripheral output bytePeripheral output wordPeripheral output double word
PQBPQWPQD
0 to 65 5350 to 65 5340 to 65 532
Timers Timer T 0 to 255Counters Counter C 0 to 255Data block Data block opened with the DB [OPN]
instruction
Data bit in the data blockData byteData wordData double word
DBXDBBDBWDBD
0.0 to 65 535.70 to 65 5350 to 65 5340 to 65 532
Data block opened with the DI [OPN] instruction
Data bit in the instance DBData byteData wordData double word
DIXDIBDIWDID
0.0 to 65 535.70 to 65 5350 to 65 5340 to 65 532
Local data 1) Temporary local data bitTemporary local data byteTemporary local data wordTemporary local data double word
LLBLWLD
0.0 to 65 535.70 to 65 5350 to 65 5340 to 65 532
1) With FBD instructions, you can only use an address in the L memory area when you declare it as VAR_TEMP in the variable declaration table.
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2.2 Boolean Logic and Truth Tables
The FBD programming language is based on the binary logic of Booleanalgebra in which variables can adopt the values true (1) or false (0).Each logic instruction checks the signal state of a variable for 1 (true,satisfied) or 0 (false, not satisfied) and then produces a result. The instructionthen either saves the result or uses it to perform a Boolean logic operation.The result of the logic operation is known as the RLO.
To represent the logic, the logic boxes known from Boolean algebra are used.
The results of the logic instructions for all possible combinations of logicalvariables are listed in truth tables.
The rules of Boolean logic are illustrated below based on the AND, OR, andexclusive OR logic operations.
In an AND logic operation, the signal states of two or more specifiedaddresses are checked. If the signal state of the address is 1 the condition issatisfied and the instruction produces the result 1. If the signal state of theaddress is 0, the condition is not satisfied and the operation produces theresult 0.
Figure 2-1 illustrates an AND logic operation in the FBD programminglanguage.
I1.0&
I1.1 =Q4.0
The condition is satisfied when thesignal state is 1 at inputs I1.0 ANDI1.1.
Figure 2-1 AND Logic Operation in FBD
The possible results of an AND logic operation can be represented in a truthtable. Here, 1 means satisfied and 0 means not satisfied. The possiblelogic instructions and their results are shown in Table 2-7.
Table 2-7 AND Truth Table
If the result of the signalstate check at address I1.0
is as below
and the result of the signalstate check at address I1.1
is as below
the result of the logic instruc-tion is as follows:
1 1 10 1 01 0 0
0 0 0
Boolean Logic
AND LogicOperation
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In an OR logic operation, the signal states of two or more specified addressesare checked. If the signal state of one of the addresses is 1, the condition issatisfied and the instruction provides the result 1. If the signal state of alladdresses is 0, the condition is not satisfied and the instruction produces theresult 0.
Figure 2-2 shows an OR logic operation in the FBD programming language.
I1.0I1.1 =
Q4.0The condition is satisfied when thesignal state is 1 at inputs I1.0 ORI1.1.
>=1
Figure 2-2 OR Logic Operation in FBD
The possible results of an OR logic operation can be shown in a truth table.Here, 1 means satisfied and 0 means not satisfied. The possible logicoperations and their results are shown in Table 2-8.
Table 2-8 OR Truth Table
If the result of the sig-nal state check at ad-dress I1.0 is as below
and the result of thesignal state check at
address I1.1 is as below
the result of the logic instructionis as follows:
1 0 1
0 1 11 1 1
0 0 0
In an exclusive OR logic operation, the signal states of two or more specifiedaddresses are checked. If the signal state of one of the addresses is 1 thecondition is satisfied and the instruction provides the result 1. If the signalstate of all addresses is 0 or 1, the condition is not satisfied and theinstruction produces the result 0.
Figure 2-3 shows an exclusive OR logic operation in the FBD programminglanguage.
I1.0I1.1 =
Q4.0The condition is satisfied when thesignal state is 1 at input I1.0 OR atinput I1.1 exclusively (i.e. not atboth).
XOR
Figure 2-3 Exclusive OR Logic Operation in FBD
OR LogicOperation
Exclusive ORLogic Operation
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The possible results of an exclusive OR logic operation can be represented ina truth table. Here, 1 means satisfied and 0 means not satisfied. Thepossible logic operations and their results are shown in Table 2-9.
Table 2-9 Exclusive OR Truth Table
If the result of thesignal state check at
address I1.0 is as below
and the result of thesignal state check at
address I1.1 is as below
the result of the logic instructionis as follows:
1 0 1
0 1 11 1 0
0 0 0
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2-9Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01
2.3 Significance of the CPU Registers in Statements
Registers help the CPU perform logic, math, shift, or conversion instructions.These registers are described below.
The accumulators are general-purpose registers that you use to process bytes,words, and double-words. The accumulators are 32-bits wide.
0781516232431
Accumulator (1 or 2) Low wordHigh word
Low byteHigh byteLow byteHigh byte
Figure 2-4 Areas of an Accumulator
The status word contains bits that you can reference in the address of bitlogic instructions. The following sections explain the significance of bits0 through 8.
28215... ...29 2427 26 25 2023 22 21
BR OSCC1 CC0 OV FCOR STA RLO
Figure 2-5 Structure of the Status Word
Value Meaning0 Sets the signal state to 01 Sets the signal state to 1x Changes the state State remains unchanged
Explanation
Accumulators
Status Word
Changes in theBits of the StatusWord
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Bit 0 of the status word is called the first-check bit (FC bit, see Figure 2-5).At the start of an FBD network, the signal state of the FC bit is always 0,unless the previous network ended with the SAVE box
Each logic instruction checks the signal state of the FC bit as well as thesignal state of the contact that the instruction addresses. The signal state ofthe FC bit determines the sequence of a logic string. If the FC bit is 0 (at thestart of an FBD network), the instruction stores the result in the result oflogic operation bit (RLO) of the status word and sets the FC bit to 1. This isknown as the first check. The 1 or 0 that is set in the RLO bit after the firstcheck is then referred to as the result of first check.
If the signal state of the FC bit is 1, an instruction then combines the result ofits signal state check at the addressed contact with the RLO formed at theaddressed contact after the first check, and sets the result in the RLO bit.
A logic string made up of FBD instructions always ends with an outputinstruction (for example set output, reset output, assign) or with a jumpinstruction dependent on the result of the logic operation (RLO). Theseinstructions reset the FC bit to 0.
Bit 1 of the status word is called the result of logic operation bit (RLO bit,see Figure 2-5). This bit stores the result of a string of logic instructions orcompare instructions. The signal state of the RLO bit provides informationabout signal flow.
The first instruction in an FBD network checks the signal state of an addressand produces a result of 1 or 0. The instruction enters the result of this signalstate in the RLO bit. The second instruction in a string of logic operationsalso checks the signal state of an address and produces a result. Theinstruction now combines this result with the value of the RLO bit of thestatus word according to the rules of Boolean logic (see First Check above).The result of the logic operation is entered in the RLO bit of the status wordand replaces the previous value in the RLO bit. Each subsequent instructionin the string of logic operations combines two values: the result of the signalcheck at the specified address and the current RLO.
You can, for example, assign the state of a bit memory location to the RLOduring a first check using a Boolean logic operation or trigger a jumpinstruction.
First Check
Result of LogicOperation
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Bit 2 of the status word is called the status bit (STA bit, see Figure 2-5). Thestatus bit stores the value of a bit that is referenced. The status of a logicinstruction that reads memory is always the same as the value of the bit thatthis instruction checks (the bit on which it performs its logic operation). Thestatus of a bit instruction that writes to memory (Set Output, Reset Output, orAssign) is the same as the value of the bit to which the instruction writes. Ifno writing takes place, the value is the same as the value of the bit that theinstruction references. The status bit has no significance for bit instructionsthat do not access memory. These instructions set the status bit to 1 (STA=1).The status bit is not checked by an instruction. It is interpreted duringprogram test (program status) only.
Bit 3 of the status word is called the OR bit (see Figure 2-5). The OR bit isrequired to execute an AND before OR logic operation. An AND logicoperation can contain the instructions AND input and AND NOT input. TheOR bit indicates to the instructions that a previously executed AND logicoperation produced the value 1 so that the result of the OR logic operationhas already been determined. Any other bit-processing instruction resets theOR bit.
Bit 5 of the status word is called the overflow bit (OV bit, see Figure 2-5).The OV bit indicates an error. It is set by a math instruction or a comparefloating-point numbers instruction after an error has occurred (overflow,illegal instruction, illegal floating-point number). The bit is set or resetaccording to the result of the math or compare instruction (error).
Bit 4 of the status word is called the store overflow bit (OS bit, see Figure2-5). The OS bit is set together with the OV bit when an error occurs. Sincethe OS bit is unchanged when math instructions are executed without errors(in contrast to the OV bit), this indicates whether or not an error occurred inone of the previously executed instructions. The following instructions resetthe OS bit: JOS (jump if stored overflow bit = 1, must be programmed inSTL), block calls and block end statements.
Bits 7 and 6 of the status word are called condition code 1 and conditioncode 0 (CC1 and CC0, see Figure 2-5). The CC1 and CC0 bits provideinformation about the following results or bits:
Result of a math instruction
Result of a compare instruction
Result of a digital instruction
Bits that have been shifted out of the address by a shift or rotateinstruction.
Tables 2-10 to 2-15 list the meaning of CC1 and CC0 after your program hasexecuted certain instructions.
Status Bit
OR Bit
Overflow Bit
Stored OverflowBit
CC1 and CC0
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Table 2-10 CC1 and CC0 after Math Instructions, without Overflow
CC1 CC0 Explanation0 0 Result = 0
0 1 Result < 01 0 Result > 0
Table 2-11 CC1 and CC0 after Integer Math Instructions, with Overflow
CC1 CC0 Explanation0 0 Negative range overflow in Add Integer and Add Double Integer
0 1
Negative range overflow in Multiply Integer and MultiplyDouble IntegerPositive range overflow in Add Integer, Subtract Integer, AddDouble Integer, Subtract Double Integer, Twos ComplementInteger, and Twos Complement Double Integer
1 0
Positive range overflow in Multiply Integer and Multiply DoubleInteger, Divide Integer, and Divide Double IntegerNegative range overflow in Add Integer, Subtract Integer, AddDouble Integer, and Subtract Double Integer
1 1 Division by 0 in Divide Integer, Divide Double Integer, andReturn Fraction Double Integer
Table 2-12 CC1 and CC0 after Floating-Point Math Instructions, with Overflow
CC1 CC0 Explanation0 0 Gradual underflow0 1 Negative range overflow
1 0 Positive range overflow1 1 Not a valid floating-point number
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Table 2-13 CC1 and CC0 after Comparison Instructions
CC1 CC0 Explanation0 0 IN2 = IN1
0 1 IN2 < IN11 0 IN2 > IN1
1 1 IN1 or IN2 is not a valid floating-point number
Table 2-14 CC1 and CC0 after Shift and Rotate Instructions
CC1 CC0 Explanation0 0 Bit shifted out last = 01 0 Bit shifted out last = 1
Table 2-15 CC1 and CC0 after Word Logic Instructions
CC1 CC0 Explanation0 0 Result = 0
1 0 Result 0
Bit 8 of the status word is called the binary result bit (BR bit, see Figure 2-5).The BR bit forms a link between the processing of bits and words. This bit isan efficient method with which you can interpret the result of a wordinstruction as a binary result and include this result in a binary string of logicoperations. The BR bit represents an internal memory bit in which the RLOcan be saved prior to a word instruction that changes the RLO so that the oldRLO is available again after the operation when the interrupted series of bitinstructions is resumed.
With the BR bit, you can, for example, program a function block (FB) or afunction (FC) in Statement List (STL) and call the FB or FC in FBD.If you write a function block or a function that you want to call in FBD,regardless of whether you write the FB or FC in STL or FBD, you must takeinto account the BR bit. The BR bit corresponds to the Enable output (ENO)of an FBD box. You save the RLO in the BR bit using the SAVE instruction(in STL) or with the SAVE FBD box according to the following criteria: Save an RLO of 1 in the BR bit when the FB or FC is processed without
errors.
Save an RLO of 0 in the BR bit if an error occurs during the processing ofan FB or FC.
Program these instructions at the end of the FB or FC so that they are the lastinstructions executed in the block.
Binary Result Bit
Configuration and Elements of Function Block Diagram
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2-14Function Block Diagram (FBD) for S7-300 and S7-400
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! WarningThe BR bit can be reset to 0 unintentionally.When you write FBs or FCs in FBD and do not handle the BR bit asdescribed above, an FB or FC might overwrite the BR bit of another FB orFC.To avoid this problem, save the RLO at the end of each FB or FC asdescribed above.
The Enable input (EN) and Enable output (ENO) parameters of an FBD boxfunction as explained below:
If EN is not activated (its signal state is 0), the box does not execute itsfunction and ENO is not activated (it also has a signal state of 0).
If EN is activated (its signal state is 1) and the box executes its functionwithout errors, ENO is also activated (its signal state is also 1).
If EN is activated (its signal state is 1) and an error occurs while thefunction is being executed, ENO is not activated (its signal state is 0).
When you call a system function block (SFB) or a system function (SFC) inyour program, the SFB or SFC indicates whether or not the CPU executed thefunction without errors by setting the signal state of the BR bit:
If an error occurred during execution, the BR bit is set to 0.
If the function was executed without errors, the BR bit is 1.
Meaning ofEN/ENO
Configuration and Elements of Function Block Diagram
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3-1Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01
Addressing
Section Description Page3.1 Overview 3-2
3.2 Types of Addresses 3-4
ChapterOverview
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3.1 Overview
Many FBD instructions operate with one or more addresses. The addressspecifies a constant or a location at which the instruction finds a variablewhich it uses to perform a logic operation. This location can be a bit, byte,word, or double word.
Examples of possible addresses are as follows:
A constant, the value of a timer or counter, or an ASCII character string
A bit in the status word of the programmable controller
A data block and a location within the data block area
The following types of addressing are available:
Immediate addressing (specifying a constant as the address) Direct addressing (specifying a variable as the address)Figure 3-1 shows an example of immediate and direct addressing.
The function of the box is to compare two input parameters (in this case, two16-bit integers) to see if the first input is less than or equal to the second. Theconstant 50 is entered as input parameter IN1. Memory word MW200, alocation in memory, is entered as input parameter IN2.
Because the constant 50 in the example is the actual value with which IN1 ofthe box will work, 50 is an immediate address of the instruction box. BecauseMW200 points to a location in memory where there is another value withwhich IN2 of the box will work, MW200 is a direct address. MW200 is alocation, not the actual value itself.
CMP
IN1
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3-3Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01
Table 3-1 Constant Formats for Immediate Addressing Using Addresses of Elementary Data Types
Type andDescription
Size inBits
Format Options Range and Number Notation (Lowest Value to Highest Value)
Example
BOOL(Bit)
1 Boolean Text TRUE/FALSE TRUE
BYTE(Byte)
8 Hexadecimal B#16#0 to B#16#FF B#16#10byte#16#10
WORD(Word)
16 Binary
Hexadecimal
BCDUnsigned decimal
2#0 to2#1111_1111_1111_1111W#16#0 to W#16#FFFF
C#0 to C#999B#(0,0) to B#(255,255)
2#0001_0000_0000_0000
W#16#1000word16#1000C#998B#(10,20)byte#(10,20)
DWORD(Doubleword)
32 Binary
HexadecimalUnsigned decimal
2#0 to2#1111_1111_1111_1111_1111_1111_1111_1111DW#16#0000_0000 toDW#16#FFFF_FFFFB#(0,0,0,0) toB#(255,255,255,255)
2#1000_0001_0001_1000_1011_1011_0111_1111
DW#16#00A2_1234dword#16#00A2_1234B#(1,14,100,120)byte#(1,14,100,120)
INT(Integer)
16 Signed decimal -32768 to 32767 1
DINT(Doubleinteger)
32 Signed decimal L#-2147483648 to L#2147483647 L#1
REAL(Floatingpoint)
32 IEEEfloating point
Upper limit: 3.402823e+38Lower limit: 1.175495e-38 )
1.234567e+13
S5TIME(SIMATICtime)
16 S5 Time in 10-ms units (asdefault value)
S5T#0H_0M_0S_10MS toS5T#2H_46M_30S_0MS andS5T#0H_0M_0S_0MS
S5T#0H_1M_0S_0MSS5TIME#0H_1M_0S_0MS
TIME(IEC time)
32 IEC time in 1-msunits, signedinteger
T#-24D_20H_31M_23S_648MS toT#24D_20H_31M_23S_647MS
T#0D_1H_1M_0S_0MSTIME#0D_1H_1M_0S_0MS
DATE(IEC date)
16 IEC date in 1-day units
D#1990-1-1 to D#2168-12-31
D#1994-3-15DATE#1994-3-15
TIME_OF_DAY(Time ofday)
32 Time of day in1-ms units
TOD#0:0:0.0 toTOD#23:59:59.999
TOD#1:10:3.3TIME_OF_DAY#1:10:3.3
CHAR(Character)
8 Character A,B, etc. E
Addressing
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3.2 Types of Addresses
One of the following elements can be used as the address of an FBDinstruction:
A bit whose signal state will be checked
A bit to which the signal state of the logic operation string will beassigned
A bit to which the result of logic operation (RLO) will be assigned A bit that will be set or reset
A number that indicates a counter that will be incremented ordecremented
A number that indicates a timer to be used
An edge memory bit that saves the previous RLO
An edge memory bit that saves the previous signal state of a differentaddress
A byte, word, or double word containing a value with which the FBDelement or box will work
The number of a data block (DB or DI) that will be opened or created The number of a function (FC), system function (SFC), a function block
(FB), or system function block (SFB) that will be called A label as the destination for a jump
Variables as addresses consist of an address identifier and an address withinthe memory area indicated by the address identifier. An address identifier canbe one of the following two basic types:
An address identifier that indicates the following two data objects: The memory area in which the instruction finds a value (data object)
with which it can perform a logic operation (for example I forprocess input image, see Table 2-5).
The size of a value (data object) with which the instruction willperform a logic operation (for example B for Byte, W for Wordand D for Double Word, see Table 2-5).
An address identifier that indicates a memory area but not the size of thedata object in the area (for example an identifier for the T area (timers), C(counters), or DB or DI (data block) and the number of the timer, counter,or data block, see Table 2-5).
PossibleAddresses
Address Identifiers
Addressing
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3-5Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01
A pointer identifies the location of a variable. A pointer contains an addressinstead of a value. When assigning an actual parameter for the parametertype Pointer, you provide the memory address. With STEP 7, you can enterthe pointer either in the pointer format or simply as an address (for exampleM 50.0). The following example illustrates the pointer format for accessingdata starting at M 50.0.
P#M50.0
If you are working with an instruction whose address identifier indicates amemory area of your programmable controller and a data object that is eithera word or double word in size, remember that the memory location is alwaysreferenced as a byte address. This byte address is the smallest byte number orthe number of the high byte within the word or double word. The address inthe instruction shown in Figure 3-2, for example, references four successivebytes in the memory area M starting at byte 10 (MB10) through to byte 13(MB13).
Instruction: L MD10
Address identifier Byte address
Figure 3-2 Example of a Memory Location Referenced as a Byte Address
Figure 3-3 shows data objects with the following sizes: Double word: memory double word MD10
Word: memory word MW10, MW11 and MW12
Byte: memory bytes MB10, MB11, MB12 and MB13
If you use absolute addresses that are a word or double word long, make surethat you avoid any overlapping byte assignments.
MB10 MB11 MB12 MB13
MW11
MD10
MW10 MW12
Figure 3-3 Referencing a Memory Location as a Byte Address
Pointers
Working withWords or DoubleWords as the DataObject
Addressing
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3-6Function Block Diagram (FBD) for S7-300 and S7-400
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Addressing
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4-1Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01
Bit Logic Instructions
Section Description Page4.1 Overview 4-2
4.2 AND Logic Operation 4-34.3 OR Logic Operation 4-4
4.4 AND-before-OR Logic Operation and OR-before-ANDLogic Operation
4-5
4.5 Exclusive OR Logic Operation 4-64.6 Insert Binary Input 4-74.7 Negate Binary Input 4-8
4.8 Assign 4-94.9 Midline Output 4-104.10 Save RLO to BR Memory 4-11
4.11 Set Output 4-12
4.12 Reset Output 4-134.13 Set Counter Value 4-14
4.14 Up Counter Instruction 4-164.15 Down Counter Instruction 4-174.16 Pulse Timer Instruction 4-184.17 Extended Pulse Timer Instruction 4-204.18 On-Delay Timer Instruction 4-22
4.19 Retentive On-Delay Timer Instruction 4-244.20 Off-Delay Timer Instruction 4-264.21 Positive RLO Edge Detection 4-284.22 Negative RLO Edge Detection 4-294.23 Address Positive Edge Detection 4-304.24 Address Negative Edge Detection 4-314.25 Set_Reset Flip Flop 4-324.26 Reset_Set Flip Flop 4-33
ChapterOverview
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4.1 Overview
Bit logic instructions work with two digits, 1 and 0. These two digits formthe base of a number system called the binary system. The two digits 1 and 0are called binary digits or simply bits. In conjunction with AND, OR, XORand outputs, a 1 stands for logical YES and a 0 for logical NO.
The bit logic instructions interpret the signal states 1 and 0 and combinethem according to the rules of Boolean logic. These combinations produce aresult of 1 or 0 known as the result of logic operation (RLO, see Section 2.2).The logic operations triggered by the bit logic instructions execute a varietyof functions.
Bit logic instructions are available for the following functions:
AND, OR, and XOR: these instructions check the signal state andproduce a result that is either copied to the RLO bit or combined with it.With AND logic operations, the result of the signal state check iscombined according to the AND truth table (see Table 2-7). With ORlogic operations, the result of the signal state check is combinedaccording to the OR truth table (see Table 2-8), with exclusive OR logicoperations, according to the exclusive OR truth table (see Table 2-9).
Assign and Midline Output: these instructions assign the RLO or store ittemporarily.
The following instructions react to an RLO of 1:
Set Output and Reset Output
Set_Reset Flip Flop and Reset_Set Flip Flop
Some instructions react to a rising or falling edge so that you can executethe following functions:
Increment or decrement the value of a counter
Start a timer
Produce an output of 1
The remaining instructions affect the RLO directly in the following ways:
Negate the RLO
Save the RLO in the binary result bit of the status word
In this chapter, the counter and timer instructions are shown in theinternational and SIMATIC forms.
Explanation
Functions
Bit Logic Instructions
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4-3Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01
4.2 AND Logic Operation
With the AND instruction, you can check the signal states of two or morespecified addresses at the inputs of an AND box.
If the signal state of all addresses is 1, the condition is satisfied and theinstruction provides the result 1. If the signal state of an address is 0, thecondition is not satisfied and the instruction produces the result 0.
If the AND instruction is the first instruction in a string of logic operations, itsaves the result of its signal state check in the RLO bit.
Every AND instruction that is not the first instruction in the string of logicoperations, combines the result of its signal state check with the value storedin the RLO bit. These values are combined according to the AND truth table.
Table 4-1 AND Box and Parameters
FBD Box Parameters Data Type Memory Area Description
&
BOOLTIMERCOUNTER
I, Q, M, T, C, D, L The address indicates the bit whosesignal state will be checked.
I0.0
Status Word Bits
Output Q4.0 is set when the signal state is 1 at inputI0.0 AND I0.1.
BR CC1 CC0 OV OS OR STA RLO FCwrites x x x 1
&
I0.1 =Q4.0
Figure 4-1 AND Logic Operation
Description
Bit Logic Instructions
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4.3 OR Logic Operation
With the OR instruction, you can check the signal states of two or morespecified addresses at the inputs of an OR box.
If the signal state of one of the addresses is 1, the condition is satisfied andthe instruction produces the result 1. If the signal state of all addresses is 0,the condition is not satisfied and the instruction produces the result 0.
If the OR instruction is the first instruction in a string of logic operations, itsaves the result of its signal state check in the RLO bit.
Each OR instruction that is not the first instruction in the string of logicoperations combines the result of its signal state check with the value storedin the RLO bit. These values are combined according to the OR truth table.
Table 4-2 OR Box and Parameters
FBD Box Parameters Data Type Memory Area Description
>=1
BOOLTIMERCOUNTER
I, Q, M, T, C, D, L The address specifies the bit whosesignal state will be checked
Status Word Bits
Output Q4.0 is set when the signal state is 1 at input I0.0 OR at inputI0.1.
BR CC1 CC0 OV OS OR STA RLO FCwrites x x x 1
I0.0 >=1
I0.1 =Q4.0
Figure 4-2 OR Logic Operation
Description
Bit Logic Instructions
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4-5Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01
4.4 AND-before-OR Logic Operation and OR-before-AND LogicOperation
With the AND-before-OR instruction, you can check the result of a signalstate according to the OR truth table.
With an AND-before-OR logic operation the signal state is 1 when at leastone AND logic operation is satisfied.
I0.0The signal state is 1 at output Q3.1 whenat least one AND logic operation is satisfied.
&
I0.1
I0.2 &
I0.3
>=1
Q3.1The signal state is 0 at output Q3.1 whenno AND logic operation is satisfied.
Status Word Bits
BR CC1 CC0 OV OS OR STA RLO FCwrites x x x 1
=
Figure 4-3 AND-before-OR Logic Operation
With the OR-before-AND instruction, you can check the result of a signalstate check according to the AND truth table.
With an OR-before-AND logic operation the signal state is 1 when all ORlogic operations are satisfied.
I1.0The signal state is 1 at output Q3.1 whenboth OR logic operations are satisfied.I1.1
I1.2
I1.3
>=1Q3.1
The signal state is 0 at output Q3.1 whenat least one OR logic operation is not satisfied.
>=1
Status Word Bits
BR CC1 CC0 OV OS OR STA RLO FCwrites x x x 1
=
&
Figure 4-4 OR-before-AND Logic Operation
Description
Description
Bit Logic Instructions
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4.5 Exclusive OR Logic Operation
With the Exclusive OR instruction, you can check the result of a signal statecheck according to the Exclusive OR truth table.
With an Exclusive OR logic operation, the signal state is 1 when the signalstate of one of the two specified addresses is 1.
Table 4-3 Exclusive OR Box and Parameters
FBD Box Parameters Data Type Memory Area Description
XOR
BOOLTIMERCOUNTER
I, Q, M, T, C, D, L The address specifies the bit whosesignal state will be checked.
Status Word Bits
The signal state is 1 at output Q3.1 when the signal state is 1 ateither input I0.0 OR at input I0.2 (exclusively, in other words not at both).
BR CC1 CC0 OV OS OR STA RLO FCwrites x x x 1
I0.0XOR
I0.2 =Q3.1
Figure 4-5 Exclusive OR Logic Operation
Description
Bit Logic Instructions
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4-7Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01
4.6 Insert Binary Input
The Insert Binary Input instruction inserts a further binary input to an AND,OR, or XOR box.
Table 4-4 Binary Input Element and Parameters
FBD Element Parameters Data Type Memory Area Description
BOOL
TIMERCOUNTER
I, Q, M, T, C, D, L The address specifies the bit whosesignal state will be checked
Status Word Bits
BR CC1 CC0 OV OS OR STA RLO FCwrites 1 x
Output Q4.0 is 1 when the signal state atI1.0 AND I1.1 AND I1.2 is 1.
I1.0 &I1.1
=
Q4.0I1.2
Figure 4-6 Insert Binary Input
Description
Bit Logic Instructions
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4-8Function Block Diagram (FBD) for S7-300 and S7-400
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4.7 Negate Binary Input
The Negate Binary Input instruction negates the RLO.
When you negate the result of logic operation, you must remember certainrules:
If the result of logic operation at the first input of an AND or OR box isnegated, there is no nesting.
If the result of logic operation is negated but not at the first input of anOR box, the entire binary logic operation before the input is included inthe OR logic operation.
If the result of logic operation is negated but not at the first input of aAND box, the entire binary logic operation before the input is included inthe AND logic operation.
Table 4-5 Negate Binary Input Element
FBD Element Parameters Data Type Memory Area Description
None
Status Word Bits
BR CC1 CC0 OV OS OR STA RLO FCwrites 1 x
Output Q4.0 is 1 when:the signal state at I1.0 AND I1.1 is NOT 1AND the signal state at I1.2 AND I1.3 is NOT 1OR the signal state at I1.4 is NOT 1.I1.2 &
I1.3
I1.4
>=1
I1.0 &I1.1
&
=
Q4.0
Figure 4-7 Negate Binary Input
Description
Bit Logic Instructions
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4-9Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01
4.8 Assign
The Assign instruction produces the result of logic operation. The box at theend of a logic operation has the signal 1 or 0 according to the followingcriteria:
The output has the signal 1 when the conditions of the logic operationbefore the output box are satisfied
The output has the signal 0 when the conditions of the logic operationbefore the output box are not satisfied.
The FBD logic operation assigns the signal state to the output that isaddressed by the instruction (to achieve the same effect, the signal state ofthe RLO bit could also be assigned to the address). If the conditions of theFBD logic operations are satisfied, the signal state at the output box is 1.Otherwise the signal state is 0. The Assign instruction is influenced by theMaster Control Relay (MCR).For more detailed information about the functions of the MCR, refer toSection 16.4.
You can only place the Assign box at the right-hand end of the string of logicoperations. You can, however, use several Assign boxes.
You can create a negated assignment with the Negate Input instruction.
Table 4-6 Assign Box and Parameters
FBD Box Parameters Data Type Memory Area Description
=
BOOL I, Q, M, D, L The address specifies the bit to whichthe signal state of the string of logicoperations is assigned.
Status Word Bits
The signal state at output Q4.0 is 1 when the signalstate is 1 at inputs I0.0 AND I0.1, OR I0.2 is 0.
BR CC1 CC0 OV OS OR STA RLO FCwrites 0 x 0
Q4.0
I0.0 &
I0.1
I0.2
>=1
=
Figure 4-8 Assign
Description
Bit Logic Instructions
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4.9 Midline Output
The Midline Output instruction is an intermediate element that buffers theRLO. More precisely, this element buffers the bit logic operation of the lastbranch to be opened before the Midline Output.
The Midline Output instruction is influenced by the Master Control Relay(MCR). For more information about the MCR functions, see Section 16.4.You can create a negated Midline Output by negating the input of theMidline Output.
Table 4-7 Midline Output Box and Parameters
FBD Box Parameters Data Type Memory Area Description
# BOOL I, Q, M, D, L1 The address specifies the bit to
which the RLO will be assigned.
1 With the Connector instruction you can only use an address in the L memory area if you declare the address inVAR_TEMP; you cannot use the L memory area for absolute addresses.
Status Word Bits
BR CC1 CC0 OV OS OR STA RLO FCwrites 0 x 1
The Midline Outputs buffer the following results of the logic operations:M0.0 buffers the negated M1.1 the negatedRLO of RLO of DB5.DBX3.2 the negated RLO of the entireM2.2 the RLO of bit logic operation in bit 2 of the 3rd bytes in DB 5.
I1.2 &I1.3
I1.4
>=1
I1.0 &I1.1 &
=
M0.0
DB5.DBX3.2 Q4.0
I1.0 &I1.1
I1.2 &I1.3
I1.4
#
M1.1#
M2.2# #
#
Figure 4-9 Midline Output
Description
Bit Logic Instructions
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4-11Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01
4.10 Save RLO to BR Memory
The Save RLO to BR Memory instruction saves the RLO in the BR bit of thestatus word. The first check bit FC is not reset.
For this reason, if there is an AND logic operation in the next network, thestate of the BR bit is included in the logic operation.
Using the Save RLO to BR Memory instruction in conjunction withchecking the BR bit in the same block or on subordinate blocks is notrecommended, because the BR bit can be modified by many instructionsoccurring inbetween. It is advisable to use the SAVE instruction beforeexiting a block, since the ENO output (=BR bit) is then set to the value of theRLO bit and you can then check for errors in the block.
With the Save RLO to BR Memory instruction, the RLO of a network canform part of a logic operation in a subordinate block. The CALL instructionin the calling block resets the first check bit.
Table 4-8 Save RLO to BR Memory Box and Parameters
FBD Box Parameters Data Type Memory Area Description
SAVE None
Status Word Bits
BR CC1 CC0 OV OS OR STA RLO FCwrites x
The result of logic operation (RLO) is written to the BR bit.SAVE
I1.2 &I1.3
Figure 4-10 Save RLO to BR Memory
Description
Bit Logic Instructions
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4.11 Set Output
The Set Output instruction is only executed when the RLO is 1. If the RLO is1, this instruction sets the specified address to 1. If the RLO is 0, theinstruction does not affect the specified address which remains unchanged.
The Set Output instruction is influenced by the Master Control Relay (MCR).For more detailed information about the MCR, refer to Section 16.4.
Table 4-9 Set Output Box and Parameters
FBD Box Parameters Data Type Memory Area Description
S
BOOL I, Q, M, D, L The address specifies which bit willbe set.
Status Word Bits
BR CC1 CC0 OV OS OR STA RLO FCwrites 0 x 0
Q4.0
The signal state at output Q4.0 is set to 1 only when: The signal state is 1 at inputs I0.0 AND I0.1
OR the signal state at input I0.2 is 0.
If the RLO of the branch is 0, the signal state of Q4.0 isnot changed.
I0.0 &I0.1
S
>=1
I0.2
Figure 4-11 Set Output
Description
Bit Logic Instructions
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4-13Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01
4.12 Reset Output
The Reset Output instruction is only executed when the RLO is 1. If the RLOis 1, this instruction resets the specified address to 0. If the RLO is 0, theinstruction does not affect the specified address which remains unchanged.
The Reset Output instruction is influenced by the Master Control Relay(MCR). For more detailed information about the MCR, refer to Section 16.4.
Table 4-10 Reset Output Box and Parameters
FBD Box Parameters Data Type Memory Area Description
R
BOOLTIMERCOUNTER
I, Q, M, T, C, D, L The address specifies which bit willbe reset.
Status Word Bits
BR CC1 CC0 OV OS OR STA RLO FCwrites 0 x 0
The signal state at output Q4.0 is reset to 0 only when: The signal state is 1 at inputs I0.0 AND I0.1
OR the signal state at input I0.2 is 0.
If the RLO of the branch is 0, the signal state at outputQ4.0 is unchanged.
Q4.0
I0.0 &I0.1
R
>=1
I0.2
Figure 4-12 Reset Output
Description
Bit Logic Instructions
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4.13 Set Counter Value
With the Set Counter Value instruction, you assign a default value to thecounter you have specified. This instruction is executed only when there is arising edge at the RLO (change from 0 to 1 in the RLO).You can only place the Set Counter Value box at the right-hand end of thestring of logic operations. You can, however, use several Set Counter Valueboxes.
Table 4-11 Set Counter Value Box and Parameters, with SIMATIC Mnemonics
FBD Box Parameters Data Type MemoryArea
Description
SZ
Counternumber
COUNTER Z Address1 specifies the number of thecounter that will be assigned a presetvalue.
ZW
ZW WORD E, A, M, D, Lor constant
The value that is preset (address2)can be in the range between 0 and999. If you enter a constant, thecharacters, C# must precede thevalue indicating the BCD format, forexample C#100.
Table 4-12 Set Counter Value Box and Parameters with International Mnemonics
FBD Box Parameters Data Type MemoryArea
Description
SC
Counternumber
COUNTER C Address1 specifies the number of thecounter that will be assigned a presetvalue.
CV
CV WORD I, Q, M, D, Lor constant
The value that is preset (address2)can be in the range between 0 and999. If you enter a constant, thecharacters, C# must precede thevalue indicating the BCD format, forexample C#100.
Description
Bit Logic Instructions
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4-15Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01
Status Word Bits
BR CC1 CC0 OV OS OR STA RLO FCwrites 0 0
I0.0
C5 The counter C5 has the value 100 preset when the signalstate of I0.0 changes from 0 to 1 (rising edge in the RLO).C# specifies that you are entering a value in BCD format.If there is no rising edge, the value of counter C5 is notchanged.C#100 CV
SC
Figure 4-13 Set Counter Value
Bit Logic Instructions
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4-16Function Block Diagram (FBD) for S7-300 and S7-400
C79000-G7076-C566-01
4.14 Up Counter Instruction
The Up Counter instruction increments the value of a specified counter by 1when there is a rising edge at the RLO (change from 0 to 1) and the value ofthe counter is less than 999. If there is no rising edge at the RLO, or thecounter has already reached the value 999, it is not incremented.
The Set Counter Value instruction sets the value of the counter (seeSection 4.13).You can only place the Up Counter box at the right-hand end of the string oflogic operations. You can, however, use several Up Counter boxes.
Table 4-13 Up Counter Boxes and Parameters with SIMATIC and International Mnemonics
FBD Boxes Parameters Data Type Memory Area Description
ZV
CU
Counternumber
COUNTER Z
C
The address specifies the number ofthe counter that will be incremented.
Status Word Bits
BR CC1 CC0 OV OS OR STA RLO FCwrites 0 0
I0.0
C10 If the signal state of I0.0 changes from 0 to 1 (rising edgein the RLO), the value of the counter C10 is incrementedby 1 (unless the value of C10 is 999).If there is no rising edge, the value of C10 remainsunchanged.
CU
Figure 4-14 Up Counter
Description
Bit Logic Instructions
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4-17Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01
4.15 Down Counter Instruction
The Down Counter instruction decrements the value of a specified counter by1 when there is a rising edge at the RLO (change from 0 to 1) and the valueof the counter is higher than 0. If there is no rising edge at the RLO, or if thecounter has already reached the value 0, the value of the counter is notdecremented.
The Set Counter Value instruction sets the value of the counter (seeSection 4.13).You can only place the Down Counter box at the right-hand end of the stringof logic operations. You can, however, use more than one Down Counterboxes.
Table 4-14 Down Counter Boxes and Parameters with SIMATIC and International Mnemonics
FBD Boxes Parameters Data Type Memory Area Description
ZR
CD
Counternumber
COUNTER Z
C
The address specifies the number ofthe counter to be decremented.
Status Word Bits
BR CC1 CC0 OV OS OR STA RLO FCwrites 0 0
I0.0
C10If the signal state of input I0.0 changes from 0 to 1 (risingedge at the RLO), the value of counter C10 is decrementedby 1 (unless the value of C10 is already 0).If there is no rising edge, the value of C10 is not changed.
CD
Figure 4-15 Down Counter
Description
Bit Logic Instructions
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4-18Function Block Diagram (FBD) for S7-300 and S7-400
C79000-G7076-C566-01
4.16 Pulse Timer Instruction
The Pulse Timer instruction starts a timer with a specified value when thereis a rising edge at the RLO (change from 0 to 1). As long as the RLO ispositive, the timer continues to run for the specified time. A signal statecheck for 1 produces 1 as long as the timer is running. If the RLO changesfrom 1 to 0 before the time has expired, the timer is stopped. In this case, asignal state check for 1 produces a result of 0.
The time units used for timers are d (days), h (hours), m (minutes), s(seconds) and ms (milliseconds).For more detailed information about the memory area and the components ofa timer, refer to Section 5.1.
You can only place the Pulse Timer box at the right-hand end of the string oflogic operations. You can, however, use more than one Pulse Timer box.
Table 4-15 Pulse Timer Box and Parameters with SIMATIC Mnemonics
FBD Box Parameters Data Type Memory Area Description
SITimernumber
TIMER T The address specifies thenumber of the timer to bestarted.
TW
TW S5TIME E, A, M, D, L orconstant
Time value (S5TIME format)
Table 4-16 Pulse Timer Box and Parameters with International Mnemonics
FBD Box Parameters Data Type Memory Area Description
SPTimernumber
TIMER T The address specifies thenumber of the timer to bestarted.
TV
TV S5TIME I, Q, M, D, L orconstant
Time value (S5TIME format)
Description
Bit Logic Instructions
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4-19Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01
Status Word Bits
BR CC1 CC0 OV OS OR STA RLO FCwrites 0 0
T5If the signal state of input I0.0 changes from 0 to 1 (rising edge atthe RLO), timer T5 is started. As long as the signal state is 1, thetimer continues to run for the specified time of 2 seconds. If thesignal state at I0.0 changes from 1 to 0 before this time hasexpired, the timer is stopped.As long as the timer is running, the signal state at output Q4.0 is 1.Examples of timer values:S5T#2s = 2 secondsS5T#12m_18s = 12 minutes and 18 seconds
I0.0
TV
SP
S5T#2s
Q4.0=T5
Network 1:
Network 2:
Figure 4-16 Pulse Timer
Bit Logic Instructions
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4-20Function Block Diagram (FBD) for S7-300 and S7-400
C79000-G7076-C566-01
4.17 Extended Pulse Timer Instruction
The Extended Pulse Timer instruction starts a timer with a specified value ifthere is a rising edge at the RLO (change from 0 to 1). The timer continues torun for the specified time even if the RLO changes to 0 before this time hasexpired. A signal state check for 1 produces 1 as long as the timer is running.The timer is restarted with the specified time if the RLO changes from 0 to 1while the timer is running.
For more detailed information about the memory area and the components ofa timer, refer to Section 5.1.
You can only place the Extended Pulse Timer box at the right-hand end of thestring of logic operations. You can, however, use more than one ExtendedPulse Timer box.
Table 4-17 Extended Pulse Timer Box and Parameters with SIMATIC Mnemonics
FBD Box Parameters Data Type Memory Area Description
SVTimernumber
TIMER T The address specifies thenumber of the timer to bestarted.
TW
TW S5TIME E, A, M, D, L orconstant
Time value (S5TIME format)
Table 4-18 Extended Pulse Timer Box and Parameters with International Mnemonics
FBD Box Parameters Data Type Memory Area Description
SETimernumber
TIMER T The address specifies thenumber of the timer to bestarted.
TV
TV S5TIME I, Q, M, D, L orconstant
Time value (S5TIME format)
Description
Bit Logic Instructions
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4-21Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01
Status Word Bits
BR CC1 CC0 OV OS OR STA RLO FCwrites 0 0
If the signal state of input I0.0 changes from 0 to 1 (rising edge atthe RLO), timer T5 is started. The timer continues to run withoutbeing influenced by a falling edge at the RLO. If the signal state ofinput I0.0 changes from 0 to 1 before the specified time hasexpired, the timer is retriggered.
As long as the timer is running, the signal state at output Q4.0 is 1.
S5T#2s
I0.0
TV
SET5
Q4.0=T5
Network 1:
Network 2:
Figure 4-17 Extended Pulse Timer
Bit Logic Instructions
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4-22Function Block Diagram (FBD) for S7-300 and S7-400
C79000-G7076-C566-01
4.18 On-Delay Timer Instruction
The On-Delay Timer instruction starts a specified timer when there is a risingedge at the RLO (change from 0 to 1). A signal state check for 1 produces 1when the specified time has expired without an error occurring and the RLOis still 1. If the RLO changes from 1 to 0 while the timer is running, the timeris stopped. In this case, a signal state check for 1 always produces the result0.
For more detailed information about the address of a timer in memory andthe components of a timer, refer to Section 5.1.
You can only place the On-Delay Timer box at the right-hand end of thestring of logic operations. You can, however, use more than one On-DelayTimer box.
Table 4-19 On-Delay Timer Box and Parameters with SIMATIC Mnemonics
FBD Box Parameters Data Type Memory Area Description
SETimernumber
TIMER T The address specifies thenumber of the timer to bestarted.
TW
TW S5TIME E, A, M, D, L orconstant
Time value (S5TIME format)
Table 4-20 On-Delay Timer Box and Parameters with International Mnemonics
FBD Box Parameters Data Type Memory Area Description
SDTimernumber
TIMER T The address specifies thenumber of the timer to bestarted.
TV
TV S5TIME I, Q, M, D, L orconstant
Time value (S5TIME format)
Description
Bit Logic Instructions
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4-23Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01
Status Word Bits
BR CC1 CC0 OV OS OR STA RLO FCwrites 0 0
If the signal state of input I0.0 changes from 0 to 1(rising edge at the RLO), timer T5 is started. When thetime expires, and the signal state is still 1, output Q4.0has the value 1. If the signal state changes from 1 to 0,the timer is stopped.S5T#2s
I0.0
TV
SDT5
Q4.0=T5
Network 1:
Network 2:
Figure 4-18 On-Delay Timer
Bit Logic Instructions
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4-24Function Block Diagram (FBD) for S7-300 and S7-400
C79000-G7076-C566-01
4.19 Retentive