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Precise Continuous Non-Intrusive Measurement-Based
Execution Time Estimation
Boris Dreyer, Christian Hochberger, Simon Wegener, Alexander Weiss
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This work was funded within the project CONIRAS by the German Federal Ministry for Education and Research with the funding ID 01IS13029. The responsibility for the content remains with the authors.
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The Setting
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The Timing Problem
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Problem Solved?
Reinhard Wilhelm et al.: The Worst-case Execution Time Problem
— Overview of Methods and Survey of Tools
ACM Transactions on Embedded Computing Systems, Vol. 7, No. 3, April 2008.
CONCLUSIONS
„The problem of determining upper bounds on execution
times for single tasks and for quite complex processor
architectures has been solved. Several commercial WCET
tools are available and have experienced very positive
feedback from extensive industrial use.“
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Well, almost…
Unpredictable delays due to interference on multi-cores
Unpredictable hardware (e.g. random replacement policies for caches)
Undocumented hardware
⇒Very pessimistic results!
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Multi-core Interference-Sensitive WCET Analysis
Leveraging Runtime Resource Capacity Enforcement
ECRTS’14
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PREDATOR : ICT project in the 7th Framework Program of the EU
Predictability Considerations in the Design
of Multi-core Embedded Systems
ERTS 2010
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Measurements?
Karsten Schmidt et al.:
Non-Intrusive Tracing at First Instruction
SAE Technical Paper 2015-01-0176
“In the selected use case, a simple regression test, first a
function trace for a longer time span, and then later on an
instruction trace for a dedicated time span were generated.
This approach (instead of tracing everything across a long
time span) is necessary due to the limited bandwidth to
components outside of the microcontroller.”
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Catching the Worst Case
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Catching the Worst Case
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Measurements?
Karsten Schmidt et al.:
Non-Intrusive Tracing at First Instruction
SAE Technical Paper 2015-01-0176
“The art of tracing lies in the selection of the proper
abstraction level and time in order to perform safe
regression tests or identify potential issues as fast as
possible. Especially when working under high time pressure
with high costs related to the tests, or when working under
extreme conditions, […], efficiency in tracing is crucial.”
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Time stamps
MPSoC (4 CPUs)
Data read
Instructions
CP
U 0
Data written
Time stamps
Data read
Instructions
CP
U 1
Data written
Time stamps
Data read
Instructions
CP
U 2
Data written
Time stamps
Data read
Instructions
CP
U 3
Data written
Bandwith (average): 0,3 .. 4 Bit / Instruction (non-cycle accurate)5 .. 8 Bit / Instruction (cycle accurate)8 Bit / Instruction (data trace)
MPSoC, 4 CPUs, 1 GHzCycle accurate instruction + data trace4 x 14 Bit x 1 GHz => approx. 28 Gbit/s ( + timestamps)( + bus master trace)( + peak bandwidth)
embedded trace based emulation system
Emulator Target
MPSoC
CPUs
peripherals
Emb
edd
ed
trac
e
trace data
Offline analysis
State of The Art: Embedded Trace
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Trace Recording and Offline Processing
SoC
Traceport
CPU0
CPU1
CPU2
CPU3
Per
Per
Mem
Mem
Trace tool
SDRAM
Host
Hard disc
Trace data processing
(offline)
SoC vendor’s responsibility
Tool vendor’s responsibility
Results
Drawbacks:
- Not all trace messages go through the SoC‘s trace port due to limited bandwidth - Processing bandwidth of host trace port is smaller than trace port bandwidth - Huge latency for the detection of MPSoC internal states - Restricted to on-chip trigger logic
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Solution: Online Analysis of Trace Data
Real-time processing trace tool
Event processing
SoC
Traceport
CPU0
CPU1
CPU2
CPU3
Per
Per
Mem
Mem
Mes
sage
pro
cess
ing
Instrumentation Trace
Data Trace
Ownership Trace
Watchpoint Trace
InstructionInstrution
Reconstruction
Configurable generic event
processing structures Custom
programmable FPGA fabric
Custom programmable
processor
con
figu
rati
on
HLL propositions
compiler
CoreSight / Nexus via parallel, Aurora, PCIe lanes
up to 20 Gbit/s
- Trace bandwidth ≤ processing bandwidth - µs latency for detection of MPSoC internal states - Parallel processing / parallel oberservations
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Our Approach
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Workflow
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Workflow
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Measurement Configurator
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Events
(address, tag, level, distinctor, call, entry, exit, return)
Events are generated for each basic block.
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Events
(address, tag, level, distinctor, call, entry, exit, return)
The address of the basic block‘s first instruction.
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Events
(address, tag, level, distinctor, call, entry, exit, return)
A custom field used to efficiently address statistic records in memory
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Events
(address, tag, level, distinctor, call, entry, exit, return)
The loop nesting level of the basic block.
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Events
(address, tag, level, distinctor, call, entry, exit, return)
A field to distinguish two loops with the same nesting level that lie directly after another.
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Events
(address, tag, level, distinctor, call, entry, exit, return)
Is another routine called in the basic block?
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Events
(address, tag, level, distinctor, call, entry, exit, return)
Is a routine entered with this basic block?
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Events
(address, tag, level, distinctor, call, entry, exit, return)
Is a routine exited with this basic block?
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Events
(address, tag, level, distinctor, call, entry, exit, return)
Did a return from a called routine happen?
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Measurement Configurator
Enter f, Call g
(0x1004, 1, 0, 0, 1, 1, 0, 0)
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Measurement Configurator
Enter g, Enter L1
(0x2000, 2, 1, 0, 0, 1, 0, 0)
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Measurement Configurator
Enter L2
(0x202c, 3, 2, 0, 0, 0, 0, 0)
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Measurement Configurator
Leave L2, Enter L3
(0x2050, 5, 2, 1, 0, 0, 0, 0)
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Measurement Configurator
Leave g
(0x207c, 8, 0, 0, 0, 0, 1, 0)
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Workflow
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Event Stream
(0x1004, 1, 0, 0, 1, 1, 0, 0) @ t+0
(0x2000, 2, 1, 0, 0, 1, 0, 0) @ t+8
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+30
(0x2034, 4, 2, 0, 0, 0, 0, 0) @ t+46
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+48
(0x2034, 4, 2, 0, 0, 0, 0, 0) @ t+56
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+57
(0x2050, 5, 2, 1, 0, 0, 0, 0) @ t+59
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Execution Time
of BB @ 0x1004
8 cycles
Event Stream
(0x1004, 1, 0, 0, 1, 1, 0, 0) @ t+0
(0x2000, 2, 1, 0, 0, 1, 0, 0) @ t+8
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+30
(0x2034, 4, 2, 0, 0, 0, 0, 0) @ t+46
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+48
(0x2034, 4, 2, 0, 0, 0, 0, 0) @ t+56
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+57
(0x2050, 5, 2, 1, 0, 0, 0, 0) @ t+59
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Execution Time
of BB @ 0x2034
2 cycles
Event Stream
(0x1004, 1, 0, 0, 1, 1, 0, 0) @ t+0
(0x2000, 2, 1, 0, 0, 1, 0, 0) @ t+8
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+30
(0x2034, 4, 2, 0, 0, 0, 0, 0) @ t+46
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+48
(0x2034, 4, 2, 0, 0, 0, 0, 0) @ t+56
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+57
(0x2050, 5, 2, 1, 0, 0, 0, 0) @ t+59
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Execution Time
of BB @ 0x2034
1 cycle
Event Stream
(0x1004, 1, 0, 0, 1, 1, 0, 0) @ t+0
(0x2000, 2, 1, 0, 0, 1, 0, 0) @ t+8
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+30
(0x2034, 4, 2, 0, 0, 0, 0, 0) @ t+46
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+48
(0x2034, 4, 2, 0, 0, 0, 0, 0) @ t+56
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+57
(0x2050, 5, 2, 1, 0, 0, 0, 0) @ t+59
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Execution Time
of BB @ 0x2034
1 cycle
Event Stream
(0x1004, 1, 0, 0, 1, 1, 0, 0) @ t+0
(0x2000, 2, 1, 0, 0, 1, 0, 0) @ t+8
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+30
(0x2034, 4, 2, 0, 0, 0, 0, 0) @ t+46
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+48
(0x2034, 4, 2, 0, 0, 0, 0, 0) @ t+56
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+57
(0x2050, 5, 2, 1, 0, 0, 0, 0) @ t+59
Pure maximisation gives 2 cycles.
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Execution Time
of BB @ 0x2034
1 cycle
Event Stream
(0x1004, 1, 0, 0, 1, 1, 0, 0) @ t+0
(0x2000, 2, 1, 0, 0, 1, 0, 0) @ t+8
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+30
(0x2034, 4, 2, 0, 0, 0, 0, 0) @ t+46
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+48
(0x2034, 4, 2, 0, 0, 0, 0, 0) @ t+56
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+57
(0x2050, 5, 2, 1, 0, 0, 0, 0) @ t+59
Pure maximisation gives 2 cycles.
We want to take typical cache behaviour into account!
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Execution Time
of BB @ 0x2034
1 cycle
Event Stream
(0x1004, 1, 0, 0, 1, 1, 0, 0) @ t+0
(0x2000, 2, 1, 0, 0, 1, 0, 0) @ t+8
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+30
(0x2034, 4, 2, 0, 0, 0, 0, 0) @ t+46
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+48
(0x2034, 4, 2, 0, 0, 0, 0, 0) @ t+56
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+57
(0x2050, 5, 2, 1, 0, 0, 0, 0) @ t+59
Pure maximisation gives 2 cycles.
Idea: Distinguish between first and all other loop iterations.
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Loop Iteration State Machine
A state is a data structure that keeps track of the call stack, the loop nesting level and whether we are in the first or in a later iteration of a loop.
Calling a routine / returning from a routine changes the state.
Entering / leaving a loop changes the state.
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The pointer to the active row.
States
valid id index
0 0 0
0 0 0
0 0 0
→ 1 1 0
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Is the row valid?
States
valid id index
0 0 0
0 0 0
0 0 0
→ 1 1 0
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The id identifies a loop or a routine.
States
valid id index
0 0 0
0 0 0
0 0 0
→ 1 1 0
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The index discriminates between first and further iterations.
States
valid id index
0 0 0
0 0 0
0 0 0
→ 1 1 0
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valid id index
0 0 0
0 0 0
0 0 0
→ 1 1 0
State Transformations
(0x1004, 1, 0, 0, 1, 1, 0, 0)
(0x2000, 2, 1, 0, 0, 1, 0, 0)
Routine Call,
Increased Loop Nesting Level
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valid id index
0 0 0
→ 1 2 0
0 0 0
1 1 0
valid id index
0 0 0
0 0 0
0 0 0
→ 1 1 0
State Transformations
(0x1004, 1, 0, 0, 1, 1, 0, 0)
(0x2000, 2, 1, 0, 0, 1, 0, 0)
Routine Call,
Increased Loop Nesting Level
![Page 49: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/49.jpg)
valid id index
0 0 0
→ 1 2 0
0 0 0
1 1 0
State Transformations
(0x2000, 2, 1, 0, 0, 1, 0, 0)
(0x202c, 3, 2, 0, 0, 0, 0, 0)
Entering a loop
![Page 50: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/50.jpg)
valid id index
→ 1 3 0
1 2 0
0 0 0
1 1 0
valid id index
0 0 0
→ 1 2 0
0 0 0
1 1 0
State Transformations
(0x2000, 2, 1, 0, 0, 1, 0, 0)
(0x202c, 3, 2, 0, 0, 0, 0, 0)
Entering a loop
![Page 51: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/51.jpg)
valid id index
→ 1 3 0
1 2 0
0 0 0
1 1 0
State Transformations
(0x2034, 4, 2, 0, 0, 0, 0, 0)
(0x202c, 3, 2, 0, 0, 0, 0, 0)
Recursively entering a loop
![Page 52: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/52.jpg)
valid id index
→ 1 3 1
1 2 0
0 0 0
1 1 0
valid id index
→ 1 3 0
1 2 0
0 0 0
1 1 0
State Transformations
(0x2034, 4, 2, 0, 0, 0, 0, 0)
(0x202c, 3, 2, 0, 0, 0, 0, 0)
Recursively entering a loop
![Page 53: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/53.jpg)
valid id index
→ 1 3 1
1 2 0
0 0 0
1 1 0
State Transformations
(0x202c, 3, 2, 0, 0, 0, 0, 0)
(0x2050, 5, 2, 1, 0, 0, 0, 0)
Entering a different loop
![Page 54: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/54.jpg)
valid id index
→ 1 5 0
1 2 0
0 0 0
1 1 0
valid id index
→ 1 3 1
1 2 0
0 0 0
1 1 0
State Transformations
(0x202c, 3, 2, 0, 0, 0, 0, 0)
(0x2050, 5, 2, 1, 0, 0, 0, 0)
Entering a different loop
![Page 55: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/55.jpg)
valid id index
→ 1 5 1
1 2 0
0 0 0
1 1 0
State Transformations
(0x2050, 5, 2, 1, 0, 0, 0, 0)
(0x206c, 7, 1, 0, 0, 0, 0, 0)
Leaving a loop
![Page 56: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/56.jpg)
valid id index
0 0 0
→ 1 2 0
0 0 0
1 1 0
valid id index
→ 1 5 1
1 2 0
0 0 0
1 1 0
State Transformations
(0x2050, 5, 2, 1, 0, 0, 0, 0)
(0x206c, 7, 1, 0, 0, 0, 0, 0)
Leaving a loop
![Page 57: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/57.jpg)
valid id index
0 0 0
→ 1 2 0
0 0 0
1 1 0
State Transformations
(0x206c, 7, 1, 0, 0, 0, 0, 0)
(0x207c, 8, 0, 0, 0, 0, 1, 0)
Leaving a loop
![Page 58: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/58.jpg)
valid id index
0 0 0
0 0 0
→ 1 8 0
1 1 0
valid id index
0 0 0
→ 1 2 0
0 0 0
1 1 0
State Transformations
(0x206c, 7, 1, 0, 0, 0, 0, 0)
(0x207c, 8, 0, 0, 0, 0, 1, 0)
Leaving a loop
![Page 59: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/59.jpg)
valid id index
0 0 0
0 0 0
→ 1 8 0
1 1 0
State Transformations
(0x207c, 8, 0, 0, 0, 0, 1, 0)
(0x101c, 9, 0, 0, 0, 0, 1, 1)
Leaving a routine
![Page 60: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/60.jpg)
valid id index
0 0 0
0 0 0
0 0 0
→ 1 1 0
valid id index
0 0 0
0 0 0
→ 1 8 0
1 1 0
State Transformations
(0x207c, 8, 0, 0, 0, 0, 1, 0)
(0x101c, 9, 0, 0, 0, 0, 1, 1)
Leaving a routine
![Page 61: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/61.jpg)
Example
![Page 62: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/62.jpg)
valid id index
0 0 0
0 0 0
0 0 0
→ 0 0 0
Example
(?, ?, ?, ?, 1, ?, ?, ?)
first further
1 0 0
2 0 0
3 0 0
4 0 0
5 0 0
6 0 0
7 0 0
8 0 0
9 0 0
![Page 63: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/63.jpg)
valid id index
0 0 0
0 0 0
0 0 0
→ 1 1 0
Example
(?, ?, ?, ?, 1, ?, ?, ?)
(0x1004, 1, 0, 0, 1, 1, 0, 0) @ t+0
first further
1 0 0
2 0 0
3 0 0
4 0 0
5 0 0
6 0 0
7 0 0
8 0 0
9 0 0
![Page 64: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/64.jpg)
valid id index
0 0 0
→ 1 2 0
0 0 0
1 1 0
Example
(0x1004, 1, 0, 0, 1, 1, 0, 0) @ t+0
(0x2000, 2, 1, 0, 0, 1, 0, 0) @ t+8
first further
1 8 0
2 0 0
3 0 0
4 0 0
5 0 0
6 0 0
7 0 0
8 0 0
9 0 0
![Page 65: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/65.jpg)
valid id index
→ 1 3 0
1 2 0
0 0 0
1 1 0
Example
(0x2000, 2, 1, 0, 0, 1, 0, 0) @ t+8
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+30
first further
1 8 0
2 22 0
3 0 0
4 0 0
5 0 0
6 0 0
7 0 0
8 0 0
9 0 0
![Page 66: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/66.jpg)
valid id index
→ 1 3 0
1 2 0
0 0 0
1 1 0
Example
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+30
(0x2034, 4, 2, 0, 0, 0, 0, 0) @ t+46
first further
1 8 0
2 22 0
3 16 0
4 0 0
5 0 0
6 0 0
7 0 0
8 0 0
9 0 0
![Page 67: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/67.jpg)
valid id index
→ 1 3 1
1 2 0
0 0 0
1 1 0
Example
(0x2034, 4, 2, 0, 0, 0, 0, 0) @ t+46
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+48
first further
1 8 0
2 22 0
3 16 0
4 2 0
5 0 0
6 0 0
7 0 0
8 0 0
9 0 0
![Page 68: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/68.jpg)
valid id index
→ 1 3 1
1 2 0
0 0 0
1 1 0
Example
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+48
(0x2034, 4, 2, 0, 0, 0, 0, 0) @ t+56
first further
1 8 0
2 22 0
3 16 8
4 2 0
5 0 0
6 0 0
7 0 0
8 0 0
9 0 0
![Page 69: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/69.jpg)
valid id index
→ 1 3 1
1 2 0
0 0 0
1 1 0
Example
(0x2034, 4, 2, 0, 0, 0, 0, 0) @ t+56
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+57
first further
1 8 0
2 22 0
3 16 8
4 2 1
5 0 0
6 0 0
7 0 0
8 0 0
9 0 0
![Page 70: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/70.jpg)
valid id index
→ 1 5 0
1 2 0
0 0 0
1 1 0
Example
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+57
(0x2050, 5, 2, 1, 0, 0, 0, 0) @ t+59
first further
1 8 0
2 22 0
3 16 8
4 2 1
5 0 0
6 0 0
7 0 0
8 0 0
9 0 0
![Page 71: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/71.jpg)
valid id index
→ 1 5 0
1 2 0
0 0 0
1 1 0
Example
(0x2050, 5, 2, 1, 0, 0, 0, 0) @ t+59
(0x205c, 6, 2, 1, 0, 0, 0, 0) @ t+71
first further
1 8 0
2 22 0
3 16 8
4 2 1
5 12 0
6 0 0
7 0 0
8 0 0
9 0 0
![Page 72: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/72.jpg)
valid id index
→ 1 5 1
1 2 0
0 0 0
1 1 0
Example
(0x205c, 6, 2, 1, 0, 0, 0, 0) @ t+71
(0x2050, 5, 2, 1, 0, 0, 0, 0) @ t+73
first further
1 8 0
2 22 0
3 16 8
4 2 1
5 12 0
6 2 0
7 0 0
8 0 0
9 0 0
![Page 73: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/73.jpg)
valid id index
→ 1 5 1
1 2 0
0 0 0
1 1 0
Example
(0x2050, 5, 2, 1, 0, 0, 0, 0) @ t+73
(0x205c, 6, 2, 1, 0, 0, 0, 0) @ t+79
first further
1 8 0
2 22 0
3 16 8
4 2 1
5 12 6
6 2 0
7 0 0
8 0 0
9 0 0
![Page 74: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/74.jpg)
valid id index
→ 1 5 1
1 2 0
0 0 0
1 1 0
Example
(0x205c, 6, 2, 1, 0, 0, 0, 0) @ t+79
(0x2050, 5, 2, 1, 0, 0, 0, 0) @ t+80
first further
1 8 0
2 22 0
3 16 8
4 2 1
5 12 6
6 2 1
7 0 0
8 0 0
9 0 0
![Page 75: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/75.jpg)
valid id index
0 0 0
→ 1 2 0
0 0 0
1 1 0
Example
(0x2050, 5, 2, 1, 0, 0, 0, 0) @ t+80
(0x206c, 7, 1, 0, 0, 0, 0, 0) @ t+83
first further
1 8 0
2 22 0
3 16 8
4 2 1
5 12 6
6 2 1
7 0 0
8 0 0
9 0 0
![Page 76: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/76.jpg)
valid id index
0 0 0
→ 1 2 1
0 0 0
1 1 0
Example
(0x206c, 7, 1, 0, 0, 0, 0, 0) @ t+83
(0x2000, 2, 1, 0, 0, 1, 0, 0) @ t+91
first further
1 8 0
2 22 0
3 16 8
4 2 1
5 12 6
6 2 1
7 8 0
8 0 0
9 0 0
![Page 77: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/77.jpg)
valid id index
→ 1 3 0
1 2 1
0 0 0
1 1 0
Example
(0x2000, 2, 1, 0, 0, 1, 0, 0) @ t+91
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+102
first further
1 8 0
2 22 11
3 16 8
4 2 1
5 12 6
6 2 1
7 8 0
8 0 0
9 0 0
![Page 78: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/78.jpg)
valid id index
→ 1 3 0
1 2 1
0 0 0
1 1 0
Example
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+102
(0x2034, 4, 2, 0, 0, 0, 0, 0) @ t+110
first further
1 8 0
2 22 11
3 16 8
4 2 1
5 12 6
6 2 1
7 8 0
8 0 0
9 0 0
![Page 79: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/79.jpg)
valid id index
→ 1 3 1
1 2 1
0 0 0
1 1 0
Example
(0x2034, 4, 2, 0, 0, 0, 0, 0) @ t+110
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+112
first further
1 8 0
2 22 11
3 16 8
4 2 1
5 12 6
6 2 1
7 8 0
8 0 0
9 0 0
![Page 80: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/80.jpg)
valid id index
→ 1 3 1
1 2 1
0 0 0
1 1 0
Example
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+112
(0x2034, 4, 2, 0, 0, 0, 0, 0) @ t+119
first further
1 8 0
2 22 11
3 16 8
4 2 1
5 12 6
6 2 1
7 8 0
8 0 0
9 0 0
![Page 81: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/81.jpg)
valid id index
→ 1 3 1
1 2 1
0 0 0
1 1 0
Example
(0x2034, 4, 2, 0, 0, 0, 0, 0) @ t+119
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+120
first further
1 8 0
2 22 11
3 16 8
4 2 1
5 12 6
6 2 1
7 8 0
8 0 0
9 0 0
![Page 82: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/82.jpg)
valid id index
→ 1 5 0
1 2 1
0 0 0
1 1 0
Example
(0x202c, 3, 2, 0, 0, 0, 0, 0) @ t+120
(0x2050, 5, 2, 1, 0, 0, 0, 0) @ t+122
first further
1 8 0
2 22 11
3 16 8
4 2 1
5 12 6
6 2 1
7 8 0
8 0 0
9 0 0
![Page 83: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/83.jpg)
valid id index
→ 1 5 0
1 2 1
0 0 0
1 1 0
Example
(0x2050, 5, 2, 1, 0, 0, 0, 0) @ t+122
(0x205c, 6, 2, 1, 0, 0, 0, 0) @ t+126
first further
1 8 0
2 22 11
3 16 8
4 2 1
5 12 6
6 2 1
7 8 0
8 0 0
9 0 0
![Page 84: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/84.jpg)
valid id index
→ 1 5 1
1 2 1
0 0 0
1 1 0
Example
(0x205c, 6, 2, 1, 0, 0, 0, 0) @ t+126
(0x2050, 5, 2, 1, 0, 0, 0, 0) @ t+127
first further
1 8 0
2 22 11
3 16 8
4 2 1
5 12 6
6 2 1
7 8 0
8 0 0
9 0 0
![Page 85: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/85.jpg)
valid id index
→ 1 5 1
1 2 1
0 0 0
1 1 0
Example
(0x2050, 5, 2, 1, 0, 0, 0, 0) @ t+127
(0x205c, 6, 2, 1, 0, 0, 0, 0) @ t+135
first further
1 8 0
2 22 11
3 16 8
4 2 1
5 12 8
6 2 1
7 8 0
8 0 0
9 0 0
![Page 86: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/86.jpg)
valid id index
→ 1 5 1
1 2 1
0 0 0
1 1 0
Example
(0x205c, 6, 2, 1, 0, 0, 0, 0) @ t+135
(0x2050, 5, 2, 1, 0, 0, 0, 0) @ t+136
first further
1 8 0
2 22 11
3 16 8
4 2 1
5 12 8
6 2 1
7 8 0
8 0 0
9 0 0
![Page 87: Precise Continuous Non-Intrusive Measurement-Based Execution … · 2016. 9. 30. · Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement](https://reader036.vdocuments.site/reader036/viewer/2022071110/5fe4d8398f34031ee508f492/html5/thumbnails/87.jpg)
valid id index
0 0 0
→ 1 2 1
0 0 0
1 1 0
Example
(0x2050, 5, 2, 1, 0, 0, 0, 0) @ t+136
(0x206c, 7, 1, 0, 0, 0, 0, 0) @ t+139
first further
1 8 0
2 22 11
3 16 8
4 2 1
5 12 8
6 2 1
7 8 0
8 0 0
9 0 0
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valid id index
0 0 0
0 0 0
→ 1 8 0
1 1 0
Example
(0x206c, 7, 1, 0, 0, 0, 0, 0) @ t+139
(0x207c, 8, 0, 0, 0, 0, 1, 0) @ t+143
first further
1 8 0
2 22 11
3 16 8
4 2 1
5 12 8
6 2 1
7 8 4
8 0 0
9 0 0
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valid id index
0 0 0
0 0 0
0 0 0
→ 1 1 0
Example
(0x207c, 8, 0, 0, 0, 0, 1, 0) @ t+143
(0x101c, 9, 0, 0, 0, 0, 1, 1) @ t+149
first further
1 8 0
2 22 11
3 16 8
4 2 1
5 12 8
6 2 1
7 8 4
8 6 0
9 0 0
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valid id index
0 0 0
0 0 0
0 0 0
→ 0 0 0
Example
(0x101c, 9, 0, 0, 0, 0, 1, 1) @ t+149
(?, ?, ?, ?, ?, ?, ?, 1) @ t+155
first further
1 8 0
2 22 11
3 16 8
4 2 1
5 12 8
6 2 1
7 8 4
8 6 0
9 6 0
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Example first further
1 8 0
2 22 11
3 16 8
4 2 1
5 12 8
6 2 1
7 8 4
8 6 0
9 6 0
Overall execution time estimate:
Our method: 191 cycles
Context insensitive: 258 cycles
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Implementation
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FPGA Implementation
We are currently building a prototype based on a Xilinx Virtex 7 FPGA (xc7v585t) and RLDRAM.
Most complicated part is the connection to the SoC‘s trace interface (i.e. event generation).
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Resource Usage on FPGA
Loop Iteration State Machine (~ 180 MHz)
3 BRAMs
470 Registers
398 LUTs
Statistics Module (~ 130 MHz)
7 BRAMs
481 Registers
406 LUTs
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Conclusion
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The CONIRAS Approach
Precise
We account for typical (instruction) cache behaviour.
Continuous
We perform direct online aggretation at runtime.
Non-intrusive
We use the hardware support of modern SoCs.
Measurement-Based Execution Time Estimation
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The CONIRAS Approach
⇒ Reduced pessimism
⇒ Improved observability
⇒ Scalability
⇒ Statistics instead of piles of data
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98