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Power Minimization using Simultaneous Gate Sizing, Dual-Vdd and Dual-
Vth Assignment
Ashish Srivastava, Dennis Sylvester, David Blaauw
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Outline
Introduction Preliminary Algorithm Experimental Results Conclusions
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Introduction
Gate size => Delay Power VDD => Delay Power
VTH => Delay Power
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Outline
Introduction Preliminary
Dual Vdd constraint Cluster Voltage Scaling (CVS)
Algorithm Experimental Results Conclusions
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Dual Vdd Constraint
N1
MP1
MN1
Static current
VDDL<VDDH-|Vtp|=>PMOS can not be cut-off
01
ON
VDDLVDDH
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Cluster Voltage Scaling (CVS)
6
3
1
4
2
5 8
9
7
10
i1
i2
i3
i4
i5
o1
o2
o3
o4
VDDHVDDL
LC
LC
LC
LC
Level Converter
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Cluster Voltage Scaling (CVS)
6
3
1
4
2
5 8
9
7
10
i1
i2
i3
i4
i5
o1
o2
o3
o4
VDDH VDDL
{O1,o2,o3,o4}
Order by Capacitance or Slack
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Outline
Introduction Preliminary Algorithm - VVS
Backward Pass Frontward Pass
Experimental Results Conclusions
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Outline
Introduction Preliminary Algorithm
Backward Pass Frontward Pass
Experimental Results Conclusions
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Backward Pass
Change cells from high VDD to low VDD
Dual Vdd & single Vth
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Backward Pass
Step1 CVS without gate upsizing
Step2 with gate upsizing
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Backward Pass
Step1 CVS
VDDH VDDL
4
26
5
1
73
8
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Backward Pass
Step 2 Backward front
VDDH VDDL
4
26
57
3
8
High VddGate Upsizing
Slack1
arcs arc kSSlack
D
pySensitivit
min
1
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Backward Pass
Escape local minima. Find the globe minima.
The front between high and low Vdd gates is in the best position in terms of the total power dissipation for a dual Vdd, single Vth.
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Outline
Introduction Preliminary Algorithm
Backward Pass Frontward Pass
Experimental Results Conclusions
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Forward Pass
Select a gate to high Vdd or upsizeing
Set gates to high Vth
Power Reduce?
Accept this move
Yes No
Reverse this move
Create timing slack
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Forward Pass
How to select a gate to high Vdd or to up-sizing?
arcs arc kSSlack
D
pySensitivit
min
1
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Forward Pass
How to select a gate to high Vth?
arcs
arc
D
SlackPySensitivit
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Outline
Introduction Preliminary Algorithm Experimental Results Conclusions
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Experimental Results % Savings compared to initial design
Initial Power (uW) CVS only Backward Pass VVS
Circuit
Leakage
Switching
TotalLeaka
ge
Switching
TotalLeaka
ge
Switching
TotalLeaka
ge
Switching
Total
c432 35.4 81.7117.
10.50% 1.90%
1.50%
0.50% 1.90%1.50
%57.80
%6.00%
21.70%
c880 48.9 140.1188.
920.60
%19.80%
20.00%
20.60%
19.80%20.00
%44.00
%22.90%
28.40%
c1908 75.3 202.7 278 5.40% 5.60%5.50
%5.40% 5.60%
5.50%
44.10%
7.40%17.40
%
c2670 100 248.9 34920.30
%21.40%
21.10%
20.20%
37.80%32.70
%20.20
%37.80%
32.70%
c3540 131.6 302.6434.
23.40% 6.50%
5.60%
2.80% 26.40%19.20
%49.40
%26.10%
33.20%
c5315 210.9 413.8624.
721.20
%25.40%
23.90%
18.90%
50.50%39.90
%19.00
%50.70%
40.00%
c6288 544.3 1716.22260
.5
1.10% 15.70%12.20
%1.00% 15.80%
12.20%
20.30%
19.40%19.60
%
c7552 214.9 521.4736.
330.20
%32.70%
32.00%
36.40%
50.80%46.60
%36.60
%51.20%
46.90%
Average
12.80%
16.10%15.20
%13.20
%26.10%
22.20%
36.40%
27.70%30.00
%
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Experimental Results
The nominal activity is adjusted such the leakage power constitutes approximately 8% of the total power dissipation.
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Experimental Results
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Outline
Introduction Preliminary Algorithm Experimental Results Conclusions
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Conclusions
The VVS algorithm combines gate sizing with Vdd and Vth assignment to minimize the total power dissipation.