OFDM AND SOQPSK TRANSCEIVER HARDWAREIMPLEMENTATION WITH PRELIMINARY RESULTS
Item Type text; Proceedings
Authors Wang, Enkuang D.; Brothers, Timothy J.
Publisher International Foundation for Telemetering
Journal International Telemetering Conference Proceedings
Rights Copyright © held by the author; distribution rights InternationalFoundation for Telemetering
Download date 28/01/2021 06:34:26
Link to Item http://hdl.handle.net/10150/624249
OFDM AND SOQPSK TRANSCEIVER HARDWARE
IMPLEMENTATION WITH PRELIMINARY RESULTS
Enkuang D Wang and Timothy J Brothers Georgia Tech Research Institute
Atlanta, Georgia 30318
{enkuang.wang, timothy.brothers}@gtri.gatech.edu
ABSTRACT
This paper presents a hardware implementation of a transceiver capable of both orthogonal
frequency-division multiplexing (OFDM) and shaped-offset quadrature phase shift keying
(SOQPSK) transmissions using a dataflow programming language. Based on the physical layer
iNET standard, we introduce a transceiver implementation that utilizes both waveforms with low
density parity check (LDPC) forward error correction (FEC) codes. This testbed is intended to test
and enable an adaptive algorithm that uses both waveforms as its modulation schemes. As such, it
has the ability to dynamically select various modulation parameters and coding rates. The
hardware implementations are described and performance utilizations are presented.
INTRODUCTION
The migration toward the integrated network enhanced telemetry (iNET) system introduces a new
challenge of defining adaptive modulation and coding algorithms for the telemetry community.
Adaptive modulation and coding scheme has been widely used in several Long Term Evolution
(LTE) and WiFi standards [1-2]. Similar adaptive algorithms have yet been applied to aeronautical
telemetry. In order to accomplish this task, the adaptive algorithm must employ two completely
different modulation waveforms defined in iNET: 1) telemetry group SOQPSK (SOQPSK-TG)
and 2) OFDM. Solving this task involves an initiation of a multi-scheme adaptation, in which both
SOQPSK and OFDM are used under the same decision rule. The Georgia Tech Research Institute
(GTRI) has investigated adaptive modulation and coding scheme for aeronautical telemetry,
developed an algorithm that employs both modulation types, and validated its performance via
simulations. The performance of an adaptive scheme has shown to have 30% to 340% goodput
performance improvement over a baseline scheme in various static telemetry channel models [3].
To further raise the technology readiness level (TRL) of using adaptive schemes in aeronautical
telemetry, GTRI continued this effort by implementing the design onto a software defined radio
(SDR) platform for laboratory demonstration. This SDR hardware comprises of a National
Instrument (NI) PXIe-7975R FlexRIO FPGA module, a NI 5791 RF transceiver module, and a NI
8135 controller and the software is the LabVIEW Communication Systems Design Suite.
This paper focuses on the hardware implementation of [3], including both the transceiver
architecture and the adaptive scheme. The implementation involves building both OFDM and
SOQPSK transceivers onto the same FPGA, such that we can use a single processing unit to drive
the adaptation across both modulation schemes. We also present a simplified version of the
adaptive algorithm that employs both waveforms in an AWGN channel. The last part of this paper
presents the results of the adaptive scheme along with hardware resource utilizations.
HARDWARE SYSTEM ARCHITECTURE
A. Overall System Architecture
This section details the transmitter and receiver modules of the Link Dependent Adaptive Radio
(LDAR) transceiver. The general building blocks for the transceiver are derived from the iNET
standard, which includes SOQPSK-TG as the single-carrier waveform and OFDM as the multi-
carrier waveform. A low density parity check (LDPC) code [4] is used as the primary FEC code.
The overall transceiver system architecture is shown in Figure 1, where the upper box shows the
transmitter system modules and the lower box highlights the receiver blocks. As seen from this
figure, the transceiver assigns the signal processing modules to both the controller and the FPGA.
The following sub-sections include a brief description and derivation to each of the individual
modules shown in Figure 1.
Figure 1. LDAR transceiver top-level system architecture.
B. Transmitter
As shown in Figure 1, the modules for the transmitter consist of input data generator, LDPC
encoder, OFDM modulator, and SOQPSK modulator. Based on the modulation and coding scheme
(MCS) signal generated from the LDAR adapter at the controller, the encoded codewords are either
modulated as OFDM or SOQPSK signals.
1. LDPC Encoder
The LDPC encoding algorithm we used is defined in the iNET specification [5], which is done by
cyclically shifting the first row of each sub-matrices of the generator matrix per one encoding
iteration. Since it has eight 256-bit shift registers, it takes a total of 4096 iterations to complete the
encoding process for a 2/3 LDPC codeword. The encoder was initially implemented on the FPGA.
However, due to memory issues of the FPGA compiler, the design was unable to be compiled into
a bitfile. Thus, the design was moved to the controller. Table 1 shows the estimated FPGA resource
utilizations for the 2/3 LDPC encoder.
Table 1. 2/3 LDPC Encoder FPGA Resource Utilization
Block RAMs 4/795
DSP48s 0/1540
Flip Flops 13,247/508,400 (2.60 %)
Look-Up Tables 21,676/254,200 (8.53 %)
Throughput (Mb/s) 250
Clock Rate (MHz) 265
2. OFDM and SOQPSK Modulators
Both of the modulators were implemented on the FPGA. For OFDM, the bits are first grouped into
their respective in-phase and quadrature (IQ) components. These IQ symbols are then sent to the
OFDM modulator as data subcarriers. The general design flow for an OFDM modulator is shown
in Figure 2. The IQ data symbols are first interleaved with the pilot subcarriers and OFDM zero-
paddings. An inverse fast Fourier transform (IFFT) is taken and the cyclic prefix (CP) is prepended
to the interleaved signal. The last stage of the OFDM modulator is to prepend the pre-computed
time-domain attached synchronization marker (ASM), short training sequences (STS), and long
training sequences (LTS) to the time-domain signals.
Figure 2. OFDM modulation flow diagram.
For the SOQPSK modulator, since the information is carried in the phase differences of the signal,
the design flow (shown in Figure 3) is different from that of the OFDM modulator. The preambles
are prepended to the input bits at the start of the modulator. The interleaved streams are then passed
to the precoder to generate ternary symbols. These symbols are then up-sampled by 2, convolved
with the frequency pulse filter, and ran through a discrete-time integrator. The last block is to
convert the phase signals to time-domain waveforms via a polar to Cartesian conversion.
Figure 3. SOQPSK modulation flow diagram.
C. Receiver
Similar to the transmitter, the receiver signal processing blocks are divided into the FPGA and the
host controller. As shown in the bottom of Figure 1, the receiver is comprised of an OFDM receiver
and a SOQPSK receiver. Depending on the MCS signal, the received signals become the input to
the respective receiver.
1. Matched Filter and Burst Detector
The first two modules for both receivers are identical, in which both have a matched filter and a
burst detector. For OFDM, the matched filter coefficients are the conjugated time-reversed version
of the modulated iNET ASM coefficients. For SOQPSK, the optimal preambles, defined in [6],
are used as the matched filter coefficients. After the received signals are convolved with the
matched filter, the filter output is compared to a threshold at the burst detector. If the filter output
magnitude exceeds the threshold, then the received signals are considered valid for a burst length.
The burst lengths used are shown in Table 2. As seen from Table 2, the number of codeblocks for
each modulation is different. This is due to a design constraint stemming from the multirate
dataflow language of the LabVIEW software, in which the input IQ symbols and output of a
particular module has to be the same.
Table 2. Input and Output Lengths for Each Modulation Type
Modulation # of Input Bits # of Input IQ Symbols # of Output Samples
OFDM - QPSK 12288 6144 10624
OFDM - 16 QAM 24576 6144 10624
OFDM - 64 QAM 36864 6144 10624
SOQPSK 6144 N/A 12568
2. OFDM Receiver
The OFDM demodulation flow diagram is shown in Figure 4. After it receives the samples from
the burst detector, it estimates and corrects the carrier frequency offset (CFO) of the received signal
via the STS. Next, an FFT is used to transform the time-domain signal to the frequency-domain.
In the frequency domain, the LTS is examined to estimate the channel and create a one-tap least
squares (LS) equalizer. The last block of the OFDM receiver is the quadrature amplitude
modulation (QAM) or quadrature phase shift keying (QPSK) de-mapper, where the log-likelihood
ratios (LLRs) for the encoded bits are generated from the received IQ symbols.
Figure 4. OFDM receiver processing blocks.
3. SOQPSK Receiver
The SOQPSK receiver processing flow is illustrated in Figure 5. The received samples and phase
signal come from the burst detector. For SOQPSK, the phase offset is estimated from the very first
phase sample after the peak threshold is detected. The detected phase offset is used to correct the
phase offset of the entire received signal burst. After the phase correction, a simple offset QPSK
(OQPSK) detector is used to detect the signal. To do this, a –π/4 phase correction has to be applied
to the received signal such that the constellations are rotated to look similar to an OQPSK
constellation. With a phase-rotated constellation, the demodulator can follow the simple decision
rule shown in (1), where 𝑟[𝑘] is the LLR of the demodulated SOQPSK sample 𝑦[𝑘].
Figure 5. SOQPSK receiver processing blocks.
𝑟[𝑘] = {𝑅𝑒{𝑦[𝑘]}
𝐼𝑚{𝑦[𝑘]}𝑘 𝑒𝑣𝑒𝑛𝑘 𝑜𝑑𝑑
(1)
4. EVM, Dispersion, and SNR Calculators
Once the received samples are demodulated into their respective LLRs, these values are then used
to estimate the signal-to-noise ratio (SNR) of the channel. The equation for the error vector
magnitude (EVM) and dispersion are defined in (2) and (3), respectively. For EVM, 𝑁𝑠 is the
number of symbols over which EVM is averaged, 𝑆𝑡,𝑖 is the transmitted symbol, 𝑆𝑟,𝑖 is the received
symbol. For dispersion, 𝑦𝑛 is the received symbol. Here we assume the received SOQPSK signal
is equalized; therefore, the IQ samples reside very closely to the unit circle. Based on a mapping
between EVM and dispersion defined in [7], the EVMs can be mapped to their corresponding
dispersion values via (4). Using dispersion, the SNR of an additive white Gaussian noise (AWGN)
channel can be estimated using (5), which is a regression line that was generated from the
theoretical dispersion vs SNR plot shown in Figure 6. The estimated SNR is then fed as an input
to the LDAR adapter at the controller.
𝐸𝑉𝑀 =
1𝑁𝑠
∑ |𝑆𝑟,𝑖 − 𝑆𝑡,𝑖|2𝑁𝑠
𝑖=1
1𝑁𝑠
∑ |𝑆𝑡,𝑖|2𝑁𝑠
𝑖=1
(2)
𝐷𝑖𝑠𝑝𝑒𝑟𝑠𝑖𝑜𝑛 = 𝐸[(|𝑦𝑛|2 − 1)2] (3)
𝐷𝑖𝑠𝑝𝑒𝑟𝑠𝑖𝑜𝑛𝑎𝑤𝑔𝑛 = 2[(𝐸𝑉𝑀)2 + 𝐸𝑉𝑀] (4)
𝑆𝑁𝑅𝑑𝐵̂ = −4 𝑙𝑛(𝐷𝑖𝑠𝑝𝑒𝑟𝑠𝑖𝑜𝑛𝑎𝑤𝑔𝑛) + 4.5 (5)
Figure 6. Plot of dispersion vs various SNRs and its regression line.
5. LDPC Decoder
Similar to the LDPC encoder, the LDPC decoder was initially developed to be implemented on
the FPGA, but due to resource constraints, it was moved to the controller. The estimated FPGA
resource utilizations and throughput are shown in Table 3. The FPGA LDPC decoder can achieve
a throughput of 320 Mbps, but if the LDPC decoder is ran on the host controller, the achievable
throughput is dropped to just 1.36 Mbps for one decoding iteration. The limitation of running the
decoder on the host is that it does not meet the throughput constraint of 160 Mbps. The LDPC
decoding algorithm is shown below:
Algorithm 1. LDPC Decode Algorithm for Both FPGA and Host Controller
1. 𝒑𝒋𝟎 = 𝑳𝑳𝑹𝒋 (5)
2. 𝑪𝑻𝑽𝒊𝒋𝟎 = 𝟎 (6)
3. 𝑽𝑻𝑪𝒊𝒋𝒕 = 𝒑𝒋
𝒕−𝟏 − 𝑪𝑻𝑽𝒊𝒋𝒕−𝟏 (7)
4. 𝑪𝑻𝑽𝒊𝒋𝒕 = 𝟎. 𝟕𝟓 ∏ 𝒔𝒊𝒈𝒏(𝑽𝑻𝑪𝒊𝒌
𝒕 ) 𝒎𝒊𝒏𝒌∈ℵ(𝒊)\{𝒋}
{|𝑽𝑻𝑪𝒊𝒌𝒕 |}𝒌∈ℵ(𝒊)\{𝒋} (8)
5. 𝒑𝒋𝒕 = 𝑽𝑻𝑪𝒊𝒋
𝒕 + 𝑪𝑻𝑽𝒊𝒋𝒕 (9)
As seen from the above algorithm, we implemented the scaled-min-sum algorithm (MSA) [8]. The
a posteriori probability (APP) 𝑝𝑗𝑡 is initialized as 𝐿𝐿𝑅𝑗 log-likelihood ratio, and the check-to-
variable node update 𝐶𝑇𝑉𝑖𝑗𝑡 is initialized as all 0. At tth iteration, the variable-to-check node update
𝑉𝑇𝐶𝑖𝑗𝑡 is defined in (7), and 𝑘 ∈ ℵ(𝑖)\{𝑗} is the set of variable node neighbors of check node 𝑖
excluding variable node 𝑗. Since the parity check matrix H (PCM H) of this particular LDPC has
a sub-matrix that consists of only one edge between each check node (CN) and variable node (VN),
this algorithm can effectively increase the throughput by 256, size of the sub-matrix. The PCM H
used for this 2/3 LDPC decoder is a 3072⨯6144 matrix defined in iNET.
Table 3. FPGA Utilizations and Throughput for 2/3-rate LDPC Decoder
BRAMs 40/795
DSP48s 0/1540
Flip Flops 43,633/508,400 (8.58%)
Look-Up Tables 49,863/254,200 (19.62%)
Throughput (Mb/s) 320
Clock Rate (MHz) 415
6. LDAR Adapter
The LDAR adapter module at the controller is used for selecting MCS signal that best
accommodates the current channel condition. For this particular development phase, the only
source of channel degradation being introduced is the AWGN noise. Thus, if the adapter sees
significant SNR changes, it would pick a new MCS signal. If the estimated SNR is similar to the
previous value, the adapter would not pick a new MCS signal. The same MCS signal is fed to both
the controller for LDPC selection and the FPGA for modulation selection. The LDAR decision
rule is shown in Table 5 under the Adaptive Algorithm section.
D. Transceiver Hardware Utilizations The total FPGA resource utilizations are shown in Table 4. As shown in Figure 1 and described from
previous sub-sections, the FPGA is primarily responsible for modulate and demodulate waveforms in
addition to compute the channel metrics, such as EVM, dispersion, and SNR. The total resource utilizations
in Table 4 do not include the estimated resource usages of the LDPC encoder and decoder modules.
Table 4. Total FPGA Resource Utilizations
Registers 185,566/504,400 (36%)
DSPs 499/1540 (32%)
Block RAMs 501/795 (63%)
LUTs 144,928/254,200 (56%)
Total Slices 55,205/63,550 (87%)
ADAPTIVE ALGORITHM
Since the objective is to demonstrate adaptive modulation and coding via cables in a laboratory
environment, the adaptive algorithm was designed and modified for AWGN channels. To generate
a set of empirical decision rules, the bit error rate (BER) vs SNR plot, shown in Figure 7, is used.
This figure shows the simulated BER vs SNR curves for every combination of modulation and
code rates. Using this figure and a given BER threshold, the operational SNR regions for each
MCS can be identified. The BER threshold was chosen to be 1⨯10-5. This means that if the BER
is less than the threshold, the MCS is considered reliable. Based on the simulation results, a near-
optimal decision rule was created and shown in Table 5. Since only the 2/3 LDPC is considered
for the laboratory demonstration, Table 5 only includes the regions for modulations with 2/3 LDPC
and no FEC encoding.
Table 5. Achieved Decision Rule Table for AWGN Channel
SNR (dB) Transmission Mode Throughput (Mbps)
-5 to 3 SOQPSK 2/3 5
4 SOQPSK 7.5
5 to 10 QPSK 2/3 12.8
11 to 14 QPSK 19.2
15 to 18 16 QAM 2/3 25.6
19 to 24 16 QAM 38.4
25+ 64 QAM 57.6
Figure 7. BER vs SNR for every LDAR MCS.
LABORATORY DEMONSTRATION SETUP AND RESULTS
The LDAR demonstration setup is shown in Figure 8. To clearly show the performance
improvement achieved by using the LDAR adaptive modulation, we will compare its performance
with that of a fixed modulation using the same RF channel. Two NI 5791 RF transceivers (and
associated FPGAs) are configured for loopback testing, in which an RF signal generator produces
AWGN noise. This allows us to produce a given, known amount of SNR for both transceiver
channels. The first transceiver uses LDAR, that is, its modulation adapts to the changing channel
SNR as measured by EVM or dispersion metrics, employing SOQPSK and OFDM constellations.
The second transceiver uses a fixed scheme, which is user selectable. The user can view the real-
time, achieved throughput and burst throughput on side by side monitors.
LDAR Host Controller
RF Front End
TX RX
Fixed-Mod Host Controller
RF Front End
TX RX
RF Noise GeneratorSplitter / Combiner
Splitter / CombinerSplitter / Combiner
Performance Displays
Figure 8. LDAR laboratory demonstration setup.
The resulting “good” burst throughput for each MCS at various SNRs is recorded by manually
adjusting the noise power level and is shown in Figure 9. In this figure, each MCS has a theoretical
limit where the BER performance is less than 1⨯10-5, meaning that if any received packet has a
BER higher than 1⨯10-5, the effective throughput for that particular SNR region is zero. From
Figure 9, it can be seen that 2/3 SOQPSK is the most robust scheme at low SNRs; however, as the
SNR increases, its spectral efficiency decreases. This is because at high SNR, the channel permits
an MCS with higher throughputs. Similarly, if OFDM 64 QAM is used, it can only tolerate
channels with SNR greater than 23 dB. In the case of LDAR, it adaptively uses a reliable mode
with the highest throughput that accommodates current channel condition at any given SNR.
Figure 9. Link burst throughput for each transmission mode at various SNR.
CONCLUSION AND FUTURE WORK
We have successfully implemented and demonstrated in hardware an adaptive system that
combines both OFDM and SOQPSK modulations. We have shown in a laboratory setting that
combining the high throughput of OFDM constellations with the noise robustness of SOQPSK can
maintain a minimum level of bit error performance in varying channel conditions. We have
theoretically and empirically created a decision mechanism to determine the optimal
SNR/EVM/dispersion levels for switching modulations and code rates. Doing so achieves the best
possible throughput for a given level of bit error performance. The results also show that LDAR
algorithm adaptively selects a reliable MCS that best tolerates current channel conditions.
Currently, the LDPC encoding and decoding processing are done at a controller instead of an
FPGA. Because of this, the hardware system is not able to compute at a desired throughput. For
the next phase of the development, we are porting the implementation to a larger FPGA platform
to achieve the throughput constraint in a deployable form factor.
ACKNOWLEDGEMENT
This project is funded by the Test Resource Management Center (TRMC) Test and
Evaluation/Science & Technology (T&E/S&T) Program through the U.S. Army Program
Executive Office for Simulation, Training and Instrumentation (PEO STRI) under Contract No.
W900KK-13-C-024. The public release number is 412 TW-PA-16246.
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