Sub-threshold VLSI Logic Family Exploiting
Unbalanced Pull-up/down Network, Logical
Effort and Inverse-Narrow-Width Techniques
MINGZHONG LI
State Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE,
University of Macau
20 January 2016
ID: 1S-8
Background and Motivation
Inverter
NAND
NOR
2
low-power
dissipation
& durable
battery life
operations to acquire minimum
energy consumption
Ene
rgy/
Cyc
le (
J)
VDD (V)
1E-16
1E-15
1E-14
1E-13
1E-170.2 0.4 0.6 0.8 1
Sub-
threshold
ETotal
Eswitch
Eleakage
- Minimum energy solution
𝑬𝒔𝒘𝒊𝒕𝒄𝒉 = 𝑪𝒆𝒇𝒇𝑽𝑫𝑫𝟐 ∝ 𝑽𝑫𝑫
𝟐
𝑬𝒍𝒆𝒂𝒌𝒂𝒈𝒆 = 𝑾𝒆𝒇𝒇𝑰𝒍𝒆𝒂𝒌𝒂𝒈𝒆𝑽𝑫𝑫𝒕𝒅𝑳𝑫𝑷 ∝ 𝑽𝑫𝑫
𝑬𝑻𝒐𝒕𝒂𝒍 = 𝑬𝒔𝒘𝒊𝒕𝒄𝒉 + 𝑬𝒍𝒆𝒂𝒌𝒂𝒈𝒆 ∝ 𝑽𝑫𝑫𝟐
Problems: sub-optimal energy efficiency; large silicon area
Solutions: sub-threshold logic; low computational cost algorithm
(circuit level) (system level)
ID: 1S-8
Inverse-Narrow-Width Effect
3
𝜇𝑒𝑓𝑓 ∝1
𝑉𝑇𝑡𝑑 =
𝜅𝑉𝐷𝐷𝐶𝐿𝐼𝑠𝑢𝑏
𝐼𝑠𝑢𝑏 = 𝐼0 ∙ 𝜇𝑒𝑓𝑓 ∙𝑊
𝐿∙ 𝑒
𝑉𝐺𝑆−𝑉𝑇+𝜂𝑉𝐷𝑆𝑛𝑉𝑡ℎ ∙ (1 − 𝑒
−𝑉𝐷𝑆𝑉𝑡ℎ )
Transistor Width (mm)
0.42
0.44
0.46
0.48
0.5
0.1 0.5 0.9 1.7 2.5
Minimum
NMOS VT
@ 220 nm
NM
OS
VT (
V)
2.11.3Transistor Width (mm)
-0.46
-0.47
-0.48
-0.49
-0.50.1 0.5 0.9 1.7 2.5
Minimum
PMOS |VT|
interval @
400 – 590 nm
PM
OS
VT (
V)
2.11.3
(a) (b)
(a) NMOS, (b) PMOS VT vs. transistor width @ 0.3 V
ID: 1S-8
Unbalanced Network
4
Balanced networks- P/N ratio (typical): 5/1.
- Energy sub-optimized
- Full operating freq. range
Unbalanced networks- P/N ratio (typical): < 5/1.
- Energy-optimized
- Low-to-moderate operating freq.
ID: 1S-8
Single Stage Gates Design
5
Minimum energy solution
- Wp = 420 nm; Wn = 220 nm.
- NAND and NOR scaling.
Resistor Model Derivatives
Rx/n
Rx/n nWx
nWx
Stack Devices Sizing
RxRx Wx Wx
Parallel Devices SizingRP
Rn
Wp
Wn
Wp/L
Wn/L
Wp/L
3Wn/L
3Wp/LWp/L Wp/L
3Wn/L
3Wn/L
3Wp/L
3Wp/L
Wn/L Wn/L Wn/L
ID: 1S-8
Single Stage Gates Design
6
ID: 1S-8
Multi-stage Gates Design
7
- g: 11. - g: 4.
A B
A
B
Logical effort (major criteria)
𝑔 = 𝑊𝑖𝑊𝑖𝑛𝑣
=𝑊𝑏𝑊𝑖𝑛𝑣
L Fixed
A B
A
B
𝑔 = 𝐶𝑖𝐶𝑖𝑛𝑣
=𝐶𝑏𝐶𝑖𝑛𝑣
faster & more robust
Propagation Delay (µ)
Num
ber
of O
ccur
renc
es 20
0 0.5 2.0
15
10
5
0
25
1.51.0 2.5 3.0 3.5
Mean: 1.47857µ Std. Dev.: 475.962n
N: 100
ID: 1S-8
Measurement Results
8
0.45V liberty
file (.lib)
based FIR
0.2 mm
0.265 mm0.3V liberty
file (.lib)
based FIR
0.35 mm
0.33 mm
0.6V liberty
file (.lib)
based FIR0.25
mm
0.196 mm
Power Supply Voltage (V)
Nor
mal
ized
Ene
rgy/
Cyc
le
0
0.4
0.8
1.2
0.25 0.35 0.45 0.55
Circuit with 0.30V .libCircuit with 0.60V .libCircuit with 0.45V .lib
0.32V
0.34V
0.44V
(b) Energy w/ random signal
Power Supply Voltage (V)
Nor
mal
ized
Ene
rgy/
Cyc
le
0
0.4
0.8
1.2
0.25 0.35 0.45 0.55
0.28V
0.31V
0.39V
Circuit with 0.30V .libCircuit with 0.60V .libCircuit with 0.45V .lib
(a) Energy w/ ECG signal
FPGA
Control
Logic
CLK
reset
Test Vectors
Core with
0.3-V .lib
Core with
0.6-V .lib
Core with
0.45-V .libOscilloscope
Agilent 3458A
Multimeter
Power Supply
Normalized energy/cycle with inputs (a) ECG signal; (b) random signal
(Black dots indicate the optimum points)
ID: 1S-8
Benchmark
9
This Work[1]
TCASII’12
[2]
VLSI’07
[3]
JSSC’10
[4]
JSSC’10with
0.45V .lib
with
0.6V .lib
FIR Type 14-tap, 8-bit 30-tap, 8-bit 8-tap, 8-bit 14-tap, 8-bit 8-tap, 8-bit
Technology 0.18-μm 0.13-μm 0.13-μm 0.13-μm 90-nm
Optimum
VDD (V)0.31 0.39 0.35 0.2 0.27 0.29
Freq. (Hz) 100k 100k 29k 12k 20M 148k
Energy/Tap
(pJ)0.02735 0.03568 1.1 1.19 1.11 0.6275
Power (nW) 38.29 49.95 32 114 310,000 742.96
FoM* 0.4273 0.5575 0.57 18.55 17.37 9.80
Area/Channel
(mm2)0.053 0.049 0.058 1.54 0.38 N/A
*FIR FoM = power(nW)/freq.(MHz)/# of taps/input bit length/coefficient bit length
[1] A. Klinefelter, et. al., "A programmable 34 nW/channel sub-threshold signal band power extractor on a body sensor node SoC," IEEE
Trans. on Circuits and Systems II, vol. 59, no. 12, pp. 937-941, Dec. 2012.
[2] H. Myeong-Eun, et. al., "An 85 mV 40 nW process-tolerant subthreshold 8 x 8 FIR filter in 130 nm Technology," in Proc. IEEE Symp. VLSICircuits - VLSI ‘07, pp. 154-155, Jun. 2007.
[3] W.-H. Ma, et. al., "187 MHz subthreshold-supply charge-recovery FIR," IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 793–803, Apr. 2010.[4] I. J. Chang, et. al., "Exploring asynchronous design techniques for process-tolerant and energy-efficient subthreshold operation," IEEE J.
Solid-State Circuits, vol. 45, no. 2, pp. 401-410, 2010.
ID: 1S-8
Conclusion
10
1. Unbalanced pull-up/down networks and logical effort are applied to
realized a sub-threshold VLSI logic family for biomedical applications.
2. Three 14-tap 8-bit FIR filters were designed and measured according to
different liberty timing files.
3. The achieved FoMs at the minimum energy operating points for the 0.45
and 0.6-V library designs were 0.4273 (at 0.31 V) and 0.5575 (at 0.39 V)
which compared favorably with the state-of-the-art F.I.R. filter designs.
ID: 1S-8