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MAKING A “MODEL”
BOB PEDDENPOHL MODELING MANAGERCYPRESS MODELING CENTERLEXINGTON, KY
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OUTLINE
WHAT DOES CY KENTUCKY DO?WHAT IS A BSIM SPICE MODEL?HOW TO MAKE A MOS SPICE MODEL?
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DESIGN KIT MAKES MONEY
PRODUCT ($)DESIGN KIT (CAD, R&D)
MARKET NEEDS
PRODUCT SPECS
CIRCUIT SCHEMATIC
LAYOUT
CIRCUIT DESIGN
SPICERCX
MODELS
MEAS.VTHIDS
METAL THICKILD THICK
SILICON QUAL
SCHEMATICSLAYOUTS
DRCLVS
E-TEST MODULESTEST CHIP TAPEOUT
PRODUCT PLANS
PRE-SILICON WORK
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DESIGN KIT MAKES MONEY
PRODUCT ($)DESIGN KIT (CAD, R&D)
MARKET NEEDS
PRODUCT SPECS
CIRCUIT SCHEMATIC
LAYOUT
CIRCUIT DESIGN
SPICERCX
MODELS
MEAS.VTHIDS
METAL THICKILD THICK
SILICON QUAL
SCHEMATICSLAYOUTS
DRCLVS
E-TEST MODULESTEST CHIP TAPEOUT
PRODUCT PLANS
PRE-SILICON WORK
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5 Cypress Confidential
OUTLINE
WHAT DOES CY KENTUCKY DO?WHAT IS A BSIM SPICE MODEL?HOW TO MAKE A MOS SPICE MODEL?
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INTRODUCTION: MODELS
GENERIC DEFINITIONMAN MADE EXPRESSIONS TO REPRESENT MOTHER NATURE
VLSI DESIGN DEFINITIONMODELS = DESIGNERS PERCEPTION OF TECHNOLOGY
ENGINEERING DEFINITIONMODELS = PHYSICAL EQUATIONS + PARAMETERS
Ids = BETA (Vgs-VT)^2 where VT = 0.6 BETA = w/l*COX*MOBILITY = 1E-6
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INTRODUCTION:TYPES OF MODELS
SIMULATION MODELS
TABLE LOOKUP
SIMULATORS ACCESS MEASURED DC/AC DATA IN A TABULAR FORM
ANALYTICAL (OR COMPACT)
ANALYTICAL OR COMPACT DEVICE MODELS BASED PRIMARILY ON DEVICE PHYSICS. FITTING PARAMETERS INTRODUCED TO IMPROVE ACCURACY
NUMERICAL
NUMERICAL SOLUTION OF DEVICE CHARACTERISTIC
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SCHEMATICS USE BSIM COMPACT MODELS
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INTRODUCTION: MODELS LIMITATIONS
IDEAL VS REALITYIDEAL DESIGN SIMULATIONS EXACTLY EQUAL SILICON MEASUREMENTS
REALITYMODEL NOT PERFECTMODEL HAS ACCURACY LIMITATIONSGOOD DESIGNER UNDERSTANDS MODEL LIMITATIONSNEED TO MODEL PROCESS VARIATIONSNEED MODELS QUICKLY TO ENABLE DESIGNERS
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OUTLINE
WHAT DOES CY KENTUCKY DO?WHAT IS A BSIM SPICE MODEL?HOW TO MAKE A MOS SPICE MODEL?
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WHAT MODELS USED AT UK?WHAT CY TECHNOLOGY DID YOU USE?
RAM7: Wmin/Lmin = 0.42/0.20um, Vcc=1.8V, Idrive = 9.99 mA
WHEN WAS TECHNOLOGY QUALIFIED?MODEL FROZEN Q302
WHAT TYPE OF MOSFETS?LV MOS (NSHORT/PSHORT), LVT PMOS (PLOWVT)CELL FETS (NPASS, NPD, PPU)
WHAT’S NSHORT ELECTRICAL TOX? JUNCTION DEPTH?TOX= 41 A, XJ = 0.1um
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MODEL DEVELOPMENT PROCESS
MEASUREMENT (DC, AC, TRAN)
EXTRACT WAFER CASE MODEL
RO MEAS = RO SIMS
CENTER TO EDR NOMINAL (TT)
SELECT “GOLDEN” WAFER
SKEW MODELS (FF, SS, FS, SF)
QA & RELEASE TO DESIGN
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SELECT “GOLDEN” WAFER
IDEAL: MODELING SILICON CLOSE TO NOMINALREALITY: ~400+ PARAMETERS, ONLY MOST IMPORTANT ON TARGET
NOMINALMIN MAX
WAFER
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MODEL DEVELOPMENT PROCESS
MEASUREMENT (DC, AC, TRAN)
EXTRACT WAFER CASE MODEL
RO MEAS = RO SIMS
CENTER TO EDR NOMINAL (TT)
SELECT “GOLDEN” WAFER
SKEW MODELS (FF, SS, FS, SF)
QA & RELEASE TO DESIGN
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MEASUREMENTS: HARDWARE & SOFTWARE
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MEASUREMENTS: COMPLETE MOS
FET DC (VTH0, RDSW)FET AC (CGDO,DLC)DIODE DC (JS,JSW)DIODE AC (CJ, CJSW)
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MEASUREMENTS: FET DC
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MEASUREMENTS: FET DC
MODEL NEEDS SCALE WITHIN ALL GEOMETRY, TEMP
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Threshold Voltage vs Length
0.3
0.4
0.5
0.6
0.1 1 10 100
Length (L) in microns
VTH Vth
MEASUREMENTS: DC FET QA, VTH VS. L
MODEL ACCURACY <=> MEASUREMENT ACCURACYCONDENSED DATA TRENDS
Strong Halo , L dependenceStrong Halo , L dependence
Halo with SCEHalo with SCE
Normal SCENormal SCE
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MEASUREMENTS: DC FET QA, VTH VS. W
MODEL ACCURACY <=> MEASUREMENT ACCURACYCONDENSED DATA TRENDS
Threshold Voltage vs Width
0.3
0.4
0.5
0.6
0.1 1 10 100
Width (W) in microns
VTH Vth
LOCOS (+k3)
STI (-k3)
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MEASUREMENTS: FET AC
-2.0 -1.2 -0.4 0.4 1.2 2.0Vgate (V)
11.0
14.14
17.28
20.42
23.56
26.7
Cg
g (
pF
)
NCGG_GC.CV W/L=16800.00/0.15 T=25C
OXTC Α∝ε
( ))(vXTC
DEPOX+Α
∝ε
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0.0 0.4 0.8 1.2 1.6 2.0Vbias (V)
4.0
5.02
6.04
7.06
8.08
9.1
Max.Err%= Rms Err%=0.22
MEASUREMENTS: DIODE DC/AC
-5.0 -3.8 -2.6 -1.4 -0.2 1.0V (V)
1.0e-11
1.0e-10
1.0e-9
1.0e-8
1.0e-7
1.0e-6
1.0e-5
1.0e-4
1.0e-3
1.0e-2
Max.Err%= Rms Err%=25.4
REVERSE BIAS DC CHARACTERISTIC
I_FORWARD ~mA
I_Reverse ~ pA
REVERSE BIAS AC CHAR.= f(CJA, CJP, EX,)
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MEASUREMENTS: TRANSIENT
RING OSCILLATOR VALIDATION OF MODEL
ININO/PO/P
( )CTINTERCONNEFETCTINTERCONNE
d
CCRWHERE
NDELAYRO
⊕×∝
××=
τ
τ2_
C9R10
TECH DESCRIPTION DELAY (PS/STAGE) SPECC9 143 stages WP/WN=4/2 FanOut=1 55.7 55.0
R10 143 stages WP/WN=4/2 FanOut=1 31.0 31.0
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MODEL DEVELOPMENT PROCESS
MEASUREMENT (DC, AC, TRAN)
EXTRACT WAFER CASE MODEL
RO MEAS = RO SIMS
CENTER TO EDR NOMINAL (TT)
SELECT “GOLDEN” WAFER
SKEW MODELS (FF, SS, FS, SF)
QA & RELEASE TO DESIGN
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WAFER CASE: DC MOS EXTRACTION
MODEL = EQUATIONS + PARAMETERS
EQUATIONS (BSIM3V3) + MODEL PARAMETERS = WAFER CASE MODEL
Threshold Model
Mobility ModelDrive Current
Channel Length
Modulation
Short Channel Effects
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WAFER CASE: MOS MODEL BINNING
Long/Wide Long/Wide Constant Constant VtVt
Narrow Width Effects Narrow Width Effects (STI/LOCOS)(STI/LOCOS)
Sho
rt C
hann
el E
ffect
s (H
ALO
/DIB
L)
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WAFER CASE: AC FET + DIODE
MODEL EXTRACTION
MODEL = EQUATIONS + PARAMETERS
EQUATIONS (BSIM3V3) + PARAMETERS (EXTRACTED FROM MEASUREMENTS) = MODEL (WAFER CASE)
Accumulation
Inversion
Intrinsic Cap for Analog Design
BSIM3 Limitation
0.0 0.4 0.8 1.2 1.6 2.0Vbias (V)
4.0
5.02
6.04
7.06
8.08
9.1
Max.Err%= Rms Err%=0.22
-5.0 -3.8 -2.6 -1.4 -0.2 1.0V (V)
1.0e-11
1.0e-10
1.0e-9
1.0e-8
1.0e-7
1.0e-6
1.0e-5
1.0e-4
1.0e-3
1.0e-2
Max.Err%= Rms Err%=25.4 4.58
MOS DIODE IV MODEL
MOS DIODE CV MODEL
MOSFET CV MODEL
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MODEL DEVELOPMENT PROCESS
MEASUREMENT (DC, AC, TRAN)
EXTRACT WAFER CASE MODEL
RO MEAS = RO SIMS
CENTER TO EDR NOMINAL (TT)
SELECT “GOLDEN” WAFER
SKEW MODELS (FF, SS, FS, SF)
QA & RELEASE TO DESIGN
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RO CAL: LAYOUT EXTRACTED SIMULATION
VALIDATE CAD EXTRACTION RULES + MOS BSIM MODELS
ININO/PO/P
( )CTINTERCONNEFETCTINTERCONNE
d
CCRWHERE
NDELAYRO
⊕×∝
××=
τ
τ2_
R10
LAYOUT (DESIGN DEP.) LAYOUT MODEL: (ILD, METAL THICK)
C9
CALIBRE RCX
CIRCUIT: FET DELAY + Rinterconnect + Cinterconnect
SPICE MODELS
RO SIMS = RO MEAS
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MODEL DEVELOPMENT PROCESS
MEASUREMENT (DC, AC, TRAN)
EXTRACT WAFER CASE MODEL
RO MEAS = RO SIMS
CENTER TO EDR NOMINAL (TT)
SELECT “GOLDEN” WAFER
SKEW MODELS (FF, SS, FS, SF)
QA & RELEASE TO DESIGN
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CORNER MODELS
WAFER CASE SIMULATIONS = WAFER MEASUREMENTSWHAT ABOUT PROCESS VARIATIONS?WILL MY DESIGN YIELD?
NOMINALMIN MAX
WAFER
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CORNER MODELS
REALITYEVERY SITE/WAFER/LOT/SPLIT IS DIFFERENT ( PROCESS VARIATIONS)
WORKING WITH REALITYCORNERS: MODELING SPACE TO COVER ALLPOSSIBILITIES (STATISTICALLY) IN PROCESS
TEAM EFFORT TO GET GOOD YIELDFAB: +/-4 SIGMA E-TEST à 99.99% WAFERS INSIDE MIN/MAX MODELING: MIN/MAX MODELS MATCH FAB LIMITSDESIGN: SIMULATE DESIGN WORKING AT MIN/MAX LIMITSALL 3 GROUPS WORKING = GOOD PRODUCT YIELD
NOMINALMIN MAXtt.cor
ss.cor
wafer.cor
ff.cor
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WHY 5 MOS CORNERS?
VTs AT SS & FF = 70% SPEC RANGEVTs AT FS/SF = 100% SPEC RANGE
0.660.670.680.690.7
0.710.720.730.740.750.760.770.780.790.8
0.810.820.830.840.850.860.870.88
vtxn
s15
-1.05 -1.03 -1.01 -0.99 -0.97 -0.95 -0.93 -0.91 -0.89 -0.87 -0.85 -0.83vtxps15
fs
sf
7
8
9
10
11
12
idsn
s15
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7idsps15
ff
ss
VTXNS15 vs. VTXPS15 (V) (Vth @ W/L=25/0.15um)
IDSNS15 vs. IDSPS15 (mA)Idrive (Vgs=Vds=Vcc)W/L=25/0.15um
ss
ff
fs
sf
tt
tt
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WHY CORNER METHODOLOGY IMPORTANT
MODEL MUST MATCH DESIGN/FAB AGREED LIMITS
FAB WANTS WIDE MIN/MAX LIMITSSTATISTICAL PROCESS CONTROL (SPC)HOW GOOD DOES A PROCESS RUN WITHIN IT’S NOM/MIN/MAX
DESIGN WANTS NARROW MIN/MAX LIMITSEASIER TO DESIGNSMALL PROCESS VARIATION à SMALLER SI AREA
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MODEL DEVELOPMENT PROCESS
MEASUREMENT (DC, AC, TRAN)
EXTRACT WAFER CASE MODEL
RO MEAS = RO SIMS
CENTER TO EDR NOMINAL (TT)
SELECT “GOLDEN” WAFER
SKEW MODELS (FF, SS, FS, SF)
QA & RELEASE TO DESIGN
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QA: MODEL DOCUMENTATION
MODEL SUMMARY TABLE
MODEL ACCURACY IN SUB-THRESHOLD, GM ACCURACY
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37 Cypress Confidential
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APPENDIX
BOB PEDDENPOHL (PED)CYPRESS MODELING CENTER
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Applying the Corner Models
Design
Interconnect R
tres, fres, sres
Interconnect C
tpar, fpar, spar
r+c.mod
Interconnects/Passives
trtc, hrlc, lrhc
FET Corners
tt, ff, ss, sf, fs
CellFET Corners
ttcell, ffcell, sscell
Temp coef of R
C for various line/space
Npass
Nlatch
Platch
Nmos/Pmos
Nthick/Pthick (HV)
Diode
PNP
metal/contact/poly/diff
Sheet resistances