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EE 201 : Digital Circuits and
Micro rocessors
Dr. Amit Sethi
Room 303, EEE Dept.
2529, amitsethi
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Logic Families
Module objectives:
Get an understanding of how logic gates work
Develop appreciation for low level issues in gates
Understand characteristics of different families
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An example of a TTL gateAn example of a TTL gate
A B ICQ1 Q1 Q2 Q3 Q4 Y, O/P
0 0 + ON OFF OFF ON 1
+Vcc
Q2
Q4
4K 1.6K 130R1 R2R3
A standard TTL NAND gate circuit
Table explaining the operation of the TTL NAND
gate circuit
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1 0 + ON OFF OFF ON 1
1 1 0 OFF ON ON OFF 0
AB Y O/P
Q1 Q
3
R4
1K
I CQ1D
1 D2
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Transistor Size ScalingTransistor Size ScalingPerformance improves as size is decreased: shorter switching time, lower power consumption.
2 orders of magnitude reduction in transistor size in 30 years.
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Moores LawMoores Law
In 1965, Gordon Moore predicted that the number of
transistors that can be integrated on a die woulddouble every 18 to 14 months
i.e., grow exponentially with time
Considered a visionary million transistor/chipbarrier was crossed in the 1980s
2300 transistors, 1 MHz clock (Intel 4004/4040) - 1971
42 Million transistors, 2 GHz clock (Intel P4) - 2001140 Million transistors, (HP PA-8500)
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Moores Law and IntelMoores Law and Intel
From Intels 4040 (2300 transistors) to Pentium II (7,500,000 transistors) and beyond
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Logic Families Logic Family : A collection of different ICs that have similar
circuit characteristics The circuit design of the basic gate of each logic family is
the same
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comparing logic families include :
Logic Levels
Power Dissipation
Propagation delay Noise margin
Fan-out ( loading )
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TTL and CMOSTTL and CMOS Connecting BJTs together gives rise to a family of
logic gates known as TTL
Connecting NMOS and PMOS transistors together
gives rise to the CMOS family of logic gates
BJTMOSFET
(NMOS, PMOS)
TTL CMOS
transistor types
logic gate families
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Comparison of Logic FamiliesComparison of Logic Families
the most important to understand
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Electrical Parameters AndElectrical Parameters And
Interpretation Of Data SheetsInterpretation Of Data Sheets Voltages and Currents
Noise Margin Power Dissipation
Pro a ation Dela
Speed-Power Product
Fan-In, Fan-Out
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For a High-state gate driving a second gate, we define:
VOH
(min), high-level output voltage, the minimum voltage level that a
logic gate willproduce as a logic 1 output.
VIH (min), high-level input voltage, the minimum voltage level that alogic gate will recognize as a logic 1 input. Voltage below this level
Voltage & CurrentVoltage & Current
.
IOH, high-level output current, current that flows from an output in thelogic 1 state under specified load conditions.
IIH, high-level input current, current that flows into an input when alogic 1 voltage is applied to that input.
Ground
VIH
VOH
IOH I IHTest setup formeasuring values
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For a Low-state gate driving a second gate, we define:
VOL (max), low-level output voltage, the maximum voltage level thata logic gate will produce as a logic 0 output.
VIL (max), low-level input voltage, the maximum voltage level that alogic gate will recognize as a logic 0 input. Voltage above this value
Voltage & CurrentVoltage & Current
will not be accepted as low. IOL , low-level output current, current that flows from an output in
the logic 0 state under specified load conditions.
IIL , low-level input current, current that flows into an input when a
logic 0 voltage is applied to that input.Inputs areconnected to Vccinstead of Ground
Ground
VIL
V OL
I OL I IL
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Noise MarginNoise Margin
Manufacturers specify voltage limits to represent
the logical 0 or 1. These limits are not the same at the input and
output sides. ,
4.8V when it is supposed to output a HIGH but, at its inputside, it can take a voltage of 3V as HIGH.
In this way, if any noise should corrupt the signal,there is some margin for error.
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Noise MarginsNoise Margins
Important characteristics are:
VOH(min) min value of outputrecognized as a 1
Vcc
IH v u u
recognized as a 1
VIL(max) max value of inputrecognized as a 0
VOL(max) max value of outputrecognized as a 0
Values outside the given rangeare not allowed.
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Typical acceptable voltage ranges for positive logic 1 andlogic 0 are shown below
A logic gate with an input at a voltage level within theindeterminate range will produce an unpredictable output
level.
Logic Level & Voltage RangeLogic Level & Voltage Range
Logic 1
Logic 0
5.0V
0V
2.5V
Indeterminate
0.8V
TTL
Logic 1
Logic 0
5.0V
Indeterminate
0V
1.5V
CMOS
3.5V
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Given the following parameters, calculate the noisemargin of 74LS series.
Parameter 74LS
VIH(min) 2V
Worked ExampleWorked Example
VIL(max)
0.8V
VOH(min) 2.7V
VOL(max) 0.4V
Solution:
High Level Noise Margin, VNH = VOH (min) - VIH (min)=2.7V-2.0V=0.7V
Low Level Noise Margin, VNL = VIL (max) - VOL (max)=0.8V-0.4V=0.4V
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Speed Characteristics (1/2)Speed Characteristics (1/2)
Propagation delay (tpd
) is the time taken for a change at the
input to appear at the output (measured at 50%)
Output
propagation delay
50%
50%
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Speed Characteristics (2/2)Speed Characteristics (2/2)
Rise Time: Time from 10% to 90% of signal, Low to High
Fall Time: Time from 90% to 10% of signal, High to Low
r se me
10% 90% 90% 10%
a me
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Other CharacteristicsOther Characteristics
Power dissipation
Power consumed while switching state (dynamic)Power consumed while retaining state (static)
T e an-out, w c s t e max mum num er oinputs that can be driven successfully to either
logic level before the output becomes invalid
Depends primarily on current drawn at output and
inputs for acceptable voltage levels
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Power DissipationPower Dissipation
Static
I2R losses due to passive components, no input signal
Dynamic
I2R losses due to charging and discharging capacitancesthrough resistances, due to input signal
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Speed (propagation delay) and power consumption
are the two most important performanceparameters of a digital IC.
A simple means for measuring and comparing the
SpeedSpeed--Power ProductPower Product
overall performance of an IC family is the speed-power product (the smaller, the better).
For example, an IC has
an average propagation delay of 10 nsan average power dissipation of 5 mW
the speed-power product = (10 ns) x (5 mW)
= 50 picoJoules (pJ) 21
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FanFan--InIn
Number of input signals to a gate
Not an electrical propertyFunction of the manufacturing process
NAND gate with a
Fan-in of 8
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FanFan--OutOut A measure of the ability of the output of one gate to
drive the input(s) of subsequent gates Usually specified as standard loads within a single
family
e.g., an input to an inverter in the same family May have to compute based on current drive
requirements when mixing families
Although mixing families is not usually recommended
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Current-source : the driving gate produces a
outgoing current VOHLow
Current Sourcing and SinkingCurrent Sourcing and Sinking
Current-sinking : the driving gate receives anincoming current
IH
VOL
IIL
High
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FanFan--OutOut An illustration of fan-out and the associated source
and sink currents
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A logic gate can supply a maximum output current
IOH(max), in the high state or
IOL(max), in the low state
A logic gate requires a maximum input current
IIH(max), in the high state or
Gate Drive Capability: FanGate Drive Capability: Fan--OutOut
IIL
(max), in the low state
Ratio of output and input current decide how many logic gates can bedriven by a logic gate
fan-out(high) = IOH(max) / IIH (max)
fan-out(low) = IOL
(max) / IIL(max)
overall fan-out = fan-out(high) or fan-out(low) whichever is lower
A typical figure of fan-out is ten (10)
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How many 74LS00 NAND gate inputs can be driven by a
74LS00 NAND gate outputs ?
Solution:
Worked ExampleWorked Example
Refer to data sheet of 74LS00, the maximum values ofIOH = 0.4mA, IOL = 8mA, IIH = 20A, and IIL = 0.4mA
Hence,
fan-out(high) = IOH(max) / IIH (max)=0.4mA/20A=20
fan-out(low) = IOL(max) / IIL(max)=8mA/0.4mA=20,overall fan-out = min (fan-out(high) , fan-out(low))
Hence, overall fan-out = 20
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TTLTTL -- Example SN74LS00Example SN74LS00 Recommended operating conditions
Vcc supply voltage 5V 0.5 V
input voltages VIH = 2VVIL = 0.8V
Electrical Characteristics output voltage VOH = 2.7V
5 Volt
Input
Range
for 1
Output
Range
for 1
wors case OL = .
max input curr. IIH = 20AIIL = -0.4mA
Prop. delay tp = 15 nS
noise margins for a logic 0 = 0.3V
for a logic 1 = 0.7V Fan-out 20 TTL loads
0 Volt
0.80.5
2.0
2.7
InputRange
for 0
OutputRange
for 0
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TTL Circuit OperationTTL Circuit Operation
A B ICQ1 Q1 Q2 Q3 Q4 Y, O/P
0 0 + ON OFF OFF ON 1
+Vcc
Q2
Q4
4K 1.6K 130
R1 R2 R3
A standard TTL NAND gate circuit
Table explaining the operation of the TTL NAND
gate circuit
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1 0 + ON OFF OFF ON 1
1 1 0 OFF ON ON OFF 0
A
B Y O/P
Q1 Q
3
R4
1K
I CQ1D
1 D2
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TransistorTransistor--Transistor Logic FamiliesTransistor Logic Families
Transistor-Transistor Logic Families:74L Low power
74H High speed
74S Schottky74LS Low power Schottky
74AS Advanced Schottky
74ALS Advance Low power Schottky
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7400 Series Evolution7400 Series Evolution BJT storage time reduction by using a BC Schottky diode.
Schottky diode has a Vfw=0.25V. When BC junction becomes forward biased
Schottky diode will bypass base current.
C
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MOS Circuit OperationMOS Circuit Operation
Table explaining the operation of
the CMOS inverter circuit
A CMOS inverter circuit
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O/PI/P
Q1
Q2
I/P Q 1 Q2 O/P0 ON OFF 1
1 OFF ON 0
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CMOS Logic FamiliesCMOS Logic Families
CMOS Logic Families40xx/45xx Metal-gate CMOS
74C TTL-compatible CMOS
74HC High speed CMOS
74ACT Advanced CMOS -TTL compatible
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CMOS Family EvolutionCMOS Family Evolution CMOS Logic Trend: Reduction of dynamic losses (cross-
conduction, capacitive charge/discharge cycles) by
decreasing supply voltages:
12V5V 3.3V 2.5V 1.8V 1.5V
Reduction of IC power dissipation is the key to:
higher integration improved reliability
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Groups within a familyGroups within a family Within each of these families there is a large variety of different
devices
We can break these into groups based on the number gates
per device
Acronym Description No Gates Example
SSI Small-scale integration 1M 80486/80586
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SSI DevicesSSI Devices
Each package contains a code identifying the package
N74LS00
Manufacturers Code
N = National SemiconductorsSN = Signetics
Specification
Family
L
LS
H
Member
00 = Quad 2 input NAND02 = Quad 2 input Nor
04 = Hex Invertors
20 = Dual 4 Input NAND
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Typical acceptable voltage ranges for positive logic 1 andlogic 0 are shown below
Comparison of Logic FamiliesComparison of Logic Families
Logic 1
5.0V
2.7V
Logic 1
5.0V
Indeterminate
3.5V
A logic gate with an input at a voltage level within theindeterminate range will produce an unpredictable output
level
Logic 00V
Indeterminate
0.8V
TTL
Logic 0
0V
1.0V
CMOS
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Comparison of Logic FamiliesComparison of Logic Families
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Comparison of Logic FamiliesComparison of Logic Families
speed power product = constant
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Success Drives ProliferationSuccess Drives Proliferation
New families introduced based on Higher performance
Lower power
New features
New signaling threshold
19602003
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Interfacing between logic families Chips in the same family are usually compatible
Across families, generally speaking, we need to match V and Iof output of driving circuit to that of the driven circuit
Buffer gates or stages must be used if current requirementsare not satisfied. Frequency of operation also becomes important for high-
speed applications
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Can TTL drive CMOS?
No
Because:
VOH(min)>VIH(min),so there is no
guarantee that TTL
high output will be
high enough as a
high input for CMOS
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TTL CMOS interface example using a pull-
up resistor
Issues:Low value pull up resistor consumes more power
High value pull up resistor decreases speed (RC circuit)
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Choosing a Logic Family Sometimes the choice is easy. E.g. for low static power, use CMOS
Often needs are conflicting: speed, power, noise immunity, cost Earlier speed dictated choice: ECL > TTL > CMOS
Now, with advanced TTL and CMOS, the choice is no longer clear-cut. Allthree will work at 100 MHz or more
ECL generates the least noise because the transitions are small, yet for thatsame reason it is more susceptible to external noise
TTL could be a compromise between noise generation and susceptibility
Advanced CMOS is the noisiest because of its rapid rise and fall times, but
the designer might opt to cope with the noise problems to take advantageof the low standby power requirements
A good rule is to use devices which are no faster than the applicationrequires and which consume the least power consistent with the needed
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Self Study Read about it on Wikipedia:
Intel, AMD, DEC and Sun MicrosystemsCadence and Synopsys
Follow what research is going on in digital
systems in EE or CS departments of:MIT, Berkley, Stanford, UIUC
Other leading academic institutions