LOGOUltralow-Power Design inNear-Threshold Region
Prof. : M. Shams
Name: Yiqi Chang
Student #:6624968
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Outline
Introduction1
Device and Circuit model2
Sensitivity Analysis3
Energy-Delay Optimization4
Sense-Amplifier-Based PTL (SAPTL)5
Architectural Optimization6
Conclusion7
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Introduction
Past five years
minimum-energy point
(MEP)
Traditional
minimum-delayoperational point (MDP)
Optimization logic circuit
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Introduction
Use minimum-energy point
Voltage-based optimization
Various architectural techniques
Ultralow power Ultralow power designdesign
Method to get ultralow power
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Device and Circuit model
Current model:Current of starting point (VGS =VT) :
n: subthreshold slope, μ: mobility , Cox: oxide capacitance, and thermal voltage ϕt =kT/q
Current in the vicinity of VT:
IC: inversion coefficient, and kfit is model-fitting parameter
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Device and Circuit model
inversion coefficient: the degree of inversion of the transistor
sub-VT (IC<1)and above-VT (IC > 1)
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Device and Circuit model
Fig. 2 Inversion coefficient for HVT and LVT devices for a 65 nm technology.
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Sensitivity Analysis
Sensitivity: a parameter x represents a percent reduction in energy for a percent increase in delay
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Sensitivity Analysis
Good news for MEP region
Easier to do than to adjust gate sizing.
Not require any layout changes
Could be done after chip fabrication
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Energy-Delay Optimization
3 parameters for optimization:
Supply
Sizing
VT(selected from the available discrete values)
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Sense-Amplifier-Based PTL (SAPTL)
Dactive: sum of the sense amplifier and driver delays
Dstack : the stack delay
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Architectural Optimization
Some architectural can be used to get optimizationTime-multiplexing technique
www.themegallery.com
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Conclusion
1.MEP: expensive of performance.
2.MDP: expensive of energy.
3.Energy 20%↑ → 10-times in performance↑
4.PTL outperforms standard CMOS in the near-
threshold region(achieving lower energy).
5.The use of time-multiplexing: both lower area
and energy without performance penalty
(reduced leakage that comes with a lower area).