Download - Lecture 23 – Sleep Modes Borivoje Nikolić
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inst.eecs.berkeley.edu/~ee241b
Borivoje Nikolić
EE241B : Advanced Digital Circuits
Lecture 23 – Sleep Modes
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Announcements
• Assignment 4 due on Friday.
• Reading• Rabaey, LPDE, Chapter 8
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Outline
• Module 5• Sleep modes
• Optimal thresholds and supplies
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5.J Lowering Leakage During Design: Transistor Stacking
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Power /Energy Optimization Space
Constant Throughput/Latency Variable Throughput/Latency
Energy Design Time Sleep Mode Run Time
Active
Logic designScaled VDD
Trans. sizingMulti-VDD
Clock gatingDFS, DVS
Leakage
Stack effectsTrans sizingScaling VDD
+ Multi-VTh
Sleep T’sMulti-VDD
Variable VTh
+ Input control
+ Variable VTh
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Stack Effect
Reduction (in 0.13μ):
Narendra, ISLPED’01EECS241B L23 SLEEP 6
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Stack Forcing
Tradeoffs:• W/2 – 1/3 of drive current, same loading• 1.5W – 3x loading, same drive current
Narendra, ISLPED’01EECS241B L23 SLEEP 7
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5.L Power Gating
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Power /Energy Optimization Space
Constant Throughput/Latency Variable Throughput/Latency
Energy Design Time Sleep Mode Run Time
Active
Logic designScaled VDD
Trans. sizingMulti-VDD
Clock gatingDFS, DVS
Leakage
Stack effectsTrans sizingScaling VDD
+ Multi-VTh
Sleep T’sMulti-VDD
Variable VTh
+ Input control
+ Variable VTh
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Power Gating with Sleep Transistors
• Key components:• Power gates (& controller)
• Leakage vs size
• Switched cap
• Slew-rate/rush current
• State preservation
• Energy overhead ofsleep/wake-up transitions
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How to Size the Sleep Transistor?
• Don’t need both header and footer
• Circuits in active mode see the sleep transistor as extra power line resistance
• The wider the sleep transistor, the better
• Wide sleep transistors cost area and are slow to turn on/off• Minimize the size of the sleep transistor for given ripple (e.g. 5%)
• Need to find the worst case vector
• Sleep transistor is not for free – it will degrade the performance in active mode
• Charging and discharging the virtual rails costs energy
• Need to sequentially wake up
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Sleep Transistor
High-VTH transistor (many in parallel) has to be very large for low resistance in linear region. Low-VTH transistor needs much less areafor the same resistance.
Courtesy: R. Krishnamurthy, Intel
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Sleep Transistor Layout
Sleep transistor
cells
ALU
Area overhead
PMOS 6%
NMOS 3%
Tschanz, ISSCC’03
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Sleep in Standard Cells
Uvieghara, ISSCC’04
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Sleep Transistor Grid
Virtual VCC Virtual VSS
VCC
VSS
M4
M4
VCC
VSS
M4
M4
M3 M3 M3 M3
No sleep transistor PMOS & NMOSsleep transistors
Tschanz, ISSCC’03
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Power Gating
No power gating
“Ideal” power gating
Realistic profile
Keating, et al, Low Power Methodology Manual, 2009.
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Preserving State
• Virtual supply collapse in sleep mode will cause the loss of state in registers
• Putting the registers at nominal VDD would preserve the state• These registers leak
• The second supply needs to be routed as well
• Can lower VDD in sleep• Some impact on robustness, noise and SEU immunity
• State preservation and recovery
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Scan-Based Retention
• Scan-out/scan-in state to preserve/restore state
Keating, et al, Low Power Methodology Manual, 2009.
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SLEEP High VT
SLEEP High VT
CLK
SLEEP High VT
SLEEP High VT
[Mutoh95]
Retention Register Design
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Gating Sequences
• Sequence of steps:• Gate clock
• Isolate inputs
• Save (scan out)
• Reset
• Gate power
Keating, et al, Low Power Methodology Manual, 2009.
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Hierarchical Power Gating
Keating, et al, Low Power Methodology Manual, 2009.
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Project reports
• Due May 4, up to 6 pages
• Presentations on May 4 in the afternoon• 12min + 3 min Q&A
• 15min for 3-person teams
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5.M Dynamic Threshold Scaling
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Power /Energy Optimization Space
Constant Throughput/Latency Variable Throughput/Latency
Energy Design Time Sleep Mode Run Time
Active
Logic designScaled VDD
Trans. sizingMulti-VDD
Clock gatingDFS, DVS
Leakage
Stack effectsTrans sizingScaling VDD
+ Multi-VTh
Sleep T’sMulti-VDD
Variable VTh
+ Input control
DVS<Variable VTh
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Dynamic Body Bias• Similar concept to dynamic voltage scaling
• Control loop adjusts the substrate bias to meet the timing/leakage goal• Can be used just as runtime/sleep
• Limited range of threshold adjustments in bulk (<100mV)• Limited leakage reduction (<10x)
• Works well in FDSOI (80-85mV/V, with ~1.8V range)
• No delay penalty • Can increase speed by forward bias
• Energy cost of charging/discharging the substrate capacitance• but doesn’t need a regulator
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FDSOI and Bulk
• Bulk CMOS• Leakage paths through bulk
• RDF dominates local variability
• Diodes and B2B tunneling limit back-bias range
N-WellP-Well
P-Sub
G GD SS D VDDSGNDS
PMOSNMOS
N-WellP-Well
P-Sub
G GD SS D VDDSGNDS
PMOSNMOS
BOXBOX
UTBB FD-SOIThin body for short-channel control
No doping – less RDF
Extended back-bias range
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FDSOI Wells and Back Bias
• Flip-well (LVT)• VDDS, nom = GNDS,nom = 0V
• Forward body bias VBSN > 0V
• 0.3V < GNDS < (3V)• Limit due to diodes, BOX
• Can forward bias 2-3V each
P. Flatresse, ISSCC’13
N-Well P-Well
P-Sub
G GD SS D VDDS=0VGNDS=0V
PMOSNMOS
BOXBOXN-WellP-Well
P-Sub
G GD SS D VDDS=VDDGNDS=0V
PMOSNMOS
BOXBOX
0V 0V
Typical (RVT)GNDS,nom = 0V, VDDS, nom = VDD
Reverse body bias, VBSN < 0V
(-3V) < GNDS < VDD/2+0.3V
Limit due to diodes, BOX
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Back-Bias in FDSOI
• = 85mV/V body coefficient, and extended voltage range• Lower coefficient and voltage range in bulk, finFET
OutIn
VDD
P
N
VDDS
GNDS N-Well
P-Sub
GDSGNDS
BOX
VBS
D. Jacquet, JSSC 4/14
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Multi VTh
• No channel implant in 28FDSOI• No multi VTh
• Can’t abut wells • RVT and LVT require different well biases
D. Jacquet, JSSC 4/14
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Back Bias in FDSOI
• Triple well (deep N-Well, DNW) allows for separate back bias
• Layout penalty; capacitance to drive
N-WellP-Well
P-Sub
G G
D SS D
PMOSNMOS RVT
BOXBOX
P-Well
G
DSGNDS=0V
NMOS
BOX
DNW
VDDS=VDDGNDS 0V
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Digital Logic: UPF
• Supply, back-bias defined in Universal Power Format (UPF)
• Or Common Power Format (CPF)
• Handled by synthesis, place and route tools
UPF description of PT_TOP with GND, VDD, GNDS and VDDS supplies.create_power_domain PD_TOP
create_supply_port GNDcreate_supply_port VDD create_supply_net GND -domain PD_TOPconnect_supply_net GND -ports {GND}create_supply_net VDD -domain PD_TOPconnect_supply_net VDD -ports { VDD }
set_domain_supply_net PD_TOP -primary_power_net VDD -primary_ground_net GND
# Body-bias specificationcreate_supply_port VDDScreate_supply_port GNDScreate_supply_net VDDS -domain PD_TOPconnect_supply_net VDDS -ports { VDDS vddgndvdds*/VDDSCORE }create_supply_net GNDS -domain PD_TOPconnect_supply_net GNDS -ports { GNDS gnds*/VDDCORE1V8 }
create_supply_set back_bias_set \-function {nwell VDDS} \-function {pwell GNDS} \-reference_gnd {GND} \
create_power_domain PD_TOP -update -supply biasassociate_supply_set back_bias_set -handle PD_TOP.bias
M.Blagojevic, Ph.D. Dissertation, ISEP 2017
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Digital Logic - Implementation
• Well taps added explicitly• Difference from bulk
Back bias strapsLow DC current
Except for very fast transitions
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Dynamic Body Bias (Bulk)
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... ...
450mVFBB
450mVFBB
VCC
VSS
PMOSbody
NMOSbody
PMOSbias
NMOSbias
PMOSbias ... ...
NMOSbias
500mVRBB
500mVRBB
VCC
VSS
PMOSbody
NMOSbody
VHIGH
VLOW
Forward body bias (FBB)
Local VCC tracking
Active mode
Reverse body bias (RBB)
Triple well needed
Idle mode
Dual-VTcore
Tschanz, ISSCC’03
Dynamic Body Bias (Bulk)
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Body Bias Layout
Sleep transistor LBGs
Number of ALU core LBGs 30
Number of sleep transistor LBGs 10
PMOS device width 13mm
Area overhead 8%
ALU core LBGs
Sleep transistor LBGsALU core LBGs
ALU
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0%
5%
10%
15%
20%
10 100 1000 10000 100000 1000000Number of idle cycles
Tota
l pow
er s
avin
gs
Total Active Power Savings(Fixed activity: = 0.05)
Body bias (1.28V): active: FBB, idle: ZBB
Reference: 450mV FBB to core with clock gating, 1.28V, 4.05GHz, 75°C
0.5 5 50 500 5000 50000
Number of consecutive idle cycles (TOFF)
Number of consecutive active cycles (TON)
Power savings for TOFF > ~100 idle cycles
PMOS sleep transistor (1.32V)To
tal p
ower
sav
ings Max 18%
Max 8%
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Generating Back-Bias
• Tradeoff – speed of charging and discharging well caps
• Often measure VBB indirectly (leakage)
• Challenge: Generating –VSS
• 28nm FDSOI implementation
D. Jacquet, VLSI 2013
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Generating Back Bias
• Fast and wide voltage range back-bias in FDSOI
M. Blagojevic, VLSI 2016
Switched capacitors generate negative bias and pump substrate
chN
dchN
chP
dchP
nwell
pwell
VDD1V8
GND
GND
Neg. Boot‐Strap
Neg.Boot‐Strap
VDD1V8
GND
GND
φ1
φ1
φ2
φ2
Cfly
pwellCharger
pwellDischarger
nwellCharger
nwellDischarger
LEVEL
SHIFT
VDD1V0VDD1V8
LEVEL
SHIFT
VDD1V0VDD1V8
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Supply/Process Compensation
• Able to track ~200mV supply droops and maintain constant frequency (measured by a replica) by back-bias adjustments
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5.N Dynamic Threshold Scaling and Variations
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Body Biasing and Variations
• Body biasing with a local control loop can be used to lower the impact of process variations
• Used to limit die-to-die and within-die variations
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Self-Adjusting Threshold-Voltage Scheme (SATS)
• Older bulk technologies had stronger body effect
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Dynamic Frequency Loop in FDSOI
Quelen, ISSCC’18
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Substrate Biasing
Tschanz, JSSC 11/02EECS241B L23 SLEEP 44
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Effectiveness of Substrate Bias
• NBB: No body bias
• ABB: Adaptive body bias
Die-to-die variations
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Effectiveness of Substrate Bias
• ABB with multiple within die (WID) sensors
Within-die variations
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Techniques Summary (around 130nm node)
0
20
40
60
80
100
0 0.2 0.4 0.6 0.8 1
Il eak
(nor
mal
ized
)
VDD [V]
Sleep transistor - up to~25x leakage reduction
Standby supply reduction~3-4x leakage reduction
Reverse bias~3x leakage
reduction
Standby supply + reverse bias~10x leakage reduction
Reduced VDD
Off-transistorload line
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Power /Energy Optimization Space
Constant Throughput/Latency Variable Throughput/Latency
Energy Design Time Sleep Mode Run Time
Active
Logic designScaled VDD
Trans. sizingMulti-VDD
Clock gatingDFS, DVS
Leakage
Stack effectsTrans sizingScaling VDD
+ Multi-VTh
Sleep T’sMulti-VDD
Variable VTh
+ Input control
+ Variable VTh
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5.O Optimal VDD, VTh
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Dynamic Voltage Scaled Microprocessor
External VDD 3.3V±10% Internal VDDL 0.8V~2.9V ±5%
TX3900
User Logic PLL
VT
VS
Pow
er D
issi
patio
n (m
W)
Operating Frequency (MHz)
0
100
200
300
0 10 20 30 40
TheoryMeasurement
Courtesy: Prof. Kuroda
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Adapting VDD and VTH
• Adapting both VDD and VTh during runtime• VTh is much less sensitive Miyazaki, ISSCC’02
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Adapting VDD and VTH
Miyazaki, ISSCC’02
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Optimal VDD, VTh• Adjusting VDD, VTh trades of energy and delay
• We studied energy-limited design• And alternate ways for optimizing energy and delay together
• E.g. energy-delay product (EDP)
• Or EnDm, n,m > 1
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Optimal EDP Contours
• Plot of EDP curves in VDD, VTh plane
Gonzalez, JSSC 8/97EECS241B L23 SLEEP 54
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Topology Inverter Adder Decoder(ELk/ESw)ref 0.1% 1% 10%
Technology parameters (Vddmax, Vth
ref) rarely optimal
Reference Design:Dref (Vdd
max,Vthref)
Large variation in optimal circuit parameters Vddopt, Vth
opt, wopt
Vddmax
Vddmin Vth
min
Vthmax
Sizing, Supply, Threshold Optimization
EECS241B L23 SLEEP 55
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Delay (Dref)
ReferenceDesign(Dref,Eref)
Energy efficient curvef (W,Vdd,Vth)
(Dref,Emin)
(Dmin,Eref)
Ener
gy (E
ref)
Sensitivity W Vdd Vth(Dref,Eref) 1.5 0.2
(Dref,Emin) 1
(Dmin,Eref) 22 16 22
40% delay improvement without energy penalty
-80%
-40%
80% of energy savedwithout delay penalty
Result: E-D Tradeoff in an Adder
EECS241B L23 SLEEP 56
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Energy-constrained delay
• Active power
f = 1/LDtp
• Leakage power
• Eliminate one variable(VTh) and find Pmin(VDD)
Nose, ASP-DAC’00
2DDact fCVP
DDS
VV
leak VeIPDDTh
0
EECS241B L23 SLEEP 57
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Minimum energy: ESw = 2ELk
10-2
10-1
100
101
0
0.2
0.4
0.6
0.8
1
ELeakage/ESwitching
EO
p / no
min
al E
Op
ref
nominalparallelpipeline
Vthref-180mV
0.81Vddmax
Vthref-95mV
0.57Vddmax
Vthref-140mV
0.52Vddmax
2
lnLk Sw opt
d
avg
E EL K
Optimal designs have high leakage (ELk/ESw ≈ 0.5)
Large (ELk/ESw)opt
Flat EOp minimum Topology dependent
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Subthreshold Optimum
f = 30kHz Minimum is independent of VT
Calhoun, JSSC 9/05EECS241B L23 SLEEP 59
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Next Lecture
• We finished low-power design
• Next is clocks and supplies
EECS241B L23 SLEEP 60