![Page 1: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/1.jpg)
ECE 448 – FPGA and ASIC Design with VHDL
Lecture 13
PicoBlaze I/O & Interrupt Interface
![Page 2: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/2.jpg)
2ECE 448 – FPGA and ASIC Design with VHDL
Required reading
• P. Chu, FPGA Prototyping by VHDL Examples
Chapter 16, PicoBlaze I/O Interface
Chapter 17, PicoBlaze Interrupt Interface
![Page 3: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/3.jpg)
Syntax and Terminology
Syntax Example Definition
sX
KK
PORT(KK)
PORT((sX))
RAM(KK)
s7
ab
PORT(2)
PORT((s1))
RAM(4)
Value at register 7
Value ab (in hex)
Input value from port 2
Input value from the port specified by register s1
Value from the RAM location 4
![Page 4: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/4.jpg)
Addressing modes
Direct mode
ADD sa, sf
INPUT s5, 2a
sa + sf sa
PORT(2a) s5
Indirect mode
STORE s3, (sa)
INPUT s9, (s2)
s3 RAM((sa))
PORT((s2)) s9
s7 – 07 s7
s2 + 08 + C s2
Immediate mode
SUB s7, 07
ADDCY s2, 08
![Page 5: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/5.jpg)
5
Output Decoding of Four Output Registers
ECE 448 – FPGA and ASIC Design with VHDL
![Page 6: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/6.jpg)
Output Instructions
OUTPUT sX, KK
PORT(KK) <= sX
OUTPUT sX, (sY)
PORT((sY)) <= sX
DIR
IND
C Z
− −
− −
![Page 7: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/7.jpg)
7
Timing Diagram of an Output Instruction
ECE 448 – FPGA and ASIC Design with VHDL
![Page 8: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/8.jpg)
8
Truth Table of a Decoding Circuit
ECE 448 – FPGA and ASIC Design with VHDL
![Page 9: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/9.jpg)
Input Instructions
INPUT sX, KK
sX <= PORT(KK)
INPUT sX, (sY)
sX <= PORT((sY))
DIR
IND
C Z
− −
− −
![Page 10: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/10.jpg)
10
Block Diagram of Four Continuous-Access Ports
ECE 448 – FPGA and ASIC Design with VHDL
![Page 11: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/11.jpg)
11
Timing Diagram of an Input Instruction
ECE 448 – FPGA and ASIC Design with VHDL
![Page 12: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/12.jpg)
12
Block Diagram of Four Single-Access Ports
ECE 448 – FPGA and ASIC Design with VHDL
![Page 13: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/13.jpg)
13
FIFO Interface
ECE 448 – FPGA and ASIC Design with VHDL
FIFO
clk rst
8din dout
full empty
write read
clk rst
8
![Page 14: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/14.jpg)
14
Operation of the First-Word Fall-Through FIFO
ECE 448 – FPGA and ASIC Design with VHDL
![Page 15: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/15.jpg)
15
Operation of the “Standard” FIFO
ECE 448 – FPGA and ASIC Design with VHDL
−−−−−
A B C D
![Page 16: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/16.jpg)
16
Interrupt Flow
ECE 448 – FPGA and ASIC Design with VHDL
![Page 17: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/17.jpg)
17
Timing Diagram of an Interrupt Event
ECE 448 – FPGA and ASIC Design with VHDL
![Page 18: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/18.jpg)
18ECE 448 – FPGA and ASIC Design with VHDL
![Page 19: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/19.jpg)
Interrupt Related Instructions
RETURNI ENABLE
PC <= STACK[TOS] ; TOS <= TOS – 1;
I <= 1; C<= PRESERVED C; Z<= PRESERVED Z
RETURNI DISABLE
PC <= STACK[TOS] ; TOS <= TOS – 1;
I <= 0; C<= PRESERVED C; Z<= PRESERVED Z
ENABLE INTERRUPT
I <=1;
DISABLE INTERRUPT
I <=0;
![Page 20: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/20.jpg)
20
Interrupt Interface with a Single Event
ECE 448 – FPGA and ASIC Design with VHDL
![Page 21: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/21.jpg)
21
Interrupt Interface with Two Requests
ECE 448 – FPGA and ASIC Design with VHDL
![Page 22: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/22.jpg)
22
Time-Multiplexed Seven Segment Display
ECE 448 – FPGA and ASIC Design with VHDL
![Page 23: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/23.jpg)
23
Block Diagram of the Hexadecimal Time-Multiplexing Circuit
ECE 448 – FPGA and ASIC Design with VHDL
![Page 24: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062315/56814ffe550346895dbdc5ca/html5/thumbnails/24.jpg)
24
Hexadecimal Multiplexing Circuit Based on PicoBlaze and mod-500 Counter
ECE 448 – FPGA and ASIC Design with VHDL