Download - Lect 07 Differential Amp
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EE4340 / EECT 5340 Analog IC Analysis and Design Fall 2014
Topic 7. Differential Amplifiers
Jin Liu Ph.D.
Professor
UT Dallas
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Page 2
Differential Amplifiers Very Important
Differential amplifier is among the most important circuit inventions
Differential operation has become the dominant choice in todays high-performance analog and mixed signal circuits
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Page 3
Single-ended and Differential Operation
A single-ended signal is measured with respect to a fixed potential
A differential signal is measured between two nodes that have equal and opposite signal excursions around a fixed potential.
Common-mode (CM) level.
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Page 4
Immunity of Environmental Noise
Corruption of a signal due to
coupling
Reduction of coupling
by differential operation
V+ = Vcm+Vid/2
V- = Vcm-Vid/2
Vcm = (V+ + V-)/2
Vid = V+ - V-
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Page 5
Effect of Supply Noise
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Page 6
Differential Distribution of Noisy Lines
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Page 7
Major Advantages of Differential Signaling
Immunity of Environmental Noise
Noise coupling from digital lines
Power supply noise
Differential noisy lines
Increase the maximum achievable voltage swing (x2)
-1v
1v
0v Single-ended swing: 2v
-1v to 1v
Differential swing: 4v
-2v to 2v
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Page 8
Basic Differential Pair
AKA: Source-coupled pair or long tailed pair
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Page 9
Input-output Characteristics
When Vin1
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Page 10
Input Common Mode Range (ICMR)
1. Tie both inputs together
2. Sweep the input voltage and
find the input voltage range in
which all transistors are
saturated
Vin,CM=Vgs1+Vod3=Vth1+Vod1+Vod3
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Page 11
Input Common Mode Range
],2
min[ 2,1,31 DDTSS
DDDCMinODGS VVI
RVVVV
VGS1=VT1+sqrt{2*Iss/2/[K*(W/L)1]}
Iss Id1=Id2=Id3/2=Iss/2
VOD3=sqrt{2*Iss/[K*(W/L)3]}
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Page 12
Large Signal Analysis
Suppose M1 and M2 are saturated
21
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Large Signal Analysis
2
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Squaring both sides,
Also
Then
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Page 14
Large Signal Analysis
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Sign of Id1-Id2, and Vin1-Vin2
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Page 15
Large Signal Analysis
DSSoxnv
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inSSoxn
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Page 16
Small Signal Analysis Differential Mode
Half-circuit concept Node P is a virtual AC ground
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Page 17
Lemma
Consider above circuit, where D1 and D2 represent any
three-terminal active device. Suppose Vin1 changes from Vo
to Vo+Vin and Vin2 from Vo to Vo-Vin. Then, if the
circuit remains linear, Vp does not change
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Page 18
Prove
Assume V1 and V2 have equilibrium value of Va and change
by V1 and V2. The output currents then change by gmV1
and gmV2. Since I1+I2=IT, gmV1+gmV2=0, i.e. V1= -
V2. Also, Vin1-V1=Vin2-V2, thus Vo+Vin-(Va+V1)=Vo-
Vin-(Va+V2). Consequently, 2Vin=V1-V2=2V1.
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Page 19
Small Signal Gain - Differential
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Page 20
Differential Pair with MOS Loads - Gain
4,3
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Page 21
Differential Pair with MOS Loads _ICMR
Vin>Vgs1+Vds(sat, Iss), Vgs1=sqrt[2*Iss/2/(KW/L)]+Vth1
For M1 in sat, Vout>Vin-Vth1,
Vin
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Page 22
Differential Pair with MOS Loads _Output Swing
Vcm+Vid/2
Vcm-Vid/2
Vout1Vdd-Vsg3, (Id3=Iss)
Vout1>Vcm-Vth1
Vout1Vcm-Vth1
Vcm+Vid/2
Vcm-Vid/2
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Differential Pair with MOS Loads
)||( 7551331 oomoommv rrgrrggA
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Page 24
Common Mode Response
SS
m
D
CMin
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inind
ininCM
dCMin
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R
v
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2
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,
21,
21
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2
1
In symmetric circuit, input CM
variations disturb the bias points,
alternating the small signal gain
and possibly limiting the output
voltage swings. Node P is not a AC ground!!
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Page 25
Common Mode Response (2)
VDD
RD
Vin,CM
2RSS
Vout
M1
VDD
RD
YX
M2
M1
Vin,CM
P
2RSS
RD
2RSS
)21(
)21(
)]21([
)21(
)]21([
21
,SSm
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mm
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gG
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Common Mode Response
Variation of output CM level, in the absence of mismatch
Av,CM Conversion of input common-mode variations to differential variation at the output
Circuit component mismatch
Asymmetrical topology
Av,CM-DM
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Component Mismatch
DSSm
m
CM,in
yX
DMCM
DDSSm
mCM,iny
DSSm
mCM,inX
RRg21
g
V
VVA
)RR(Rg21
gVV
RRg21
gVV
Common mode change at the
input introduces differential
change at the output
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Page 28
CMRR Common Mode Rejection Ratio
DMCM
DM
A
ACMRR
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Page 29
Differential Amplifier with Active Current Mirror Load
Active current mirror
that process signal
When Vin1 decreases and Vin2 increase, more current flows through
M2 and M4, Vout decreases. When Vin1
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Page 30
Differential Amplifier with Active Current Mirror Load Large signal analysis cont.
Active current mirror
that process signal
When Vin1 increase and Vin2 decreases, more current flows through
M1 and M3, Vout increases. When Vin1>>Vin2, M2 is off, zero
current flows through M2,M4. M4 operates in deep triode region,
Vout=VDD
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Page 31
Differential Amplifier with Active Current Mirror Load Large signal analysis cont.
Active current mirror
that process signal
When Vin1=Vin2, each branch has half the tail current, Vout = VF
assuming perfect symmetry.
In reality, however, asymmetries in the circuit may result a large
deviation in Vout, possibly driving M2 or M4 into the triode region.
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Page 32
Large signal analysis Input & Output Swing
Active current mirror
that process signal
For M2 to be saturated, Vout>Vin2-Vth2. For maximum swing
range, the input common mode level should be as small as possible.
Minimum input common mode level to keep all transistors saturated
is Vod5+Vgs1,2
The direct relationship between the input CM level and the output
swing in this circuit is a critical drawback.
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Page 33
Small Signal Analysis
Asymmetry in two branches causes
small voltage swing in P.
If ignore this swing, P can be assumed
to be virtual ground.
(Refer to the Razavi book on analysis
when P is NOT assumed virtual ground.
The final result after approximation
leads to the same answer
here.)
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Page 34
Small Signal Analysis Av, Gm and Rout
Av=Gm Rout
Gm is short circuit transconductance;
it is calculated with the circuit setup
on the left. 21
inm
vg
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inm
vg
22
inm
vg
)||(
||
2
22
242,1
24
2,121
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in
outm
inm
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v
iG
vg
vgiout
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Common Mode Properties
Assuming symmetry,
Vout=VF
)||()21(
21
1
)||(||
21
1
2
1
2||
2
1
4,32,14,32,1
2,14,3
2,1
4,32,12,1
2,14,3
2,1
2,1
4,3
4,3
,
OOmm
mm
m
OOm
CM
DM
mm
m
m
O
m
CMin
VoutCM
rrgRssg
Rssgg
g
rrg
A
ACMRR
Rssgg
g
Rssg
r
g
VA
Even with perfect
symmetry, the output signal
is corrupted by input CM
variation a drawback that
does not exist in fully
differential circuits.
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Homework #6
Due on 10/23/2014