Download - Lead Lag Handout
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EE 3CL4, §61 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
EE3CL4:Introduction to Linear Control Systems
Section 6: Design of Lead and Lag Controllers usingRoot Locus
Tim Davidson
McMaster University
Winter 2014
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EE 3CL4, §62 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Outline
1 Compensators
2 Lead compensationDesign via Root LocusLead Compensator example
3 Cascade compensation and steady-state errors
4 Lag CompensationDesign via Root LocusLag compensator example
5 Prop. vs Lead vs Lag
6 Concluding Insights
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EE 3CL4, §64 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Compensators• Early in the course we provided some useful guidelines
regarding the relationships between the pole positionsof a system and certain aspects of its performance
• Using root locus techniques, we have seen how thepole positions of a closed loop can be adjusted byvarying a parameter
• What happens if we are unable to obtain thatperformance that we want by doing this?
• Ask ourselves whether this is really the performancethat we want
• Ask whether we can change the system,say by buying different components
• seek to compensate for the undesirable aspects of theprocess
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EE 3CL4, §65 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Cascade compensation
• Usually, the plant is a physical process• If commands and measurements are made electrically,
compensator is often an electric circuit• General form of the compensator is
Gc(s) =Kc
∏Mi=1(s + zi)∏n
j=1(s + pj)
• Therefore, the cascade compensator adds open looppoles and open loop zeros
• These will change the shape of the root locus
![Page 5: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/5.jpg)
EE 3CL4, §66 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Compensator design
• Where should we put new poles and zeros to achievedesired performance?
• That is the art of compensator design
• We will consider first order compensators of the form
Gc(s) =Kc(s + z)
(s + p)=
K̃c(1 + s/z)
(1 + s/p), where K̃c = Kcz/p
• with the pole −p in the left half plane• and the zero, −z in the left half plane, too
• For reasons that will soon become clear• when |z| < |p|: phase lead network• when |z| > |p|: phase lag network
![Page 6: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/6.jpg)
EE 3CL4, §68 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Lead compensation
Gc(s) =Kc(s + z)
(s + p)
with |z| < |p|. That is, zero closer to origin than pole
Let p = 1/τp and z = 1/(αleadτp). Since z < p, αlead > 1.Define K̃c = Kcz/p = Kc/αlead. Then
Gc(s) =Kc(s + z)
(s + p)=
K̃c(1 + αleadτps)
(1 + τps)
![Page 7: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/7.jpg)
EE 3CL4, §69 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Lead compensationWith |z| < |p|, αlead > 1, Gc(s) = Kc(s+z)
(s+p) =K̃c(1+αleadτps)
(1+τps)
• Frequency response:
Gc(jω) =K̃c(1 + jωαleadτp)
(1 + jωτp)
• Bode diagram (in the figure, K1 = K̃c)
• Between ω = z and ω = p, |Gc(jω)| ≈ K̃cωαleadτp• What kind of operator has a frequency response with
magnitude proportional to ω? Differentiator• Note that the phase is positive. Hence “phase lead”
![Page 8: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/8.jpg)
EE 3CL4, §610 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
A passive phase lead network
Homework: Show that V2(s)V1(s) has the phase lead
characteristic
![Page 9: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/9.jpg)
EE 3CL4, §611 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Active lead and lag networks
Here’s an example of an active network architecture.
![Page 10: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/10.jpg)
EE 3CL4, §612 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Principles of Lead design viaRoot Locus
• The compensator adds poles and zeros to the P(s) inthe root locus procedure.
• Hence we can change the shape of the root locus.
• If we can capture desirable performance in terms ofpositions of closed loop poles
• then compensator design problem reduces to:• changing the shape of the root locus so that these
desired closed-loop pole positions appear on the rootlocus
• finding the gain that places the closed-loop polepositions at their desired positions
• What tools do we have to do this?• Phase criterion and magnitude criterion, respectively
![Page 11: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/11.jpg)
EE 3CL4, §613 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Root Locus Principles• The point s0 is on the root locus of P(s) if 1 + KP(s0) = 0.
• In first order compensator design with G(s) =KG
QMi=1(s+zi )Qn
j=1(s+pj )
and Gc = Kc(s+z)(s+p) , we have P(s) = (s+z)
(s+p)
QMi=1(s+zi )Qnj=1(s+pj )
andK = KcKG. We will restrict attention to the case of K > 0
• Phase cond. s0 is on root locus if ∠P(s0) = 180◦ + k360◦:
M∑i=1
(angle from −zi to s0)−n∑
j=1
(angle from −pj to s0)
+ (angle from −z to s0)− (angle from −p to s0)= 180◦ + k 360◦
• Mag. cond. If s0 satisfies phase condition, the gain that putsa closed-loop pole at s0 is K = 1/|P(s0)|:
K =
∏nj=1(dist from −pj to s0)∏Mi=1(dist from −zi to s0)
× (dist from −p to s0)
(dist from −z to s0)
![Page 12: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/12.jpg)
EE 3CL4, §614 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
RL design: Basic procedure1 Translate design specifications into desired positions of
dominant poles
2 Sketch root locus of uncompensated system to see if desiredpositions can be achieved
3 If not, choose the positions of the pole and zero of thecompensator so that the desired positions lie on the rootlocus (phase criterion), if that is possible
4 Evaluate the gain required to put the poles there(magnitude criterion)
5 Evaluate the total system gain so that the steady-state errorconstants can be determined
6 If the steady state error constants are not satisfactory, repeat
This procedure enables relatively straightforward design ofsystems with specifications in terms of rise time, settling time, andovershoot; i.e., the transient response.For systems with steady-state error specifications, Bode (andNyquist) methods may be more straightforward (later)
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EE 3CL4, §615 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Lead Comp. example
Consider a case with G(s) = 1s(s+2) and H(s) = 1.
Design a lead compensator to achieve:
• damping coefficient ζ ≈ 0.45 and
• velocity error constant Kv = lims→0 sGc(s)G(s) > 20
• swift transient response (small settling time)
What to do?
• Can we achieve this with proportional control?
• If not we will attempt lead control
![Page 14: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/14.jpg)
EE 3CL4, §616 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Attempt prop. control
• Sketch root locus of 1s(s+2)
• Sketch rays of angle cos−1(0.45) ≈ 60◦ to neg. real axis• Are there intersections? Yes• If so, what is the corresponding value of K = KPKG?
K = d1d2 = 5• Does that K generate a large enough velocity error const.?
No, Kv = 2.5 :(• Do the closed-loop poles have responses that decay
quickly? No, Ts ≈ 4s
![Page 15: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/15.jpg)
EE 3CL4, §617 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Prop. control, step response
![Page 16: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/16.jpg)
EE 3CL4, §618 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Lead compensated design
• Plot poles of G(s).Where should the closed-loop poles be? cos−1(0.45) ≈ 60◦
• Note that the settling time is not specified; it only needs to besmall. This provides design flexibility.
• However, we need a large Kv which will require large gain.Need desired positions far from open loop poles.
• Let’s start with desired roots at −4± j8• This pair has Ts = 1s and ωn =
√42 + 82 ≈ 8.9
![Page 17: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/17.jpg)
EE 3CL4, §619 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Lead Comp. example
• Now where to put the zero and pole? (Centroid denoted ca)
• Rule of thumb: put zero under desired root, or just to the left
• Determine position of the pole using angle criterion∑angles from OL zeros−
∑angles from OL poles = 180◦
∼ 90− (116 + 104 + θp) = 180=⇒ θp ≈ 50
• Hence pole at −p ≈ −10.86
![Page 18: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/18.jpg)
EE 3CL4, §620 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Lead Comp. example
• Gain of compensated system:
Prod. dist. from open-loop polesProd. dist. from open-loop zeros
=d1d2dp
dz
≈ 8.94(8.25)(10.54)
8≈ 97.1
• Hence compensated open loop: Gc(s)G(s) = 97.1(s+4)s(s+2)(s+10.86)
• Velocity constant: Kv = lims→0 sGc(s)G(s) ≈ 17.9 :(
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EE 3CL4, §621 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
What to do now?
• We tried hard, but did not achieve the design specs• Let’s go back and re-examine our choices• Zero position of compensator was chosen via rule of
thumb• Can we do better?
Yes, but two parameter design becomes trickier.• What were other choices that we made?• We chose desired poles to be of magnitude ωn ≈ 8.9• We could choose them to be further away
(faster transient response)• By how much?• Show that when desired poles have ωn = 10 as well as
the required ζ ≈ 0.45, then the choice of z ≈ 4.47,p ≈ 12.5 and KC ≈ 125 results in Kv ≈ 22.3
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EE 3CL4, §622 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Root Locus, new lead comp.
Centroid denoted ca
![Page 21: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/21.jpg)
EE 3CL4, §623 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
New lead comp.Prop.-contr. Lead contr.
Controller, GC(s) 5 125(s+4.47)(s+12.5)
OL TF, GC(s)G(s) 5s(s+2)
125(s+4.47)(s+12.5)
1s(s+2)
CL TF, Y (s)R(s)
5s(s+2)+5
125(s+4.47)s(s+2)(s+12.5)+125(s+4.47)
CL poles −1± j2 −4.47± j8.94, −5.59
CL zeros ∞,∞ −4.47,∞,∞
CL TF, again 5s2+2s+5
131(1+0.013s)s2+8.94s+100 −
1.71s+5.59
• Complex conjugate poles still dominate• Closed-loop zero at -4.47 (which is also an open-loop
zero) reduces impact of closed-loop pole at -5.59; seealso slide 48 of Section 3: Fundamentals of Feedback
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EE 3CL4, §624 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
New lead comp., ramp response
![Page 23: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/23.jpg)
EE 3CL4, §625 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
New lead comp., rampresponse, detail
![Page 24: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/24.jpg)
EE 3CL4, §626 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
New lead comp., step response
Note faster settling time than prop. controlled loop,However, the CL zero has increased the overshoot a little
Perhaps we should go back and re-design for ζ ≈ 0.40in order to better control the overshoot
![Page 25: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/25.jpg)
EE 3CL4, §627 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Outcomes• Root locus approach to phase lead design was
reasonably successful in terms of putting dominantpoles in desired positions; e.g., in terms of ζ and ωn
• We did this by positioning the pole and zero of the leadcompensator so as to change the shape of the rootlocus
• However, root locus approach does not provideindependent control over steady-state error constants(details upcoming)
• That said, since lead compensators reduce the DC gain(they resemble differentiators), they are not normallyused to control steady-state error.
• The goal of our lag compensator design will be toincrease the steady-state error constants, withoutmoving the other poles too far
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EE 3CL4, §629 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Cascade compensation
• Throughout this lecture, and all the discussion on cascadecompensation, we will consider the case in which H(s) = 1.
• We will consider first order compensators of the form
Gc(s) =K (s + z)
(s + p)
with the pole, −p, and the zero, −z, both in the left half plane
• when |z| < |p|: phase lead network
• when |z| > |p|: phase lag network
![Page 27: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/27.jpg)
EE 3CL4, §630 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Steady-state errors
If closed loop stable, steady state error for input R(s):
ess = limt→∞
e(t) = lims→0
sR(s)
1 + GC(s)G(s)
Let G(s) =KG
Qi (s+zi )Q
j (s+pj )and consider GC(s) = KC(s+z)
(s+p)
• Consider the case in which G(s) is a type-0 system.• Steady state error due to a step r(t) = Au(t):
ess = A1+Kposn
, where
Kposn = GC(0)G(0) =KCz
pKG
∏i zi∏
j pj
• Note that for a lead compensator, z/p < 1,
• So lead compensation may degrade steady-state errorperformance
Aside: What about ess of step for Type ≥ 1 systems?
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EE 3CL4, §631 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Steady-state error
• Now, consider the case in which G(s) is a type-1system, G(s) =
KGQ
i (s+zi )s
Qj (s+pj )
• Steady-state error due to a ramp r(t) = At : ess = A/Kv ,where the velocity constant is
Kv = lims→0
sGc(s)G(s) =KCz
pKG
∏i zi∏
j pj
• Once again, lead compensation may degradesteady-state error performance
• Is there a way to increase the value of these errorconstants while leaving the closed loop poles inessentially the same place as they were in anuncompensated system? Perhaps |z| > |p|?
![Page 29: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/29.jpg)
EE 3CL4, §633 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Lag compensation
Gc(s) =Kc(s + z)
(s + p)
with |z| > |p|. That is, pole closer to origin than zero
Let z = 1/τz and p = 1/(αlagτz). Since z > p, αlag > 1.Define K̃c = Kcz/p = Kcαlag. Then
Gc(s) =Kc(s + z)
(s + p)=
K̃c(1 + τzs)
(1 + αlagτzs)
![Page 30: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/30.jpg)
EE 3CL4, §634 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Frequency response
Gc(jω) =K̃C(1 + jωτz)
(1 + jωαlagτz)
Magnitude• Low frequency gain: K̃C
• Corner freq. in denominator at ωp = p = 1/(αlagτz)
• Corner freq. in numerator at ωz = z = 1/τz
• ωp < ωz
• High frequency gain: K̃C/αlag = KC
Phase• φ(ω) = atan(ωτz)− atan(αlagωτz)
• At low frequency: φ(ω) = 0• At high frequency: φ(ω) = 0• In between: negative, with max. lag at ω =
√zp
![Page 31: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/31.jpg)
EE 3CL4, §635 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Bode Diagram, with K̃c = 1
Note integrative characteristic
![Page 32: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/32.jpg)
EE 3CL4, §636 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
A passive phase lag network
![Page 33: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/33.jpg)
EE 3CL4, §637 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Active lead and lag networks
Here’s an example of an active network architecture.
![Page 34: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/34.jpg)
EE 3CL4, §638 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Lag compensator design• Lag compensator: Gc(s) = Kc
s+zs+p . with |z| > |p|.
• Recall position error constant for compensated type-0system and velocity error constant for compensated type-1system:
Kposn =KCz
pKG
∏i zi∏
j pj, Kv =
KCzp
KG∏
i zi∏j pj
where in the latter case the product in the denominator isover the non-zero poles.
Design Principles
• We don’t try to reshape the uncompensated root locus.
• We just try to increase the value of the desired error constantby a factor αlag = z/p without moving the poles (well notmuch)
• Reshaping was the goal of lead compensator design
![Page 35: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/35.jpg)
EE 3CL4, §639 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Lag compensator design
Design principles:• Don’t reshape the root locus
• Adding the open loop pole and zero from thecompensator should only result in a small change to theangle criterion for any point on the uncompensated rootlocus
• Angles from compensator pole and zero to any point onthe locus must be similar
• Pole and zero must be close together
• Increase value of error constant:• Want to have a large value for αlag = z/p.• How can that happen if z and p are close together?• Only if z and p are both small, i.e., close to the origin
![Page 36: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/36.jpg)
EE 3CL4, §640 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Lag comp. design via RootLocus
1 Obtain the root locus of uncompensated system2 From transient performance specs, locate suitable
dominant pole positions on that locus3 Obtain the loop gain for these points, K = KPKG;
hence the (closed-loop) steady-state error constant4 Calculate the necessary increase. Hence αlag = z/p5 Place pole and zero close to the origin (with respect to
desired pole positions), with z = αlagp.Typically, choose z and p so that their angles to desiredpoles differ by less than 1◦.
6 Set KC = KP
What if there is nothing suitable at step 2?• Perhaps do lead compensation first,• then lag compensation on lead compensated plant.
i.e., design a lead-lag compensator
![Page 37: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/37.jpg)
EE 3CL4, §641 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Example
Let’s consider, again, the case with G(s) = 1s(s+2) .
Design a lag compensator to achieve damping coefficientζ ≈ 0.45 and velocity error constant Kv > 20
Note: we will get a different closed loop from our leaddesign.
First step, obtain uncompensated root locus, and locatedesired dominant pole locations
![Page 38: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/38.jpg)
EE 3CL4, §642 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Example
• Gain required to put closed loop poles in desired position =prod. distances from open loop poles
• That is, K = 2.242 = 5. Therefore KP = K/KG = 5
• Velocity error const: Kv ,unc = lims→0 sKPG(s) = K/2 = 2.5
• The increase required is 20/2.5 = 8
• That implies must choose p = z/8, where z is chosen to beclose to the origin with respect to dominant closed-loop poles
![Page 39: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/39.jpg)
EE 3CL4, §643 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Example
Let’s choose z = 0.1. Hence, p = 1/80.
![Page 40: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/40.jpg)
EE 3CL4, §644 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Example
Root locus of lag comp’d system with GC(s) = KC(s+0.1)(s+1/80)
• �’s: closed-loop poles for prop.-control with KP = 5• ×’s: open-loop poles of lag comp’d system• ◦: OL zero of lag comp’d system; also a CL zero• 4’s: Closed-loop poles for lag-control with KC = 5
![Page 41: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/41.jpg)
EE 3CL4, §645 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
ExampleProp.-contr. Lag contr.
Controller, GC(s) 5 5(s+0.1)(s+1/80)
OL TF, GC(s)G(s) 5s(s+2)
5(s+0.1)(s+1/80)
1s(s+2)
CL TF, Y (s)R(s)
5s(s+2)+5
5(s+0.1)s(s+2)(s+1/80)+5(s+0.1)
CL poles −1± j2 −0.955± j1.979, −0.104
CL zeros ∞,∞ −0.1,∞,∞
CL TF, again 5s2+2s+5
4.999(1+7×10−4s)s2+1.909s+4.827 + −0.004
s+0.104
• Complex conjugate poles still dominate• Closed-loop zero at -0.1 (which is also an open-loop
zero) reduces impact of closed-loop pole at -0.104; seealso slide 48 of Section 3: Fundamentals of Feedback
![Page 42: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/42.jpg)
EE 3CL4, §646 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Ramp response
![Page 43: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/43.jpg)
EE 3CL4, §647 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Ramp response, detail
![Page 44: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/44.jpg)
EE 3CL4, §648 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Step response
Note longer settling time of lag controlled loop,and slight increase in overshoot, due to CL zero
![Page 45: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/45.jpg)
EE 3CL4, §650 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Design Comparisons
For given example: G(s) = 1s(s+2) , ζ ≈ 0.45, Kv ≥ 20.
Prop.-contr. Lead contr. Lag contr.
GC(s) 5 125(s+4.47)(s+12.5)
5(s+0.1)(s+1/80)
Y (s)R(s)
5s2+2s+5
131(1+0.013s)
s2+8.94s+100− 1.71
s+5.594.999(1+7×10−4s)
s2+1.909s+4.827+ −0.004
s+0.104
CL poles −1± j2 −4.47± j8.94, −5.59 −0.955± j1.979, −0.104
CL zeros ∞,∞ −4.47,∞,∞ −0.1,∞,∞
1/Kv 0.4 0.045 0.05
• Lag design retains similar CL poles to prop. design,plus a “slow” pole
• CL poles of lead design quite different• Lead and lag meet Kv specification (1/Kv = ess,ramp)
![Page 46: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/46.jpg)
EE 3CL4, §651 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Ramp response
![Page 47: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/47.jpg)
EE 3CL4, §652 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Ramp response, detail
![Page 48: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/48.jpg)
EE 3CL4, §653 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Step response
![Page 49: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/49.jpg)
EE 3CL4, §654 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Step response, detail
![Page 50: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/50.jpg)
EE 3CL4, §655 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Anything else to consider?
![Page 51: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/51.jpg)
EE 3CL4, §656 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Anything else to consider?
With H(s) = 1,
Y (s) =Gc(s)G(s)
1 + Gc(s)G(s)R(s) +
G(s)
1 + Gc(s)G(s)Td (s)
− Gc(s)G(s)
1 + Gc(s)G(s)N(s)
E(s) =1
1 + Gc(s)G(s)R(s)− G(s)
1 + Gc(s)G(s)Td (s)
+Gc(s)G(s)
1 + Gc(s)G(s)N(s)
![Page 52: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/52.jpg)
EE 3CL4, §657 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Response to step disturbance
![Page 53: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/53.jpg)
EE 3CL4, §658 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Response to step disturbance,detail early
![Page 54: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/54.jpg)
EE 3CL4, §659 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Response to step disturbance,detail late
Homework: Show that ess for a step disturbance is 0.2,0.0225 and 0.025 for prop., lead, lag, resp.
![Page 55: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/55.jpg)
EE 3CL4, §660 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Error due to Gaussian sensornoise
![Page 56: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/56.jpg)
EE 3CL4, §661 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Bode diagram ofGC(s)G(s)/(1 + GC(s)G(s))
![Page 57: Lead Lag Handout](https://reader030.vdocuments.site/reader030/viewer/2022020213/577cc9df1a28aba711a4d182/html5/thumbnails/57.jpg)
EE 3CL4, §663 / 63
Tim Davidson
Compensators
LeadcompensationDesign via RootLocus
Lead Compensatorexample
Cascadecompensationandsteady-stateerrors
LagCompensationDesign via RootLocus
Lag compensatorexample
Prop. vs Leadvs Lag
ConcludingInsights
Insights
• If we would like to improve the transient performance ofa closed loop
• We can try to place the dominant closed-loop poles indesired positions
• One approach to doing that is lead compensator design• However, that typically requires the use of an amplifier
in the compensator, and hence requires a power supply• Broadening of bandwidth improves transient
performance but exposes loop to noise
• If we would like to improve the steady-state errorperformance of a closed loop without changing thedominant transient features too much
• We can consider designing a lag compensator toprovide the required gain
• However, that typically produces a “weak” slow pole thatslows the decay to steady state