Performance Analysis of Unified Power Quality
Conditioner based on Diode Clamped Multilevel
Inverter for 3-Phase 3-Wire System
Janardhana Kotturu
Department of Electrical Engineering
Indian Institute of Technology Roorkee
Roorkee, India 247667
e-mail: [email protected]
Pramod Agarwal
Department of Electrical Engineering
Indian Institute of Technology Roorkee
Roorkee, India 247667
e-mail: [email protected]
Abstract—This paper presents the implementation of mul-
tilevel unified power quality conditioner using diode clamped
multilevel inverter topology at three level employed to three
phase three wire system. The control strategy for shunt and
series converters of unified power quality conditioner is selected
based on unit template technique. The performance of the system
is evaluated for different power quality conditions like voltage
sags of single phase, two phase and three phase and unbalanced
conditions. The simulations of the system are implemented in the MATLAB simulink.
Keywords—unified power quality conditioner; diode clamped
multilevel inverter; PCC; phase shift modulation; votltage sag; PLL
I. INTRODUCTION
With increasing demand of customer needs, the use of power electronic devices and nonlinear loads in distribution systems and industries, power quality (PQ) problems such as unbalance voltage sag, swell, flicker and harmonics have become serious issues. The power plants prefer cost friendly simple solutions to protect some group of loads. The custom devices are then adapted if the simple solution are not enough especially for high technology plants. The supply of reliable power is based on the concept of custom power (CP) on the application power electronic controller [1].
The combined back-to-back converter can be interfaced with the utility system by connecting the two active inverter- based filters with a common DC link, in both series and parallel manner, thereby achieving simultaneous control of the utility and the voltage delivered to the load and is referred to as universal power conditioner [1], [2] and universal flow controller [3] when applied to electrical systems and at the transmission level respectively.
UPQC being one of the recent modern technologies achieving popularity in recent years as it has the capability to simultaneously compensate the PQ problems on both load and distributer side; as it is constructed by the combination of DVR and APF feature in one technology by DC link Back-to-back configuration. The important feature of this topology is that it allows the simultaneous regulation of voltage and improvement of power factor at the point of common coupling [PCC] [4].
The unique design of multilevel inverter allows the span of high voltage and also to reduce the device switching frequency without the need of transformers. It is seen that a diode clamped inverter, with all six phases of the back-to-back
converter sharing a common DC link, is capable of synthesizing a desired waveform from several levels of DC voltage [5]–[7]. Consequently an enticing prospect would be to integrate a multilevel diode clamped inverter into a universal power conditioner.
The features offered by multilevel universal power con- ditioner (UPQC-ML) are in-numerous when deciding to what type of control is to be used while compensating source voltage (voltage sag, unbalanced voltages, voltage harmonics, current harmonics or reactive power) and load currents playing an important role in the control of the back-to-back inverters [8], [9].
II. SYSTEM DESCRIPTION
A. Multilevel unified power quality conditioner (UPQC-ML)
Non-linear
and sensitive
loads
Supply
voltage
LC Filter
Series Filter Shunt Filter
ish Lsh
iLis
vs vL
vinj
vp
vn
Fig. 1. Multilevel unified power quality conditioner using three level diode
clamped inverter.
The conventional UPQC is realized by using two voltage source inverters (VSI) namely, series active filter and a shunt active filter and both the converters are connected back to back through a common DC link. The six numbers of IGBTs are required for the realization of each two level converter. In case of multilevel unified power quality conditioner (UPQC-ML), the two level inverters are replaced by multilevel inverters, whereas in the present work, three level diode clamped multilevel inverters are preferred. As shown in Fig. 1, the two diode clamped inverters are connected back to back
with a split DC link with two identical capacitors pC and nC .
The mid point of capacitors is taken as a neutral point for the
generation of three level output from the three level inverter. The three level diode clamped multilevel inverter consists of twelve numbers of IGBTs and six numbers of clamping diodes [10].
The supply side disturbances such as voltage sag, swell and unbalance is compensated by the series active filter which also comprises of VSI connected on to the split DC link and is also connected in series with the feeder through low pass filter
(LPF) and three single phase series transformers seT
individually on the AC side and the component responsible for power factor correction and compensation of load current harmonics is the shunt converter. This shunt filter is connected
to the AC side through a coupling inductor (shL ). The constant
average voltage across the DC storage capacitors pC and nC is
also maintained by the same [10], [11].
III. CONTROL STRATEGIES
In order to evaluate the performance of UPQC-ML using three level diode clamped topology, the unit template technique (UTT) is used for series and shunt converters of UPQC, whereas in-phase level shift modulation is used for the multilevel structure.
A. Control strategy of series converter
The series converter has to mitigate the distortions from the source voltage in order to maintain distortion free load voltage at PCC. So the converter will inject the voltage into
the system through series transformer seT . The control strategy
of series converter is shown in the Fig. 2.
PLLavbvcv
ref
lavref
lbvref
lcv
ref
lmv
Multicarrier
PWM 4
5
1
2
3
12
g
g
g
g
g
g
Phase
shifter
± 120o
Load
reference
voltage
generaror
Σ+-
lav lbv lcv
mav
mbv
mcv
aubucu
p
trvn
trv
Fig. 2. Control strategy of series converter.
In the unit template technique (UTT) [12], [13], the dis-
torted source voltages ( av , bv and cv ) are sensed and processed
through the phase locked loop (PLL) block to obtain unit magnitude reference signals. The PLL block can be used to maintain the synchronism especially when the supply voltages are distorted. The PLL block generates the unit magnitude quadrature vectors of sine and cosine signals
( sin t and cos t ). In order to generate the three phase unit
magnitude templates of aU , bU and cU ; the output signal of
PLL gets phase shifted by 0120 and 0120 . Mathematically the unit vectors are computed by using (1).
31
2 2
31
2 2
1 0sin
cos
a
b
c
U
U
U
(1)
The reference load voltage signals ref
laV , ref
lbV and ref
lcV at
PCC will be computed by multiplying three phase unit vectors
aU , bU and cU with a reference load voltage magnitude of ref
lmV as shown in (2).
ref
la a
ref ref
lb lm b
ref
lc c
V U
V V U
V U
(2)
In the present work, the reference load voltage magnitude ref
lmV is taken as 187.8 V. The reference load voltage signals
( ref
laV , ref
lbV and ref
lcV ) and the sensed actual load voltage
signals (laV ,
lbV and lcV ) are processed through the comparator
in order to generate the three modulating signals (maV ,
mbV and
mcV ) for the implementation of level shift modulation. Fig. 3,
shows the in-phase level shift modulation for three level diode clamped multilevel inverter [14].
Fig. 3. In-phase level shift modulation for three level inverter.
The ‘m’ level inverter requires ‘m-1’ number of carrier
signals, so two carrier signals, namely upper (p
trV ) and lower
triangular (n
trV ) signals are used for three level PWM [15].
Fig. 3, shows the one phase leg of three level diode clamped
multilevel inverter, where 1S and 3S , 2S and 4S are compli-
mented switches. The firing pulses for 1S and 3S are generated
by the PWM operation of upper triangular and modulating
signal and similarly pulses will be generated for 2S and 4S by
the PWM operation of lower triangular and modulating signal as shown in Fig. 3.
B. Control strategy of shunt converter
The control strategy for a shunt converter of multilevel UPQC is also selected based on Unit template technique [13], [16]. The block diagram of control strategy is shown in Fig. 4. This technique is also as same as that of control strategy of series converter, but generated three phase unit template vectors are multiplied by the output signal of voltage PI
controller (ref
smI ) in order to generate three phase reference
source currents (ref
sai , ref
sbi and ref
sci ) as shown in (3).
ref
sa a
ref ref
sb sm b
ref
sc c
i U
i I U
i U
(3)
The component ref
smI can be used to regulate the DC link
voltage against switching losses and sudden load changes and it is computed by processing the error through the voltage PI controllers. Despite from the two level inverter structure, the three level inverter will have split DC link consisting of two
equal capacitors pC and nC . The voltages p
dcV and n
dcV across
both the capacitors are sensed and processed through a summer and subtractor in order to evaluate the error, the
output of the summer is compared with the ref
dcV and output of
subtractor is compared with *ref
dcV . Fig. 5, shows the block
diagram of the DC link voltage regulator.
Multicarrier
PWM 4
5
1
2
3
12
g
g
g
g
g
g
p
trvn
trv
PLLavbvcv
ref
sairef
sbiref
sci
Phase
shifter
± 120o
Load
reference
voltage
generaror
Σ+-
sai sbi sci
mav
mbv
mcv
aubucu
ref
smI
Fig. 4. Control strategy of shunt converter.
ref
dcv
ref
smIPI
+
+-
+-
+- PI
+
+
+
*ref
dcv
p
dcv
n
dcv
Fig. 5. Block diagram of DC link voltage regulation.
Now the reference three phase source current signals (ref
sai , ref
sbi and ref
sci ) and the sensed actual source current signals
( sai , sbi and sci ) are processed through the comparator in order
to generate the three modulating signals ( maV , mbV and mcV ) for
the implementation of level shift modulation. It requires two
carrier signals of (p
trV ) and (n
trV ) as shown in Fig. 3.
IV. SIMULATION RESULTS AND DISCUSSION
The performance of diode clamped three level UPQC (UPQC-DCMLI) is tested with the considered load is made a combination of linear and nonlinear load. The linear load is considered as the R-L load and nonlinear load is taken as a three phase diode bridge rectifier with an R-L load on DC side. The complete is implemented in the environment of MATLAB Simulink. The performance is evaluated with the 20 % voltage sag of different types of three phase, two phase, single phase voltage sag and unbalanced supply voltage. The system parameters are chosen as listed out in the Appendix.
A. Performance of UPQC-DCMLI with nonlinear load
The performance of the system is evaluated at steady state without any sudden changes in the system. Fig. 6, shows the simulation results of UPQC-DCMLI with nonlinear load. The source current has become sinusoidal and free from the harmonics, leaving the load current non-sinusoidal with harmonic currents caused by the nonlinear load. The THD of the source current is improved from 23.47 % to 1.30 % by
connecting UPQC-DCMLI into the system. Fig. 7, shows the FFT analysis of source current and load current.
Fig. 6. Response of UPQC-DCMLI with nonlinear load.
Fig. 7. FFT analysis of source and load currents.
B. Performance of UPQC-DCMLI with three phase voltage
sag
To evaluate the performance of UPQC-DCMLI, the system is subjected to the three phase voltage sag on the
source side at the instant of st = 0.1 sec to 0.2 sec. Fig. 8,
shows the simulation results of the system with three phase voltage sag. The UPQC makes the load voltage at PCC remains constant irrespective of voltage sag on the system and also source current became sinusoidal, free from the harmonics caused by the nonlinear load.
Fig. 8. Response of UPQC-DCMLI with three phase voltage sag.
Fig. 9. Response of UPQC-DCMLI with two phase voltage sag.
Fig. 10. Response of UPQC-DCMLI with single phase voltage sag.
Fig. 11. Response of UPQC-DCMLI with unbalanced source voltage.
C. Performance of UPQC-DCMLI with two phase voltage
sag
The performance of the UPQC-DCMLI is evaluated for applying two phase sag on the supply side. The voltage sag
exists in the system for st = 0.1 sec to 0.2 sec. As observed in
the three phase voltage sag, the similar response is found even in the two phase voltage sag. The simulation results of UPQC-DCMLI are shown in Fig. 9. The system has good recovery characteristics and the response is very effective even before and after the sag period.
D. Performance of UPQC-DCMLI with single phase voltage
sag
To observe the performance of the UPQC based on multilevel inverter, single phase voltage sag is applied in the
source side of the system at st = 0.1 sec. The simulation results
are shown in Fig. 10, and it is observed that the performance is similar to three phase and two phase sags.
E. Performance of UPQC-DCMLI with unbalanced source
voltage
The system is also evaluated by applying the unbalanced
source voltage of av = 0.8 pu,
bv = 1.2 pu and cv = 1 pu.
Without UPQC-DCMLI, the voltage at PCC is same as that of the source voltage of unbalanced. After connecting the UPQC-DCMLI to the system, the voltage at PCC is maintained at 1 pu irrespective of the unbalance condition on the source side of the system. Fig. 11, shows the simulation results of the system with unbalanced source voltage.
V. CONCLUSION
The performance of the unified power quality conditioner is evaluated for nonlinear load and different types of voltage sags and unbalance condition in the system by using three level diode clamped multilevel inverter. It has the good recovery characteristics during transient and steady state conditions against voltage sags and unbalanced conditions and also the THD of the source current is improved from 23.47 % to 1.30 % by connecting UPQC-DCMLI into the system.
VI. APPENDIX
The parameters of the system are considered to the implementation of simulation are listed out in Table I.
TABLE 1. SYSTEM PARAMETERS
System parameter Parameter value
Source votlage 3-ph, 230 rmsV , 50 Hz
Line impedance R = 0.01 Ω, L = 0.5 mH
Low pass filter R = 3 Ω, C = 5 μF
Voltage controller pK = 0.4, iK = 0.2
DC link capacitance 3000 μF
3-ph RL load R = 20 Ω, L = 10 mH
3-ph rectifier load R = 10 Ω, L = 20 mH
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