162 • 2005 IEEE International Solid-State Circuits Conference 0-7803-8904-2/05/$20.00 ©2005 IEEE.

ISSCC 2005 / SESSION 8 / CIRCUITS FOR HIGH-SPEED LINKS AND CLOCK-GENERATORS / 8.7

8.7 A Low-Jitter 5000ppm Spread SpectrumClock Generator for Multi-channel SATATransceiver in 0.18µm CMOS

Hyung-Rok Lee1,2, Ook Kim2, Gijung Ahn2, Deog-Kyoon Jeong1

1Seoul National University, Seoul, Korea2Silicon Image, Sunnyvale, CA

As external storage devices are widely used, high-speed seriallinks connecting hosts and external devices are becoming popu-lar. Serial AT Attachment (SATA) is one of the most promisingtechnologies providing large bandwidth up to 3Gb/s with possibleextension to 6Gb/s in the near future. SATA specification [1]defines an EMI reduction method using spread-spectrum clock-ing (SSC), which reduces the peak EMI emission by spreadingcarrier frequency. EMI reduction using SSC has been studied andexplored in several papers [2, 3]. However, it is more important toconsider the time-domain impact of SSC in addition to the EMIpeak reduction since the major concern in serial data transmis-sion is signal integrity in time domain. A low-jitter spread-spec-trum clock generator using multiphase clocks and the ∆Σ modu-lator is presented in this paper. With oversampling digital CDRarchitecture [4], transmitters and receivers can share a singlePLL and the spread-spectrum clock generator can use the finemultiphase clocks that are already available for CDR withoutadditional complexity to the PLL. With 10-phase clocks, theamount of phase jump in the feedback signal to the PFD can beonly one-tenth of a conventional multi-modulus frequency syn-thesizer, thus, generating significantly less jitter [5]. In addition,the use of the ∆Σ modulator with a periodic input signal furtherreduces the jitter with exact 5000ppm spreading.

Figure 8.7.1 shows the block diagram of a dual-channel 2nd-gen-eration (3Gb/s) SATA transceiver and a jitter-measurementmethod with the SSC Generator (SSCG). The central PLL gener-ates a 1.5GHz clock and all the transmitters and receivers sharethe same clock. In measuring jitter in the presence of SSC, it isvery important to remove the intentionally introduced jitter andto extract only the random jitter. In other words, the jitter of TXdata should be measured with a proper reference clock which sep-arates jitter from SSC in the data stream. By setting the band-width for the golden PLL properly, the extracted reference clockfrom the golden PLL tracks SSC and removes the effect of its jit-ter.

Due to the finite feedback loop bandwidth, there is a timing dif-ference between the input and output of the PLL. Since the fre-quency of SSC varies from its nominal frequency to 5000ppmdownward, the accumulation of phase difference can be largeenough to close the eye significantly [6]. Figure 8.7.2(a) shows thesimulation result of SSC data jitter. Even with ideal SSC, thistracking skew can be as large as 53ps when the bandwidth of thegolden PLL is 0.9MHz. The golden PLL with 6MHz bandwidthoffering only 1.2ps skew is used for jitter comparison betweenvarious structures. As shown in Fig. 8.7.2(a), the amount of deter-ministic jitter due to SSC is inversely proportional to the amountof phase jump in the feedback signal to the PFD. Another way toreduce jitter is to increase the reference clock frequency.However, 25MHz reference clock is preferred since it is readilyavailable from a crystal instead of higher frequency crystal oscil-lator. With 10-phase clocks, a better result is achieved with muchsmaller phase jump while still using the 25MHz reference clock.Figure 8.7.2(b) shows the simulation results for this structurewith a behavioral-level simulator [7], and the amount of deter-ministic jitter is 10.3ps, which is only 0.03 UI for a 3Gb/s datastream.

Figure 8.7.3 shows the block diagram of the proposed spread-spectrum clock generator. It consists of an integer-N PLL gener-ating 1.5GHz 10-phase clocks, a phase-selection logic and a ∆Σmodulator. A periodic triangular profile is fed into the ∆Σ modu-lator to generate a spread-spectrum clock. The ∆Σ modulatorshapes the noise to a higher frequency and the smoothing effectof the PLL loop results in continuous frequency modulation froma discrete staircase input. The period of the input signal to the ∆Σmodulator is set to 33µs. Proper choice of division factor and mul-tiphase control allows the exact control of frequency shift. Forexample, 5000ppm lower frequency can be generated by a 3-phase jump, which reduces the period of feedback signal to thePFD by 3 multiphase spans. That is,

25MHz × 60 × (1 - 3/600) = 25MHz × 60 × 0.995 (1)

Other frequencies between 0 to 5000ppm can also be generatedby alternating the amount of phase jump according to the outputof the ∆Σ modulator.

Figure 8.7.4 shows the block diagram of a clock MUX and MUXcontrol logic. The MUX control logic is composed of a timing gen-erator and a MUX address controller. For a phase jump largerthan one, the timing generator evenly distributes multiple singlemultiphase jumps in a single PFD comparison period for a maxi-mum timing margin.

Figure 8.7.5 shows the measured jitter with SSC off and on. Theperiodic jitter due to SSC is around 13.6pspp (=30.2-16.6) whilerandom jitter is 3.2psrms. The measured modulation frequency isaround 30.1kHz and the modulation amount is 5000ppm asshown in Fig.8.7.6(a). In Fig. 8.7.6(b) and (c), we can see the effectof SSC in frequency domain. With SSC off, a single 1.5GHz toneis observed in Fig. 8.7.6(b). With SSC enabled, since the frequen-cy is modulated, the single tone is spread down. The spreadamount is 7.5MHz (5000ppm) and the nearest peak is located at7.25MHz below the nominal frequency with 9.8dB peak reduc-tion. Figure 8.7.7 shows the chip micrograph of the test chip. Thecore area is 1.75×0.94mm2. Modulation profile and the ∆Σ modu-lator are implemented with a lookup table and additional area forimplementing SSC is 0.072mm2. BER is less than 10-12 and nochange of BER is observed either with SSC on or off.

References:[1] Serial ATA Workgroup, “Serial ATA II: Electrical Specification,”Revision 1.0, May, 2004.[2] M. Sugawara et al., “1.5 Gb/s, 5150 ppm Spread Spectrum SerDes PHYwith a 0.3mW, 1.5Gb/s Level Detector for Serial ATA,” Symp. VLSICircuits, pp. 60-63, June, 2002.[3] M. Aoyama et al., “3 Gb/s, 5000ppm Spread Spectrum SerDes PHY withFrequency Tracking Phase Interpolator for Serial ATA,” Symp. VLSICircuits, pp. 107-110, June, 2003.[4] K. Lee et al., “A CMOS Serial Link for Fully Duplexed DataCommunication,” IEEE J. Solid-State Circuits, vol. 30, pp. 353-364, Apr.,1995.[5] C.H. Heng and B.S. Song, “A 1.8-GHz CMOS Fractional-N FrequencySynthesizer with Randomized Multiphase VCO,” IEEE J. Solid-StateCircuits, vol. 38, pp. 848-854, June, 2003.[6] K.B. Hardin et al., “Design Considerations of Phase-Locked LoopSystems for Spread Spectrum Clock Generation Compatibility,” IEEE Intl.Symp. on Electromagnetic Compatibility, pp. 302-307, Aug., 1997.[7] M. H. Perrott, “Fast and Accurate Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL/DLL Circuits,” DesignAutomation Conference, pp. 498-503, June, 2002.

163DIGEST OF TECHNICAL PAPERS •

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ISSCC 2005 / February 8, 2005 / Salon 1-6 / 11:45 AM

Figure 8.7.1: SATA transceiver block diagram and jitter measurementwith SSC.

Figure 8.7.2: Simulation result (a) jitter comparison (b) jitter with pro-posed architecture.

Figure 8.7.3: Spread-spectrum clock generator.

Figure 8.7.5: Measured jitter (a) with SSC off (b) with SSC on.Figure 8.7.6: (a) modulation profile (b) spectrum with SSC off(c) spectrum with SSC on.

Figure 8.7.4: Clock MUX and MUX control logic.

PLL10

Referenceclock

TX1

RX1

SSCgenerator

Golden PLLBW = fbaud/N

TX2

RX2

-

Jitter seperatedfrom SSC

1.5GHz

25MHzJitter with SSC

Extracted SSCcomponent

(a) (b)

0.03 UI

Reference25MHz PFD LPF VCO

/60

∆−Σ

To TX & RX10

10

MUXcontrol

CLK MUX

Modulation profile

mp<0:9>

CLK MUX andcontrol logic

D-FFMUXaddr ctrl D-FF

Clock divider &control logic

2:1MUX

Frommodulator

5:1MUX

mp1mp3mp5mp7mp9

5:1MUX

mp0mp2mp4mp6mp8

To PFD

even

odd

(a)

(b)

(a)

(b) (c)

2 1

8

From ∆Σmodulator

590 • 2005 IEEE International Solid-State Circuits Conference 0-7803-8904-2/05/$20.00 ©2005 IEEE.

ISSCC 2005 PAPER CONTINUATIONS

Figure 8.7.7: Chip micrograph.

PLLRX TX

Lookuptable

Channel 1 Channel 2

Controlblock

On-chipcap.

TX RX