The challenge of innovation driven curricula change. Insight into some major trends in IT and its impact on
Informatics curricula
Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
The Skills needed in ICT are changing !
With all due respect to other disciplines….
• If Newton were to resurrect he could continue to lecture Math where he left off….
• If Heisenberg were to resurrect he could continue to lecture Physics where he left off….
• If Turing were to resurrect he would find his whole compute model has disappeared and would have to sit in on the current lectures to catch up….
• The speed of change in ICT disciplines is enormous
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
3
The need for flexibility !
While the industry very much welcomes framework standards of skills at the highest possible level, there is also the need for much flexibility:
• Innovational needs
• Regional needs
• Industry needs
• Company needs
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
4
The need for flexibility !
• Innovational needs
– Technology evolves faster than curricula !
• Regional needs
– Countries have regional centers with different needs
• Industry needs
– Different industries have different needs
• Company needs
– Companies, based on their business, have different needs
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
5
The Next Challenge:
What to drop ?
What to incorporate ?
Here the 80/20 rule probably also applies
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
6
The Industry Model (?)
Second Cycle Degree
First Cycle Degree Fle
xib
ility
80 20
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Future Thrusts in ICT
We see (at least) three major future Thrusts:
Visual Computing
High Performance Computing
Green (by) IT / CleanTech
7
Visual Computing at Intel The Next Frontier
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Rich Interaction and ImmersionNew Content Spiral
Integrated WorldUser Generated
Social Networking
Users Collaborate & Play
Scenario Play
Virtual Teamroom
Users Create
World of Warcraft Avatar
Eiffel Tower in Google Earth
Users Explore and Learn
Qwaq Treefort Virtual Room Machinima Globalkids..org
Users Enhance the Actual World
West Nile Virus VisualizationVisualizing Real world information
Dust storm in Morocco
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
SOCIAL NETWORKINGConsumers increasingly use the Internet for Peering and Collaborating
USER-GENERATED CONTENTPrimary Role of the Internet Shifting From
Communications to Content
BROADBAND CONNECTIVITYSufficient bandwidth for interactive, online 3D experience
3D GRAPHICS & INTERACTIONConsumers interact visually in 3D, beyond the
Keyboard, Mouse
VIRTUAL ECONOMYReal and virtual economies have
been connected
It is now
technologically possible,
socially acceptable, and culturally appropriate
to interact with others
within immersive
3D online environments.
And It’s Happening
Now…
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Computing Evolution: A Collision Course
Battle For Control Of The Computing Platform
Fixed Function
Programmable
General Purpose
Multi-threading Multi-core Many Core
Throughput Performance
Programmability
SMTSmall Number
Of Traditional
Cores
Arrays of
Throughput
Cores
DX7
DX9
DX10
Future
CPU
GPU
CPU
• Evolving toward throughput computing
• Motivated by energy-efficient performance
GPU
• Evolving toward general-purpose computing
• Motivated by higher quality graphics and
GP-GPU usages
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Larrabee: Block Diagram
Mem
ory
Contr
oller
Multi-Threaded
Wide SIMD
Multi-Threaded
Wide SIMD
Multi-Threaded
Wide SIMD
Multi-Threaded
Wide SIMD
D$I$D$I$
D$I$
Mem
ory
Contr
oller
Mem
ory
Contr
oller
D$I$
Multi-Threaded
Wide SIMD
D$I$
Multi-Threaded
Wide SIMD
D$I$
Multi-Threaded
Wide SIMD
D$I$
Multi-Threaded
Wide SIMD
L2 Cache
. . .
. . .
Fix
ed
Function
Textu
re
Logic
Syste
m
Inte
rface
Dis
pla
y
Inte
rface
Mem
ory
Contr
oller
•Multiple IA cores
–In-order, short pipeline
–Multi-thread support
•1024-bit ring bus
•Dedicated texture logic
•Supports virtual memory
•16-wide vector units
–Extended x86 ISA
•Fully coherent caches
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Larrabee: CPU-like Software Stack
Application
Driver
Larrabee Hardware
Tools/LibrariesPerformanceAnalysis Tools
User ProgramsGraphics Apps
Larrabee Native Apps etc.
UtilitiesDriver Control
Panel
DirectX OpenGL
PCIe/Display Driver
Rendering Pipeline
API
Driver Executive (µOS)
DevelopmentEnvironment
CompilerDebugger
Larrabee Native C/C++
Larrabee Native App
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Challenge of Parallel Programming
?
Irregular Patterns and Data Structures
Increasing Cores (2→64+ Cores)
Vector Instructions (4→8+ Wide)
Cache and Interconnect Latency
Scale to Multi-Core Today → Hard
Scale to Many-Core Tomorrow → Harder
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Ct: A Throughput Programming Model
TVEC<F32> a(src1), b(src2);
TVEC<F32> c = a + b;
c.copyOut(dest);
1 1 0 00 1 0 1 0 1 0 00 0 1 1
1 1 0 00 1 0 1 0 1 0 00 0 1 1
+
Thread 4
0 0 1 1
0 0 1 1
+
Thread 3
0 1 0 0
0 1 0 0
+
Thread 2
0 0 0 1
0 0 0 1
+
Thread 1
1 1 0 1
1 1 0 1
+
Ct JIT Compiler:
Auto-vectorization, SSE,
AVX, LarrabeeCore 1
SIMD Unit
Core 2
SIMD Unit
Core 3
SIMD Unit
Core 4
SIMD Unit
Programmer Thinks Serially; Ct Exploits Parallelism
Ct Parallel Runtime: Auto-Scale to Increasing Cores
User Writes
Core Independent C++ Code
Key Data Abstraction is the Nested Vector
Supports Dense, Sparse, and Irregular Data
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Speedup
0
10
20
30
40
50
BlackScholes
BinomialTree
Monte Carlo Convolution CollisionDetection
Ct- 8C
Ct-1C
SSE
Excellent Scale-Up
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Daniel PohlResearch Scientist
Intel Corporation
Daniel Pohl
Intel Corp.http://www.qwrt.de/
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Progress in Ray Tracing
50 Intel® Xeon™Processors
4 Frames per Second640x480
IDF 2004
Yorkfield(45nm Quadcore)
~90 frames per Second
768x768
Games Convention
2007 Dual-X5365
(total: 8 cores)
~90 frames per Second
1280x720
Fall IDF 2007
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Ron Fedkiw
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
What does the future look like?
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Visual Computing:Acquiring, Analyzing, Modeling and Synthesizing Visual Environments
Immersive
User Interface
Photorealistic
3D Rendering
3D
Audio and Video
Multi-Modal
Computing
With a Programmable, Ubiquitous, and Unified Architecture
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
High Performance Computing
22
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
23
The shift to massive computing parallelism in commodity devices
• For decades Moore‘s law has defined the increase of Hardware component complexity as well as performance. Now with Multi-Core and Manycore technology, Moore‗s Law has been transported into the Software world, with massive implications.
• Current typical programming skills are not enough to take advantage of the resulting performance boosts now available to everyone.
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
The good news: Moore‘s Law isn‘t over yet
65nm process
2005
30nm 20nm
45nm process(20 nm prototype)
2007
32nm process(15 nm prototype)
2009
15nm
22nm process(10 nm prototype)
2011
Source: Intel
Technology Node (nm) 90 65 45 32 22
Integration Capacity (BT) 2 4 8 16 32
… combined with advanced packaging, we get the
familiar transistor-doubling with each generation
These are projections only and may not be reflected in future products from Intel Corp.
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
25
The bad news: Single thread performance is falling off (ILP at point of diminishing returns?)Historic SPECint 2000 Performance
Source: published SPECInt data
The free lunch is over…Herb Sutter, MS
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Next step, Manycore: a fundamental design change - converging from many directions
general-purpose GPU• Tesla (NVidia)• Cell (IBM/Sony/Toshiba)• Firestream (AMD)
general-purpose manycore• Tilera (MIT)• RAMP (Berkeley),• Terascale R&D (Intel)• Larrabee (Intel, 2009)
heterogeneous manycore• Fusion (AMD, announced)
multicore evolving to manycore• Sun UltraSPARC T2: 8 cores x 8 threads = 64• IBM z10: 20 CPU cores (+ 2 service cores) • Intel Nehalem: 8 cores X 2 threads = 16 (2008)
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Software challenge for manycore:traditional CS programs hard to change
Curriculum• what material gets dropped?• new course or change to existing one?
Material hard to find• textbook? (parallelism dropped from CLSR 2nd ed!)• lecture material, demos, labs?
What is the right model/approach/language to teach?
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Manycore programming models: active R&D(in contrast to SMP Multicore)
Conceptual Models• “View from Berkeley”: 13 dwarfs• design patterns; RMS (Intel)• Alternatives to threads• everything old is new again?
• Linda, MPI, functional lang, skeletons(templates, frameworks (cactus)), actors…
Extensions to current languages• X10 (IBM/DARPA)• Ct (Intel CTG)• OpenMP, TBB: continue to scale?
Explicitly parallel programming languages:• Erlang (Ericsson)• TStreams (Intel/MIT)• Cilk, Haskell, Charm++, Titanium, etc, etc
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
ABCPL
ACE
ACT++
Active messages
Adl
Adsmith
ADDAP
AFAPI
ALWAN
AM
AMDC
AppLeS
Amoeba
ARTS
Athapascan-0b
Aurora
Automap
bb_threads
Blaze
BSP
BlockComm
C*.
"C* in C
C**
CarlOS
Cashmere
C4
CC++
Chu
Charlotte
Charm
Charm++
Cid
Cilk
CM-Fortran
Converse
Code
COOL
CORRELATE
CPS
CRL
CSP
Cthreads
CUMULVS
DAGGER
DAPPLE
Data Parallel C
DC++
DCE++
DDD
DICE.
DIPC
DOLIB
DOME
DOSMOS.
DRL
DSM-Threads
Ease .
ECO
Eiffel
Eilean
Emerald
EPL
Excalibur
Express
Falcon
Filaments
FM
FLASH
The FORCE
Fork
Fortran-M
FX
GA
GAMMA
Glenda
GLU
GUARD
HAsL.
Haskell
HPC++
JAVAR.
HORUS
HPC
IMPACT
ISIS.
JAVAR
JADE
Java RMI
javaPG
JavaSpace
JIDL
Joyce
Khoros
Karma
KOAN/Fortran-S
LAM
Lilac
Linda
JADA
WWWinda
ISETL-Linda
ParLin
Eilean
P4-Linda
Glenda
POSYBL
Objective-Linda
LiPS
Locust
Lparx
Lucid
Maisie
Manifold
Mentat
Legion
Meta Chaos
Midway
Millipede
CparPar
Mirage
MpC
MOSIX
Modula-P
Modula-2*
Multipol
MPI
MPC++
Munin
Nano-Threads
NESL
NetClasses++
Nexus
Nimrod
NOW
Objective Linda
Occam
Omega
OpenMP
Orca
OOF90
P++
P3L
p4-Linda
Pablo
PADE
PADRE
Panda
Papers
AFAPI.
Para++
Paradigm
Parafrase2
Paralation
Parallel-C++
Parallaxis
ParC
ParLib++
ParLin
Parmacs
Parti
pC
pC++
PCN
PCP:
PH
PEACE
PCU
PET
PETSc
PENNY
Phosphorus
POET.
Polaris
POOMA
POOL-T
PRESTO
P-RIO
Prospero
Proteus
QPC++
PVM
PSI
PSDM
Quake
Quark
Quick Threads
Sage++
SCANDAL
SAM
pC++
SCHEDULE
SciTL
POET
SDDA.
SHMEM
SIMPLE
Sina
SISAL.
distributed smalltalk
SMI.
SONiC
Split-C.
SR
Sthreads
Strand.
SUIF.
Synergy
Telegrphos
SuperPascal
TCGMSG.
Threads.h++.
TreadMarks
TRAPPER
uC++
UNITY
UC
V
ViC*
Visifold V-NUS
VPE
Win32 threads
WinPar
WWWinda
XENOOPS
XPC
Zounds
ZPL
Third party names are the property of their owners.
Implementations: Explicitly parallel languagesBe careful what you wish for….
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Third party names are the property of their owners.
Software challenge for manycore:What is Intel doing about this?
Research fundingUPCRC at Berkeley & Illinois (jointly with MS)PPL at Stanford (with several others)
ToolsIntel Thread Checker, Thread ProfilerThread Building Blocks (open source)
University ProgramMulti-core content and trainingCurriculum development grants
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
UPCRC: A Research Partnership
AcademiaH/W & S/W
Companies
Leadership$$Guidance
Innovation
Trained ResearchersGovernment
State Govs
Matching
Funds
Objective: Breakthroughs in Parallel Programming
Intel + Microsoft
$20 Million over 5 years
Matching University Investments
University of Illinois: $8 mil match
UC Berkeley: $7 mil match
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Cloud Computing
Cloud Computing Testbed – Announced July 29, 2008
• ~5 site distributed testbed, each >1000-4000 cores, open to academic research community, dedicated to supporting the development of an open source stack
• Create a technology stack and research community to create the next 100 Google’s and Amazon’s
Reuters, Forbes, Financial times, BusinessWeek online, BBC, New York Times, Dow Jones Newswires, TechCrunch, CNET, EE Times, InformationWeek, ComputerWorld, Times UK, San Jose Mercury News, Bloomberg, … July 2008
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Making Parallel Computing Pervasive
EnablingParallelComputing
Academic Research
UPCRCs
Software
Products
Multi-core
Education
TBB Open Sourced
STM-Enabled Compiler on Whatif.intel.com
Parallel Benchmarks at Princeton‘s PARSEC site
Joint HW/SW R&D program to
enable Intel products 3-7+ in future
Intel Tera-scale
Research
Academic research seeking disruptiveinnovations 7-10+years out
Community and
Experimental Tools
Wide array of leadingmulti-core SW
development tools & info available today
Multi-core Education Program
- 400+ Universities - 25,000+ students - 2008 Goal: Double this
Intel® Academic Community
Threading for Multi-core SW community
Multi-core books
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Intel Academic Community –Academic Community Collaborating Worldwide
In 72 countries around the world ,
at more than 959 Universities1626 professors areteaching 69700+ new software professionalsMulti-core programming
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
35
What we are doing to helpHelp mainstream programmers to quickly develop quality code
ResearchTomorrow’sTechniques
TransactionalMemory
Main threadMain thread Speculative Speculative
threadthread
SpawnSpawn
CommitCommit
speculative speculative
resultsresults
CC
BBAA
Main threadMain thread Speculative Speculative
threadthread
SpawnSpawn
CommitCommit
speculative speculative
resultsresults
CCCC
BBBBAAAA
SpeculativeMulti-threading
EducateTomorrow’sExperts
• 2006 - Helped 45 universities addparallel programming courses
• 2007 400+ univ. 25000 students• 2008 reaching out to 1000+ univ
Intel Academic Community
ACCELERATE TRANSITIONTO PARALLEL PROGRAMMING
ProvideToolsToday
Architect, Thread, Debug & Tune
http://www.intel.com/software/products
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Intel® Academic CommunityGet Involved!
Connect with peers & technologists
Access new technology curriculum
Lead global discussion forums
Share your knowledge!– Join the discussions in the
forums– Give your opinions in the blogs– Add your content to the Wiki– Comment on what you are
viewing
http://academiccommunity.intel.com
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Third party names are the property of their owners.
Intel University Program
• Courseware to drop into existing courses
• Continual technology updates
• Free Intel® Software Development Tools licenses for the classroom
• Wiki and blog for collaboration
• Forums for specific questions
academiccommunity.intel.com
Green (by) IT
ENERGY EFFICIENT IT STARTS WITH THE MICROPROCESSOR
BUT DOESN´T END THERE
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Intel‘s Long History of Environmental Focus
Intel’s Climate Awareness Timeline
Ahead of the Curve
Transparency and Disclosure Driving Company-wideContinuous Improvement
Public Environmental
Reporting
Public Reporting of Total Energy Use
First GlobalSector-wide
Climate Change Goal
Public Reporting of Climate Footprint
Global Energy Conservation
Goal
First ICT Company to join EU
Commission’s Sustainable
Energy Campaign
LargestPurchaserof Green
Power in US
19941996
1998
2000
2003
2006
2008
―Green‖ Fab 32 Comes Online
Led industry
agreement on PFC
reduction: world‘s 1st voluntary
GHG reduction
agreement
2007
Join US EPA Climate Leaders: Global
Climate Footprint Goal
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Intel‘s 2007 Carbon Dioxide Footprint for Operations
Total Carbon Dioxide Emissions3 million metric tons
24% PFCs
5% Other Chemicals
71% Mfg Energy
Source: Internal data, combined with World Resources Institute protocol for converting to CO2 impact.
Other chemicals includes N2O, fluorinerts, refrigerants, and CO2 generated from VOCs.
Note: Supply Chain not included.
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Energy
Water
Chemicals
Chemical Waste Solid Waste
Wastewater
Global Warming GasesAir Pollution
Logistics &
Transport
Reducing Environmental Impact of Operations
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Water
Chemicals
Chemical Waste Solid Waste
Wastewater
Global Warming GasesAir Pollution
Logistics &
Transport
Intel’s Ocotillo Campus wins EPA Water Efficiency Leader Award
WaterIntel’s newest 45nm processors to go lead free and halogen free
Intel, regulators and neighbors join together to reduce waste and increase recycling
Solid waste and consumer recycling initiatives reduce E-waste
Packaging reductions of 16-40% decreased number of shipments and fuel consumed
Intel wins the California Clean Air Award for outstanding leadership
Intel pledges to reduce global GHG emissions by 30% per production unit
Reducing Environmental Impact of Operations
Intel Ireland certified to IS393 Energy Management Systems Standard
Intel pursues LEED certification
for fabrication plants and buildings
Over 3 million gallons of water is reclaimed each year using special collection systems
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Our Current Challenge: Reducing Absolute Energy Use
Projected Energy Use with 5% Normalized Reduction
20
07
20
08
20
09
20
10
20
11
20
12
20
13
20
14
20
15
20
16
20
17
20
18
20
19
20
20
Abs Energy Norm Energy
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Source: Internal data, combined with World Resources Institute protocol for converting to CO2 impact.
Other chemicals includes N2O, fluorinerts, refrigerants, and CO2 generated from VOCs.
Note: Supply Chain not included.
Total Intel Carbon Dioxide Footprint for Operations Plus Products 2007 (based on impact of products shipped each year)
Carbon Dioxide Emissions (37.5 million metric tons)
Commute
Logistics
Operations 3.0
Products 33.8 million metric tons
Intel’s Biggest Impact Area for the
Environment
0.5
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
90nm300mm
130nm200mm
180nm200mm
250nm200mm
65nm300mm
Dual Core
45nm300mm
Reduction In Transistor Switching Power ~30%
Improvement In Transistor Density ~2x
Improvement In Transistor Switching Speed>20%
Relentless Pursuit of Moore‘s Law Opens the Door to Innovation
Industry‘s 1st 45nm High-K Process Technology
Source: Intel
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Performance Over Time*Power Reduction Over Time*
~ 1 million fold reduction in energy/transistor over 30+ years
Energy Efficiency Positive Impact On Environment
Pentium® Pro Processor
Pentium® -II Processor
Pentium® -IIiProcessor
Pentium® 4 Processor
Pentium® 4 Processor EE
Pentium® -D Processor
Core™ 2 Duo Processor X6800
Core™ 2 Duo Extreme QX6700
i486DX2
i486
386
Pentium® Processor
1986 200819881990199219941996199820002002200420061
10
100
1000
10000
Single Core Moore’s Law
Improving Energy Efficiency of Products
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Improve computing energy efficiency by 50%
• Collectively save $5.5 billion in energy costs
Reduce global CO2 emissions by 54 million tons per year
• That is the equivalent of…
The Climate Savers Computing Initiative
planting 25,000m2
(~65,000km2) of treeselimination of 20
coal plants from the planet
removal of 11 million automobiles
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Climate Savers Computing Initiative Members
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Total Intel Carbon Dioxide Footprintas a Portion of Global Emissions
3%
97%
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Source: “A Smarter Shade of Green,” ACEEE Report for the Technology CEO Council, 2008.
Automobiles
Passenger
Airlines
Agriculture
Steel
Manufacturing
Lighting
Computer
Systems
40%
121%
132%
167%
339%
2,857,000%
1978 2008Energy-efficiency
Improvement
14.3 miles per gallon of
gas
20.0 miles per gallon of
gas
22.8 revenuepassenger
milesper gallon
50.4 revenuepassenger
milesper gallon
0.63 units ofoutput per unit
of energy use
63 pounds of steel per MBtu
Incandescent light bulb— 13
lumens per watt
1,400 instructions
per second per watt
40,000,000Instructions per second per watt
Greater Role of ICT in Enabling Energy Efficiency
1.46 units ofoutput per unit
of energy use
167 pounds of steel per MBtu
Compact flourescent
bulb—57 lumens per
watt
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
3%
97%
© Prof. Dr. Mark HarrisAssociated Professor for Technology Entrepreneurship & Innovation
Intel® Director Higher Education & ResearchEurope, Middle East, Africa
Questions ?
52