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IMPACT • DMI• 1
Energy-Efficient Digital PLL Design: A Case Study in Analog/Mixed-Signal Variability
Elad AlonDept. of EECS
UC Berkeley
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IMPACT • DMI• 2
Phase-Locked Loops
Modern processor runs at 2-3 GHz– Crystals go up to
only ~100MHz
÷N
[Image: Kevin Zhang]
Phase-locked loop (PLL) generates high frequency clock from reference
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IMPACT • DMI• 3
PLL Challenges
Increasing number of PLLs
on a single die
– Need compact, low-power designs
Extremely noisy environment– Robust to supply variations
Critical to chip functionality– Robust to process/device variations
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IMPACT • DMI• 4
Outline
Review of PLL Design
Proposed Architecture and Results
Variability Implications
Conclusions
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IMPACT • DMI• 5
Linearized
Model
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PLLs
are intrinsically
2nd
order or higher feedback loops
– Stability is one of the primary concerns
Variations can destabilize the loop– E.g., what if R drops
by 50%?
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IMPACT • DMI• 6
Icp
Vreg
up
downR
C+
-
clk
÷N
PFDref_clk
Self-Biased PLL
“Self-biasing”: Apply
ratio-metric design to PLL to ensure stability
Key design changes: – Charge pump current and filter
R derived from VCO bias current
Ideally maintains constant loop dynamics– Allows aggressive loop bandwidth for low jitter
constant2
ref
vcocp
ref
n
CNKI
constant
21 2
N
CRKI vcocp
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IMPACT • DMI• 7
Supply Regulated PLLs
7
Loop can’t respond to noise outside its bandwidth– Use regulator to filter supply noise– But regulator adds extra poles into the loop – impacts stability
Regulator rejection limited by loop stability– How to improve supply rejection?
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IMPACT • DMI• 8
Remove Regulator From the Loop
8
Eliminates stability/rejection tradeoff
But, still need to control the oscillator– Analog methods exist– But are difficult to robustly self-bias across process variations– And they tend to be non-linear
cp reg+
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÷N
ref
c
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IMPACT • DMI• 9
Digital PLL
Instead of relying on analog ratios/macthing– Measure the underlying parameters and adjust control
accordingly
Much easier to do with a digital control loop…
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ref_clk
+-
Vref
Cdecap
LPF
ΣDCO
TDCN
fprop
fint
Vreg
Clk
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IMPACT • DMI• 10
Outline
Review of PLL Design
Proposed Architecture and Results
Variability Implications
Conclusions
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IMPACT • DMI• 11
Digital PLL Basics
PFD replaced by a time-to-digital converter
(TDC)
Loop filter and charge pump replaced by digital
logic
VCO replaced by digitally-
controlled oscillator (DCO)
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ref_clk
+-
Vref
Cdecap
LPF
ΣDCO
TDCN
fprop
fint
Vreg
Clk
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IMPACT • DMI• 12
Digital PLL Calibration
Digital arch. well-
suited to calibration– DCO easily measured
by forcing control input– Adjustments easily
made by digital logic after LF
– Logic complexity set by range/type of variations
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IMPACT • DMI• 13
Key Design Challenge
TDC introduces quantization noise, limit cycles– Recent designs focus on implementing a high resolution TDC– Multi-bit TDCs still very power-hungry, sensitive to variations
Is a high resolution TDC necessary?
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Thermometer Decoder
Stop
Start …
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ref_clk
+-
Vref
Cdecap
LPF
ΣDCO
TDCN
fprop
fint
Vreg
Clk
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IMPACT • DMI• 14
One-Bit TDC?
Can we get away with just a single bit TDC –
i.e., a
bang-bang phase detector (BBPD)?
BBPD linearized
gain is a function of error signal
– Compare loop performance by matching BBPD loop gain to linear loop gain with same dynamics
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I/s
VnP
Kdco/sΦin
-Φout
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I/s
VnP
Kdco/sΦin-
Φout1/Gainbb
2
err
outBB
DGain
Φin
-Φerr
Φdiv
Dout
-Dout
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IMPACT • DMI• 15
Jitter Comparison
PLL with bang-bang detector can achieve nearly the same jitter as linear loop
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IMPACT • DMI• 16
Downside of Bang-Bang Detector
BBPFD gain drops for large error signals– Loop can’t respond quickly
to large steps
Problematic with noisy power supplies– Get large supply steps
when e.g. blocks turn on and off
Need to re-introduce a linear control method…
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IMPACT • DMI• 17
Traditional PFD Operation
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÷NPFD PFD in Charge-Pump PLL
PFD generates fixed-amplitude voltage pulses– Phase information encoded in pulse widths
Voltage Current Voltage Frequency– What if we skip the intermediate conversions?
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IMPACT • DMI• 18
Proposed Linear Phase Control
PFD outputs directly modulate delay of each element inside of the DCO
Change in delay (tout
) proportional to PFD pulse- width difference (tin
)
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IMPACT • DMI• 19
Architecture Summary and Final Design
Linear phase control path stabilizes the loop, handles large transients
Retain simplicity of BBPD for integral path
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Vreg
÷N
-
+
BBPD
R-StringDAC
FrefPFD
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IMPACT • DMI• 20 20Test Board
1060 um
460 um
Package
Test-Chip and Setup
Die Photo
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IMPACT • DMI• 21
Measured Jitter Performance
21
Period Jitter: 1.13psrms
, 19.3pspp
Absolute Jitter: 2.13psrms
, 21.9pspp
With 97mVpp supply noise: ~12pspp
additional jitter
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IMPACT • DMI• 22
ComparisonThis Work [Tierno
JSSC ‘08]1 [Grollistch
ISSCC ‘10]
2
Technology 65 nm 65 nm SOI 65 nm
Area (mm2) 0.026 0.030 .038
Output Freq. (GHz) 3 4 3
Ref. Freq. (MHz) 300 500 25
Power (mW/GHz) 0.66 5.8 3.86
Period Jitter [rms, pp] (ps) 1.13, 19.3 0.7, - 1.45, 15
Absolute Jitter [rms, pp] (ps) 2.13, 21.9 6, - -, -
22
3GHz output clock in
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IMPACT • DMI• 23
Outline
Review of PLL Design
Proposed Architecture and Results
Variability Implications
Conclusions
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IMPACT • DMI• 24
Handling Variability
Although the loop is “digital”– Still have many potential opportunities for variation to impact
performance– Still need low-power means to handle these variations
Look at a couple of examples
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Vreg
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-
+
BBPD
R-StringDAC
FrefPFD
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IMPACT • DMI• 25
Mismatch Between Paths
Physical separate proportional and integral paths– This mismatch directly
translates into jitter– Paths fight each other
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IMPACT • DMI• 26
Offset Correction
Offset correction is relatively cheap – As long as don’t need to cover
too much range26
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IMPACT • DMI• 27
Tuning Range
Global variations can have even more impact– With fixed Vref (Vreg ), nominal DCO frequency can vary by
over 2-3x across process and temperature
Difficult to cover wide frequency range in DCO– Large number of bits large Cp high power
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÷N
-
+
BBPD
Fref
Vref
PFD
Vreg2N-1
CL CSW CSWCp Cp
FDCO1 FDCO2
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IMPACT • DMI• 28
Secondary Integration Path
Adjust Vref
to cover entire range of variation– Adjustments can be very slow
Coarse loop covers most of the range– Fine (fast) loop only needs a
small low-power capacitor DAC28
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IMPACT • DMI• 29
Outline
Review of PLL Design
Proposed Architecture and Results
Variability Implications
Conclusions
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IMPACT • DMI• 30
Conclusions
PLL a good driver for studying analog/mixed-signal variability– Critical to chip functionality– Operate in harsh environments– Many of them integrated onto the die
Can implement low-power digital PLLs
for improved robustness– Linear phase control path + bang-bang integral path can achieve same
jitter as an analog loop– 3GHz, 1.1psrms jitter in 2mW
Good design critical to tolerating variability– Want to codify the best practices & tradeoffs – working on a PLL
“generator”…
Slide Number 1Phase-Locked LoopsPLL ChallengesOutlineLinearized ModelSelf-Biased PLLSupply Regulated PLLsRemove Regulator From the LoopDigital PLLOutlineDigital PLL BasicsDigital PLL CalibrationKey Design Challenge One-Bit TDC?Jitter ComparisonDownside of Bang-Bang DetectorTraditional PFD OperationProposed Linear Phase ControlArchitecture Summary and Final DesignSlide Number 20Measured Jitter PerformanceComparisonOutlineHandling VariabilityMismatch Between PathsOffset CorrectionTuning RangeSecondary Integration PathOutlineConclusions