Download - How P1687 Enables FPGA-Controlled Test
© 2011, ASSET InterTech, Inc. ASSET Confidential
1 BTW October 2011
How P1687 Enables FPGA-Controlled Test
FCT Tester Architecture
Alfred L. Crouch Chief Technologist & Director of IJTAG R&D Core Instruments Officer in P1687, P1838, and iNEMI BIST Project Author of Several DFT Books and Patents
Scott A. Hack Product Manager, IJTAG and FCT Tools
© 2011, ASSET InterTech, Inc. ASSET Confidential
2 BTW October 2011
Goals of this Presentation
! Concept of FCT ! What needs to be done to perform FCT? ! Understanding board DFT for PCT (PCOLA…) ! Picking IP Functions and mapping to FPGA ! Re-usability of P1687 PDL ! Introductory example (memBIST for DDR) ! What does a board test engineer need for FCT? ! What makes a tester? ! Using an IJTAG tool as tester Operating System
© 2011, ASSET InterTech, Inc. ASSET Confidential
3 BTW October 2011
What is FPGA-Controlled Test?
For Test – anything can be programmed to help meet the test goals – then discarded….
Proc
BIST
REG
This ties Processor-Controlled Test, High-Speed IO BIST, Boundary Scan Test, and IJTAG together into one application…
Use the FPGA as an Embedded Tester… …Program it to be a Tester…
© 2011, ASSET InterTech, Inc. ASSET Confidential
4 BTW October 2011
What is FPGA-Controlled Test? The Recipe
Board Peripheral
(BP)
1. Identify Board Peripheral that is connected to an
on-board FPGA
Chip TAP
2. Identify the FPGA and its Sizing and
Performance
FPGA
Target IP 4. KEY: Identify IP that would meet Goals
3b. Identify Test Procedures, Models,
or Vectors
Functional Test – Verifies Design Structural Test – Verifies Manufacturing Performance Test – Verifies Specs
3a. Identify the Type of Test(s) to be applied to Peripheral
7. Identify the Test Automation Process/Software
Core TAP
T D R
6. Identify FPGA Programming or Architecture Issues/Problems
5. Identify Signals-to/from-Peripheral
PCOLA/SOQ/FAM
© 2011, ASSET InterTech, Inc. ASSET Confidential
5 BTW October 2011
What are we Testing? Not the Chip Guts…
! There are Chip (IC) Tests ! Fault Coverage (e.g. Stuck-At, Path Delay, Transition
Delay, n-Detect) ! Defect Coverage (shorts, opens, bridges, GOS) ! Parametrics (Max FRQ, Leakage – iDDQ, IOH,IIL, VOH,
VIL) ! Functional (Read, Write, Bus Transactions, etc.) ! Embedded BIST (Logic, Memory, HSIO)
! There are Board Tests ! PCOLA ! SOQ ! FAMI
Not about FPGA Test or Chip Test… but we can use the Embedded Units to Help with Board Test,
Board Characterization, and Board Debug-Diagnosis
© 2011, ASSET InterTech, Inc. ASSET Confidential
6 BTW October 2011
PCOLA/SOQ/FAM/I
Structural Devices
Structural Connections
Functional Connections
P
C
O
L
A
S
O
Q
F
A
M
Presence
Correctness
Orientation
Live
Alignment
Shorts
Opens
Quality
Features
At-Speed
Measurement
Boundary Scan Tests and External Equipment (ICT, X-Ray) and Visual Inspection
Boundary Scan Interconnect Test and X-Ray
Functional Tests
PCOLA tests are tests that verify the Presence of a chip in a socket or at a board location; that it is the Correct chip; and is Oriented correctly; receives power and is Live; and is Aligned correctly
SOQ tests are tests that verify the connections/signals to the chip to be free of Shorts and Opens; and can assess the Quality of the connection’s solder joints
FAM tests are tests that can operate or verify a Feature of the chip; can be applied At-speed; and that allow a Measurement to be taken
Optimizations I Independent I tests are tests that can be operated Independently so they can be scheduled in parallel to reduce test time
Simultaneous and Concurrent Tests
© 2011, ASSET InterTech, Inc. ASSET Confidential
7 BTW October 2011
ASIC or
SoC
Large FPGA with FCT
Board Tester
Medium FPGA Flash
Memory DDRx
Memory D2A
Convertor A2D
Convertor
General Purpose Bus
DDRx Memory Bus
High-Speed IO Bus
FCT Embedded Tester Coverage Concept
FCT Tester Coverage: GPB coverage
HSIO coverage
DDRx coverage
SOQ FAM
© 2011, ASSET InterTech, Inc. ASSET Confidential
8 BTW October 2011
ASIC or
SoC
Large FPGA with FCT
Board Tester
Medium FPGA Flash
Memory DDRx
Memory D2A
Convertor A2D
Convertor
General Purpose Bus
DDRx Memory Bus
High-Speed IO Bus
FCT Embedded Tester Coverage Concept
FCT Tester Coverage: GPB coverage
HSIO coverage
DDRx coverage
DDR MBIST
TAP
TDR
1. Identify Peripheral Chip 2. Identify connections to
FPGA 3. Identify Test Goal 4. Relate Test Functions
to PCOLA/SOQ/FAM 5. Identify Test Tradeoffs
a. Cost of Applied Test b. Applied Test Time c. Test Develop Cost d. Test Develop Effort
6. Select IP that meets Goals
P C O L A S O Q F A M
DDR Loopback
ADDR First-Last Read Data Width Boundary Scan
At Speed Memory Operation
© 2011, ASSET InterTech, Inc. ASSET Confidential
9 BTW October 2011
ASIC or
SoC
Large FPGA with FCT
Board Tester
Medium FPGA Flash
Memory DDRx
Memory D2A
Convertor A2D
Convertor
General Purpose Bus
DDRx Memory Bus
High-Speed IO Bus
Use Methodology – FCT Embedded Tester
1. Identify board with FPGA as an opportunity for Embedded ATE
3. Identify needed instruments to meet Test Goals and usage environment (MFG Test, Debug, NPI Test Development, etc.)
DDR MBIST
SerDes BIST
SPI I/F Xlator
Processor w/PCT support
2. Identify Test Goals of Peripheral (PCOLA, SOQ, FAM)
Common List of Instruments
1. Pattern Generator 2. Capture Buffer 3. Memory BIST/Test 4. SerDes BERT 5. HSIO Protocols (e.g. PCIe,
XAUI, DDRx) 6. SPI/I2C Interfaces 7. D2A Waveform Gen 8. A2D/DSP Sampler 9. Clock Counters 10. Flash Programmer
© 2011, ASSET InterTech, Inc. ASSET Confidential
10 BTW October 2011
ASIC or
SoC
Large FPGA with FCT
Board Tester
Medium FPGA Flash
Memory DDRx
Memory D2A
Convertor A2D
Convertor
General Purpose Bus
DDRx Memory Bus
High-Speed IO Bus
Use Methodology – FCT Embedded Tester
1. Identify board with FPGA as an opportunity for Embedded ATE
3. Identify needed instruments to meet Test Goals and usage environment (MFG Test, Debug, NPI Test Development, etc.)
2. Identify Test Goals of Peripheral (PCOLA, SOQ, FAM)
4. Apply the Embedded Tester Generator: to Create instruments plus IJTAG Network Bit File The tester may support many “Instruments” simultaneously
5. Apply the appropriate tools: Boundary Scan for Interconnect, IJTAG for Instruments, Emulation for Processor
DDR MBIST
SerDes BIST
SPI I/F Xlator
Processor w/PCT support
© 2011, ASSET InterTech, Inc. ASSET Confidential
11 BTW October 2011
SiB
T D R
RW
M B I S T
Done Fail Reset Run
T D R
RW
M B I S T
Done Fail Reset Run
SiB
SiB
• The Controller • 1149.1 TAP & TAP Controller • BSDL
• The Instrument • IP, Design-ware, EDA Gen • Portable/Reusable • Raw Instrument ICL, PDL
• The P1687 Scan-Path Network • Design-ware, EDA Generated • Compliant to P1687 Rules • P1687 Network ICL
PDL Vectors go here
TCK
TMS
TDI
TDO
TAP Controller
PDL Vectors go here IR=10111
Not P1687 is 1149.1
Not P1687 is user IP
Yes, P1687
Access Link
Instrument Interface
ICL Description
PDL Description
What is IEEE P1687? – an Instrument Access Standard
An Architecture [Normative Rules]
Architecture Description (ICL)
Instrument Procedures (PDL)
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12 BTW October 2011
Instrument Access Network
SiB TCK
TMS
TDI
TDO
TAP Controller
Signal Legend Blue = Data Red = Status Green = ScanPath
FPGA
Multiple Instruments can be accessed Simultaneously
Scan Path/Access-Time is fully adjustable by opening and Closing SIBs
Instruments can be started and operated and their SIB access closed down to minimize the scan path length but must be revisited later to collect results
Addr[24]
Data[32]
R/W~
Comp[32]
Data[32]
IP Unit2
SiB
T D R
B1
PattGen Done
Reset Start
PDL Vectors Here
Comp[32]
IP Unit3
T D R
B2
CaptBuff Cycle_# Full Reset Start
SiB
PDL Vectors Here
IP Unit1
T D R
A1
MBIST Done Fail Reset Start
SiB
PDL Vectors Here
Selection of IP Units
Stitching of Access Scan
Path
© 2011, ASSET InterTech, Inc. ASSET Confidential
13 BTW October 2011
How Does P1687 Fit in the FCT Process?
Board Peripheral
(BP)
Simple IP
Core TAP
Chip TAP
T D R
Proc Pins/Signals-to/from-Instrument
Simple IP is Mapped to
FPGA specific pins
P1687 PDL is Reusable and
can be viewed as an
Instrument API
Vectors retargeted
here using FCT
FPGA
Functional Test – Verifies Design
Performance Test – Verifies Specs
KEY: Choose a Processor that supports PCT
Structural Test – Verifies Manufacturing
© 2011, ASSET InterTech, Inc. ASSET Confidential
14 BTW October 2011
What is FPGA-Controlled Test? Custom IP
Board Peripheral
(BP) Custom Test Unit (e.g. BIST or BERT)
Chip TAP
T D R
FPGA Signals-to/from-Peripheral
Complex IP is Test Unit
Compound Complex Instrument
Original Vectors Here: Design of IP Incorporates
Vectors Instrument
Vectors (PDL) Vectors (PDL)
retargeted here using IJTAG-DL
FPGA
Structural Test – Verifies Manufacturing Performance Test – Verifies Specs
KEY: Have a library of Instrument IP for high demand functions
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15 BTW October 2011
IJTAG Tool Retargets PDL using BSDL/ICL
Instrument in FPGA
PDL Operations Scheduled as Test Program
PDL Vectors Here
ICL describes the connections from the TAP to the TDR
© 2011, ASSET InterTech, Inc. ASSET Confidential
16 BTW October 2011
A Specific Example
! An example of an FPGA-based embedded Memory Tester for on-board DDR2/3 memory
! The described tester provides SO/FAM tests for the DDR2/3 Memory and the Memory Interconnect
© 2011, ASSET InterTech, Inc. ASSET Confidential
17 BTW October 2011
The Memory System Architecture
Chip Signals
TCK TMS
TDI TDO
TAP Controller
• The Controller • 1149.1 TAP • TAP Controller • BSDL
• Instrument • IP/Design-ware • EDA Gen
• Scan-Path Network • Design-ware • EDA Generated
BSR
BYP
ID Code
IR
MEMORY
Data_In Address_In Read_Writeb Data_Out
• Test/Debug Target • IP/Design-ware/Chip • EDA Gen/Purchased
T D R
RW
M B I S T
Done Fail Reset Run Algo-Select Data-Select Read-Delay
PDL Vectors Here
ReTargeting Here
FPGA
PIN
BOUNDARY
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18 BTW October 2011
Close-Up of a Cadillac IC BIST for Memory
T D R
R E G
R E G
R E G
R E G
To_D_in
From_D_out
To_FAIL
R E G
T D R
T D R
TDI
TDO
C T R
To_ADDR
To_R_Wbar
Select Algorithm
Select Read Delay
Set Data
TDR
RST_OFF BIST_ON
Cost (32-bit) is about 170 System Flops and 42 JTAG Flops
DONE
Write (Data)
Read (Data)
Write (Comp)
Read (Comp)
Incr (Addr)
Decr (Addr)
Reset
Done
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19 BTW October 2011
Board Memory Test Algorithm Needed
Debug Algorithm Loop on Reset (BIST Off) Reset Off (BIST On) [1N] Write Background Data: Increment Address 00K [3N] Read<Data>; Write<Complement>; Read<Complement>; Decrement<Address>; [3N] Read<Complement>; Write<Data>; Read<Data>; Increment<Address>; [3N] Read<Data>; Write<Complement>; Read<Complement>; Increment<Address>; [3N] Read<Complement>; Write<Data>; Read<Data>; Decrement<Address>; [1N] Read<Data>; Increment<Address>;
Reduced Address Uniqueness Loop on Reset (BIST Off) Reset Off (BIST On) [1N] Write Data <5> to one Address <5> [1N] Write Data <5> to one Address <A> [1N] Read Data <5> from Address <5>; [1N] Read Data <5> from Address <A>; [1N] Write Data <A> to one Address <5> [1N] Write Data <A> to one Address <A> [1N] Read Data <A> from Address <5>; [1N] Read Data <A> from Address <A>;
Write (Data=
Address)
Read (Data=
Address)
Incr (Addr)
Decr (Addr)
Reset
Write (Data)
Read (Data)
Write (Comp)
Read (Comp)
Incr (Addr)
Decr (Addr)
Reset
Done
© 2011, ASSET InterTech, Inc. ASSET Confidential
20 BTW October 2011
The Memory System Architecture
Chip Signals
TCK TMS
TDI TDO
TAP Controller
• The Controller • 1149.1 TAP • TAP Controller • BSDL
• Instrument • IP/Design-ware • EDA Gen
• Scan-Path Network • Design-ware • EDA Generated
BSR
BYP
ID Code
IR
MEMORY
Data_In Address_In Read_Writeb Data_Out
• Test/Debug Target • IP/Design-ware/Chip • EDA Gen/Purchased
T D R
RW
M B I S T
Done Fail Reset Run Algo-Select Data-Select Read-Delay
PDL Vectors Here
ReTargeting Here
This portion is BSDL and all that is described is the instruction and the length of the TDR…
© 2011, ASSET InterTech, Inc. ASSET Confidential
21 BTW October 2011
FPGA BSDL Example
entity XC3S400_PQ208 is!. . .!
attribute INSTRUCTION_LENGTH of XC3S400_PQ208 : entity is 6;!
attribute INSTRUCTION_OPCODE of XC3S400_PQ208 : entity is! "EXTEST (000000)," &! "SAMPLE (000001)," &! "USER1 (000010)," & -- Not available until after configuration! "USER2 (000011)," & -- Not available until after configuration! "CFG_OUT (000100)," & -- Not available during configuration with another mode.! "CFG_IN (000101)," & -- Not available during configuration with another mode.! "INTEST (000111)," &! "USERCODE (001000)," &! "IDCODE (001001)," &! "HIGHZ (001010)," &! "JPROGRAM (001011)," & -- Not available during configuration with another mode.! "JSTART (001100)," & -- Not available during configuration with another mode.! "JSHUTDOWN (001101)," & -- Not available during configuration with another mode.! "BYPASS (111111)," &!
!"ISC_ENABLE (010000)," &!!"ISC_PROGRAM (010001)," &!!"ISC_NOOP (010100)," &!!"ISC_READ (010101)," &!!"ISC_DISABLE (010110)”;!
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22 BTW October 2011
attribute INSTRUCTION_CAPTURE of XC3S400_PQ208 : entity is!-- Bit 5 is 1 when DONE is released (part of startup sequence)!-- Bit 4 is 1 if house-cleaning is complete!-- Bit 3 is ISC_Enabled!-- Bit 2 is ISC_Done! "XXXX01";!
attribute INSTRUCTION_PRIVATE of XC3S400_PQ208 : entity is!-- If the device is configured, and a USER instruction is implemented!-- and not private to the FPGA designer, then it should be removed!-- from INSTRUCTION_PRIVATE, and the target register should be defined!-- in REGISTER_ACCESS.! "USER1," &! "USER2," &! "CFG_OUT," &! "CFG_IN," &! "JPROGRAM," &! "JSTART," &! "JSHUTDOWN," &!
!"ISC_ENABLE," &!!"ISC_PROGRAM," &!!"ISC_NOOP," &!!"ISC_READ," &!!"ISC_DISABLE";!
FPGA BSDL Example
© 2011, ASSET InterTech, Inc. ASSET Confidential
23 BTW October 2011
FPGA BSDL Example
attribute REGISTER_ACCESS of XC3S400_PQ208 : entity is!-- !"<reg_name>[<length>] (USER1)," &!-- !"<reg_name>[<length>] (USER2)," &! "BYPASS (HIGHZ,BYPASS)," &!
!"DEVICE_ID (USERCODE,IDCODE)," &!!"BOUNDARY (SAMPLE,INTEST,EXTEST)";!
. . .!
end XC3S400_PQ208;!
© 2011, ASSET InterTech, Inc. ASSET Confidential
24 BTW October 2011
The Memory System Architecture
Chip Signals
TCK TMS
TDI TDO
TAP Controller
• The Controller • 1149.1 TAP • TAP Controller • BSDL
• Instrument • IP/Design-ware • EDA Gen
• Scan-Path Network • Design-ware • EDA Generated
BSR
BYP
ID Code
IR
MEMORY
Data_In Address_In Read_Writeb Data_Out
• Test/Debug Target • IP/Design-ware/Chip • EDA Gen/Purchased
T D R
RW
M B I S T
Done Fail Reset Run Algo-Select Data-Select Read-Delay
PDL Vectors Here
ReTargeting Here
…P1687 is ICL and PDL to add the description of the Instrument and Instrument Operations
…P1687 does not need to expose the target of the IP – it is assumed that this is understood by the IP designer and is subsumed into the design of the IP.
Note: if the target of the IP is a board peripheral, then the connectivity of the right-side of the IP is provided by the board test professional.
© 2011, ASSET InterTech, Inc. ASSET Confidential
25 BTW October 2011
FCT memory test ICL module (MBIST) {! Ports {! MBIST_CLRFAIL { Function : DataIn; }! MBIST_RESET { Function : DataIn; }! MBIST_RUN { Function : DataIn; }! MBIST_DONE { Function : DataOut; }! MBIST_ERROUT[43:0] { Function : DataOut; }! MBIST_FAIL { Function : DataOut; }! }! PDL "MBIST_Debug.tcl";! PDL "MBIST_Mfg.tcl";!}!
module (MBIST_IEEE1687) {! Ports {! TDI { Function : ScanIn; }! TDO { Function : ScanOut; Source : Read_Data_TDR; }! }! Instances {! MBIST_leaf {! ModuleName : MBIST;! InputSources {! MBIST_RUN : Write_Data_TDR[2];! MBIST_RESET : Write_Data_TDR[1];! MBIST_CLRFAIL : Write_Data_TDR[0];! }! }! }!
© 2011, ASSET InterTech, Inc. ASSET Confidential
26 BTW October 2011
FCT memory test ICL
ShiftRegisters {! Write_Data_TDR[2:0] {! Scanin : tdi;! ResetValue : 1'b0;! }! Read_Data_TDR[45:0] {! Scanin : Write_Data_TDR;! ResetValue : 1'b0;! CaptureSource : (!
! ! ! !MBIST_leaf.MBIST_DONE,!! ! ! !MBIST_leaf.MBIST_FAIL,!! ! ! !MBIST_leaf.MBIST_ERROUT[43:0]!! ! !);!
}! }!}!
© 2011, ASSET InterTech, Inc. ASSET Confidential
27 BTW October 2011
FCT memory test ICL
module (IEEE1687_Network) {! Ports {! TDI { Function : ScanIn; }! TDO { Function : ScanOut; Source : MBIST_Wrapper.TDO; }! }! Instances {! MBIST_Wrapper { ModuleName : MBIST_IEEE1687; InputSources { TDI : TDI; }}! }! SiSoPaths {! P1687_Gateway : TDI, TDO;! }!}!
AccessLink {! Tap_1149_dot_1 USER_1 {! BSDL_Entity : XC3S400_PQ208;! USER1 { ScanPort : IEEE1687_Network.P1687_Gateway; }! }!}!
© 2011, ASSET InterTech, Inc. ASSET Confidential
28 BTW October 2011
FCT memory test PDL proc MBIST_Reset {} {!
!iWrite MBIST_RESET 0b0;!!iApply;!!iWrite MBIST_RESET 0b1;!!iApply;!!iWrite MBIST_RESET 0b0;!!iApply;!
}!
proc MBIST_Start {} {!!iWrite MBIST_RUN 0b1;!!iApply;!
}!proc MBIST_Stop {} {!
!iWrite MBIST_RUN 0b0;!!iApply;!
}!
proc MBIST_Clear_Fail {} {!!iWrite MBIST_CLR_FAIL 0b1;!!iApply;!!iWrite MBIST_CLR_FAIL 0b0;!!iApply;!
}!
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29 BTW October 2011
FCT memory test PDL proc BIST_Done_Monitor { {WATCH_LIMIT 100}} {! set watchdog 0;!
!set done_bit 0;!!set fail_bit 0;!!set err_bus "";!!set log_file "MBIST_Log.txt";!
while {($done_bit == 0) && ($fail_bit == 0) && ($watchdog < $WATCH_LIMIT)} {! set watchdog [ expr { $watchdog + 1 } ];!
! iRead MBIST_DONE;!! !iRead MBIST_FAIL;!! !iRead MBIST_ERROUT;!! iApply;!
! set done_bit [iGetReadValue MBIST_DONE];!! set fail_bit [iGetReadValue MBIST_FAIL];!! set err_bus [iGetReadValue MBIST_ERROUT];!! puts "WATCH MBIST_DONE: $done_bit";!
}!
!if {$fail_bit == 1} {!! !if {[string length $err_bus] == 44} {!! ! !set BSSM [bitslice $err_bus 43:40];!! ! !set BADDR_IN [bitslice $err_bus 39:32];!! ! !set BCOMPARE [bitslice $err_bus 31:16];!! ! !set BDATA_IN [bitslice $err_bus 15:0];!! ! !puts "MBIST STATUS: *FAIL* BSSM($BSSM) BADDR_IN($BADDR_IN) BDATA_IN($BDATA_IN) BCOMPARE($BCOMPARE)";!! ! !Record_Message $log_file "BIST STATUS: *FAIL* BSSM($BSSM) BADDR_IN($BADDR_IN) BDATA_IN($BDATA_IN) BCOMPARE($BCOMPARE)";!! !} else {!! ! !puts "PDL ERROR: ERROUT length expected to be 44 bits long.";!! ! !Record_Message $log_file "PDL ERROR: ERROUT length expected to be 44 bits long.";!! !}!! !return 1;!!} elseif {$done_bit == 1} {!! !puts "MBIST STATUS: Pass";!! !Record_Message $log_file "MBIST STATUS: Pass";!! !return 0;!!} else {!! !puts "MBIST STATUS: *Incomplete* Recommend WATCH_LIMIT greater than $WATCH_LIMIT.";!! !Record_Message $log_file "MBIST STATUS: *Incomplete* Recommend WATCH_LIMIT greater than $WATCH_LIMIT.";!! !return 1;!!}!
}!
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30 BTW October 2011
FCT memory test PDL proc Record_Message { logfile text_message } {! puts "$text_message";!
set fileID [ open $logfile a];! puts $fileID "$text_message";! close $fileID;!}!proc bitslice { msblsb bitrange } {!
!#!!# !Takes in a bitstring with MSB on the left and LSB on the right and returns the
specified sub-range MSB:LSB!!#!
set fields [split $bitrange ":"];! lassign $fields msb lsb ;! puts "fields = $fields";! puts "msb = $msb";! puts "lsb = $lsb";!
set lsbmsb [string reverse $msblsb];! puts "lsbmsb = $lsbmsb";!
set lsbmsb_slice [string range ${lsbmsb} $lsb $msb];! puts "lsbmsb_slice = $lsbmsb_slice"!
set msblsb_slice [string reverse ${lsbmsb_slice}];! puts "msblsb_slice = $msblsb_slice"!
return ${msblsb_slice};!}!
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31 BTW October 2011
What Does a Board Test Person Need for FCT?
! Instrument IP ! BSDL Entity of Chip: Instruction to access
Instrument TDR ! PDL File that explains Instrument Operations
! Content for Data = iWrites, iReads, iScans = Vectors ! Content for Sequence = If-Then, For-Next = flow control
! ICL File that explains TDR connections to 1149.1 and Instrument Signals ! PDL and ICL may be produced by the tool that generates the
FCT Instrument IP
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32 BTW October 2011
A Tester Provides…?
! Testers are machines that deliver vectors to boards and chips to stimulate them; and received responses from the unit under test to evaluate the response ! A tester has an OS that organizes how vectors are applied
and how responses are received ! A tester has connections to the Unit Under Test ! A tester provides a Pass/Fail indicator ! A tester may facilitate Data Collection for characterization
or debug ! A tester may provide control of environmental or parametric
conditions (i.e. voltage, frequency, timing, temperature)
! Many testers have Operating Systems and User Interfaces that take years to learn
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33 BTW October 2011
Example of IJTAG-DL as OS
Instruments in FPGA
Instrument Operations
Operations Scheduled as Test Program
Drag & Drop Operations to Schedule Tests
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34 BTW October 2011
IJTAG-DL Run Result
Action Result
Compared Bits (Done, Fail, Error Data)
Memory Data Dump
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35 BTW October 2011
Data Display Tools
! Acquiring all data from instruments allows for intelligent parsing and displaying data in a relevant manner
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36 BTW October 2011
Summary-Conclusion
! P1687’s PDL allows IP to be embedded within FPGA’s that come with their own pre-canned procedures
! IJTAG Tools can then use PDL to become the operating system for FPGA-Based Embedded IP-Instruments
! A board-test analysis can provide the information and test goals needed to pick the correct IP and conduct an SOQ or FAM type test of peripherals on the board