High Speed Memory Debug Techniques
presented by:
Jennie GrosslightProject Development Manager
Memory Solutions
FuturePlus® Systems Corporation
High Speed Memory Debug Techniques
• Basic Strategy:– Eliminate unlikely causes thru quick checks and
automated tools so you can…
– Go deep on most likely causes with thorough checks
Typical Causes of Memory Failures
• Marginal timing relationships• Protocol violation • Clock integrity issues • SI failures• Other possibilities
– Incorrect BIOS setting for On Die Termination (ODT)– Invalid Cas latency
• Errors from other buses
1. Determine if the failure is repeatable.
2. Connect a logic analyzer to the memory bus with a probe or interposer to gain rapid insight
3. Run SW tests on LA traces
4. Parametric measurements
High Speed Memory Debug Techniques
Applicable to any SDRAM, Embedded or Standard Slots
Determine if failure is repeatable• Root cause of the problem can come from a sub-
system or applications that are not directly connected to memory. – LAN access, power sequences of subsystems, entering and
exiting sleep modes, and power cycles. Cross talk and conflicting resources from a variety of sub-systems, modes, and cycles.
• Isolation of a problem during a specific test or set of conditions
• Review error logs and identifying what software was running at the time of the failure.
• Environmental variants - What was the room temperature when the system failed? Check the airflow to system.
Determine if failure is repeatable• Hardware - Is the power to the system within
specifications? Has a system of this same design ever passed validation tests?
• Do other systems fail or is this failure unit specific? • What are the revisions on the board, DIMM, processor, or
other components of the failed system? • How does the failed system differ from working systems? • Have there been recent component changes in
manufacturing?• If conditions are repeatable, run your tests under those
conditions, if not chose a robust memory test and vary the test conditions, such as temperature and power supply limits, in a methodical manner.
1. Determine if the failure is repeatable. 2. Connect a logic analyzer to the memory bus with a
probe or interposer to gain rapid insight 1. Timing Zoom 2. Eye finder and Eye Scan3. State listing/waveforms4. Markers5. Filters
3. Run SW tests on LA traces 4. Parametric measurements
High Speed Memory Debug Techniques
Applicable to any SDRAM, Embedded or Standard Slots
64k deep 250ps resolution trace
• Key Points:
– LA provides rapid insight of timing relationships of entire bus.
– 64k of high resolution timing adjustable about trigger
– Markers for quick measurements
• Clock frequency
• Data valid windows
• CAS latency
Timing RelationshipsTiming Relationships
Eye Finder – Insight-at-a-glanceClock Signal IntegrityClock Signal Integrity
Clean clock
Dirty clock
• In this example, lower screen reveals Clock noise. Apparent by wider transition area at Time=0=clock edge.
• Additional information– Setup /hold of address
and control lines– Relative skew of
address/control signals
Time=0=clock edge
Eye Scan – In depth insight
• 10ps / 5mV resolution eye diagrams
• Rapid Detection– signals with parts per million errors – Skew
• Recognition of Parts per Million error allows in depth investigation of signals with errors as opposed to investigating all signals
View Specific ViolationsView Specific Violations
• State trace list with protocol decode allows detailed protocol check
• Global markers placed in State or Waveform window track to all LA windows
Markers and Measurements
Examples of FailuresProtocol ErrorProtocol Error
Patterns left to right: • B0 Activate (pink)
• B0 Writes (red)
• B1 Activate Missing (turquoiseturquoise)
• B1 Read (light bluelight blue)
Using Colorized filter for pattern recognition. Patterns possible include:
RAS / CAS delay
CAS latency
Precharge interval
Overview of memory access
Page access pattern
1. Determine if the failure is repeatable.
2. Connect a logic analyzer to the memory bus with a probe or interposer to gain rapid insight
3. Run SW tests on LA traces
4. Parametric measurements
High Speed Memory Debug Techniques
Applicable to any SDRAM, Embedded or Standard Slots
SW macro finds smallest data eyes
SW macro finds functional errors
1. Determine if the failure is repeatable.
2. Connect a logic analyzer to the memory bus with a probe or interposer to gain rapid insight
3. Run SW tests on LA traces
4. Parametric measurements
High Speed Memory Debug Techniques
Applicable to any SDRAM, Embedded or Standard Slots
Comprehensive Data AnalysisComplete Jitter Analysis
RJ/DJ (ISI,DCD, Periodic jitter) separation
Jitter histograms
Spectral analysis
Traceable to individual bits
Bathtub BER analysis
Masks
Real Time Eye
Eye unfolding identifies failure pattern
FBD Fixture control and compliance test suite integration
High Speed Memory Debug Techniques
• Summary:– Eliminate unlikely causes thru quick checks and
automated tools so you can…
– Go deep on most likely causes with thorough checks
FuturePlus® Systems Corporation
