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Galen Sasaki EE 260 University of Hawaii 1
Electronic Design Automation (EDA)
EE 260 University of Hawaii
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Galen Sasaki EE 260 University of Hawaii 2
Outline
• Design Flow– Hardware description languages (HDL),
e.g., verilog and VHDL
• Programmable Logic– PALs and PLAs– FPGAs
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Galen Sasaki EE 260 University of Hawaii 3
Simplified Design Flow
Design Problem
Design Circuit
Schematic
A description (or a model) of a circuit
Hardware Description Language (HDL) Verilog or VHDL
module Xcircuit(a0,a1,a2,y)input a0, a1, a2;output y;wire w1, w2;
assign w1 = a0&a1;assign w2 = ~a2;assign y = w1&w2;endmodule
a0a1
a2
y
Verify/Simulate Functionality(Debugging) This can be used to simulate design or to
implement in hardware
We’ll focus on these, but there’s more!
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Galen Sasaki EE 260 University of Hawaii 4
Simplified Design Flow
Hardware Description Language (HDL) Verilog or VHDL
module Xcircuit (a0,a1,a2,y)input a0, a1, a2;output y;wire w1, w2;
assign w1 = a0&a1;assign w2 = ~a2;assign y = w1&w2;endmodule
Schematic
a0a1
a2
yw1
w2
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Galen Sasaki EE 260 University of Hawaii 5
Design Problem
Design Circuit
Verify/Simulate Functionality(Debugging)
HDL model of a circuit (functional model,can be somewhat
abstract)
Logicworks
Draw schematic
Simulate inLogicworks
HDL
Write HDL code
Simulate usingtools such asModelsimsynopsis
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Galen Sasaki EE 260 University of Hawaii 6
Design Problem
Design Circuit
Verify/Simulate Functionality(Debugging)
HDL model of a circuit (functional model,can be somewhat
abstract)
HDL model of a circuit
Synthesize model toget a gate level description
Verify/Simulate Logicand Timing
Implement in hardwareMake sure design is
consistent in hardware
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Galen Sasaki EE 260 University of Hawaii 7
Computer Aided Design (CAD)
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Galen Sasaki EE 260 University of Hawaii 8
Hardware Technologies
• Programmable Logic Devices (PLDs)– Programmable Read Only Memory
(PROM). Erasable PROMs (EPROMS)– Programmable Arrayed Logic (PALs) and
Programmable Logic Arrays (PLAs)*
• Field Programmable Gate Arrays (FPGAs)*
• Application Specific ICs (ASICs)
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Galen Sasaki EE 260 University of Hawaii 9
Note that the next set of slides are (heavily) modified versions of slides found at
http://subjects.ee.unsw.edu.au/~elec1041
by Saeid Nooshabadi
The originals were adapted from
R. Katz’s Contemporary Logic Design
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Galen Sasaki EE 260 University of Hawaii 10
Programmable Logic Arrays (PLAs)
• Programmable technology for combinatorial logic
Sum of Products
• Array of ANDs followed by an array of Ors. Prefabricated
• Programmable by deleting connections at intersections
Inputs (ordinaryand complemented)
outputs
ANDs
ORs
Product terms
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Galen Sasaki EE 260 University of Hawaii 11
Programmable Array Logic (PALs)
• Each OR has its own set of ANDs (product terms)
Inputs (ordinaryand complemented)
outputs
ANDs
ORs
Product terms
• Easier to build, faster, and most cases it isn’t much of a limitation
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Galen Sasaki EE 260 University of Hawaii 12
PLD (Programmable Logic Devices)
DQ
DQ
DQ
CLK
RegisteredPAL
Can implementa Mealy orMoore circuit
Notefeedback
These thingscan be big: Complex PLDs(CPLDs)
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Galen Sasaki EE 260 University of Hawaii 13
Field-Programmable Gate Arrays
• Logic blocks
– To implement small combinational and sequential circuits
• Interconnect
– Wires and switches to connect logic blocks to each other and to inputs/outputs
• I/O blocks
– Special logic blocks at periphery of device forexternal connections
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CLB
CLB
CLB
CLB
SwitchMatrix
ProgrammableInterconnect I/O Blocks (IOBs)
D Q
SlewRate
Control
PassivePull-Up,
Pull-Down
Delay
Vcc
OutputBuffer
InputBuffer
Q D
Pad
D QSD
RD
EC
S/RControl
D QSD
RD
EC
S/RControl
1
1
F'
G'
H'
DIN
F'
G'
H'
DIN
F'
G'
H'
H'
HFunc.Gen.
GFunc.Gen.
FFunc.Gen.
G4G3G2G1
F4F3F2F1
C4C1 C2 C3
K
Y
X
H1 DIN S/R EC
Configurable Logic Block (CLB)– 5-input, 1 output function or two 4-input, 1 output
functions– optional register on output
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Galen Sasaki EE 260 University of Hawaii 15
Xilinx 4000 CLB
Can be configured to any small combinational or sequentialcircuit. In the case of comb circuits, the flip flops are bypassed
Flip flops
Programmablecombinationalcircuits
Multiplexers are used to choose/switchcomponents to be connected
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Galen Sasaki EE 260 University of Hawaii 16
Xilinx 4000Interconnect
We can connectCLBs and IOBsby using wiresand PSMs
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Galen Sasaki EE 260 University of Hawaii 17
Xilinx 4000 IOB
Similar to CLB but it’s used to connect pins of the chip with the internal circuit
Pad can be programmed asan input or output
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Galen Sasaki EE 260 University of Hawaii 18
FPGA
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Galen Sasaki EE 260 University of Hawaii 19
Final Comments
• ASICs– Usually cheaper (in bulk) and better performance– Goes to foundary and takes time. Better once
final design is done -- no changes
• FPGAs– Better for very rapid design and redesign. Good
for prototyping but also end design.– Better for small numbers of products– More expensive, and less in performance