-
FOW/PLP Consortium
Kick-off meeting
-
Fan-Out Wafer/Panel-Level Packaging
(FOW/PLP) Consortium (9:30 – 16:30, September 8, 2016)
Unimicron (欣興電子) No. 290, Chung-Lun Village, Hsinfeng, Hsinchu
(新竹縣新豐鄉中崙村290號)
AGENDA
9:30 – 9:35 Welcome (TJ Tseng, Chairman, Unimicron)
9:35 – 9:40 Welcome (Nelson Fan, Vice President, ASM-HK)
9:40 – 9:50 Self-introduction (all participants)
9:50 – 10:45 Objectives, scope, key tasks, approach, deliverables, IP issues,
communication methods, membership fee (all participants)
10:45 – 11:00 Tea break (all participants)
11:00 – 12:30 Key capability of each participant company (≤15 minutes for each
company)
12:30 – 1:30 Lunch (all participants)
1:30 – 3:00 Test vehicles (all participants)
3:00 – 3:10 Tea break (all participants)
3:10 – 3:50 Test vehicles and company task assignments (all participants)
3:50 – 4:30 Plant tour (all participants)
4:30 - So long (all participants)
-
FOW/PLP Consortium
Chip-First (die-up and die-down)
Fan-Out Wafer/Panel-Level
Packaging (FOW/PLP)
-
FOW/PLP Consortium Project
Title: Chip-First (die-up and die-down) FOW/PLP
Duration: 24 months
Fee: US$50,000*
Over
mold
the
reconfi
gured
carrier
Passi
vatio
n
CHIP CHIP R
DL
s
Sold
er
balls
R
DL
s
Sold
er
balls CHIP CHIP CHIP CHIP
Sol
der
ball
s
Over
mol
d
the
reco
nfig
ured
carri
er
R
D
L
s R
D
L
s
Passivatio
n Al or Cu
Pad Spin coat a
polymer and dice
the wafer
Sputter UBM and
electroplate
contact pad
*Please see The Rights and Fee of FOPLP Consortium Members.
Die-down Die-up Panel Panel
-
PURPOSES
The objective of the consortium is to develop
low-cost and high-throughput manufacturable
processes for FOW/PLP with emphasis on:
(a) WLSiP (wafer-level System-in-Package)
and PLSiP (panel-level System-in-
Package)
(b) P&P (pick & place) technology
(c) Low-warpage molding
(d) RDLs (redistribution-layers) technology
(e) Line width and spacing
-
Fan-Out Wafer/Panel-Level
Packaging (FOW/PLP)
Printed Circuit Board (PCB)
CHIP2 CHIP1 EMC
RDLs
Pad
Pad Solder
ball
-
Panel Sizes: 340mmx340mm (area: 1.6 times of 12”wafer)
457mmx610mm (area: 3.8 times of 12”wafer)
Wafer Size: 300mm
Line width/Spacing ≥10µm: Formation is chip-first with die-down
P&P use high-precision and SMT equipment
RDLs use PCB + LDI (laser direct imaging) technology
RDLs use polymer +ECD
Line width/Spacing
-
Design of Test Vehicles Electrical design & characterization of FOW/PLP
Structural design and optimization of FOW/PLP
Thermal design and optimization of FOW/PLP
FOPLP Technology P&P process development
Compression molding process development
Redistribution layer (RDL) process development
Solder ball mounting
Material selections
Warpage Control
Assembly and Reliability PCB Assembly processes development
Testing Characterizations
Reliability assessment and failure analysis
Key Tasks
-
Temporary panel carrier
2-side (thermal release ) tape
Remove carrier
and tape
Dice the molded panel into
individual packages
Die-first (face-down)
Over mold the
reconfigured
panel carrier
Passivation
Device
Wafer
CHIP CHIP KGD
RDLs Solder balls
Al or Cu Pad
KGD
Build RDLs and
mount solder balls
RDLs
Solder balls
CHIP CHIP KGD CHIP CHIP KGD
EMC
EMC (epoxy mold compound)
Chip-First (Die-Down) FOW/PLP
KGD KGD KGD
Test for known good die (KGD)
-
Spin Polymer
PI, BCB, or PBO
KGD
Al or Cu Pad Passivation
EMC
Photoresist
Mask aligner
or Stepper
(Litho)
Etch Polymer,
Strip Resist
Sputter
TiCu
TiCu
Photoresist
Strip Resist &
Etch TiCu
RDL1
Polymer
Mask aligner or
Stepper (Litho)
Cu Plating
KGD
RDL1
RDL2
TiCu
EMC
KGD
Al or Cu Pad Passivation
RDL1
RDL2
TiCu
EMC
UBM Contact pad
Solder
ball
Dielectric1
Dielectric2
RDLs by Polymer and Cu Electroplating (Die-Down)
-
KGD
Al or Cu Pad Passivation
EMC
Cu
Resin
Photoresist
Laser direct
imaging (LDI)
Cu etching
Strip
photoresist
Lamination of
a RCC on the
reconfigured
panel
Drilling
Cu plating to
fill the hole
and connect
to the pad
Photoresist
RDL1
KGD EMC
Resin
Resin
Cu
Cu RDL1
RDL2
Al or Cu Pad
KGD EMC
Passivation
Resin Cu RDL1
Resin Cu
RDL2 Resin Cu
Repeat all
the
processes
to get RDL2
Contact pad Solder mask Solder
ball
Repeat all the
processes to
get Cu contact
pads, spin coat
solder mask,
and mount
solder balls
RDLs by PCB + LDI Technology (Die-Down)
-
Temporary panel carrier
2-side tape
KGD KGD KGD
Build RDLs on
contact pads and
mount solder balls
Solder balls
RDLs
Remove carrier and tape and then
dice the molded wafer or panel
into individual packages
Die-first (face-up)
Device
Wafer
RDLs Solder balls
KGD
UBM Contact pad
KGD KGD KGD
Over mold the
reconfigured
panel carrier
EMC
Backgrind the
over-mold to
expose the
contact pad
Reinforced wafer (optional)
Sputter UBM and
electroplate contact pad
Passivation
UBM
Al or Cu Pad
Contact pad
KGD
Polymer
Spin coat a polymer and
dice the wafer
Chip-First (Die-Up) FOW/PLP
-
RDLs by Polymer and Cu Electroplating (Die-Up)
Passivation UBM
KGD EMC
Cu Pad
Passivation UBM Contact Pad Polymer
Polymer, e.g., PI, BCB, or PBO
Spin Polymer
Photoresist
Mask aligner
or Stepper
(Litho)
Etch Polymer,
Strip Resist
Sputter
TiCu
Photoresist
Cu Plating
RDL2
RDL1
Strip Resist &
Etch TiCu
RDL1
Polymer
TiCu
Solder
Ball Contact Pad UBM
EMC KGD
Cu Pad
Polymer
RDL1 RDL2
Contact Pad
TiCu
Dielectric1
Dielectric2
Mask aligner or
Stepper (Litho)
-
APPROACH Finalize FOW/PLP project scope and
test vehicle specification Members input
Electrical/Thermal
design
P&P
development
Molding process
development
RDL process
development
Test vehicle
fabrication
Electrical
characterization
Design/process/assembly
Improvement
Final test vehicle
fabrication and assembly
Final reliability test
and failure analysis
Quick reliability
assessment
Final electrical/
Thermal characterization
-
Design guidelines of using FOW/PLP.
Materials guidelines of using FOW/PLP.
Process guidelines (such as P&P, molding,
RDLs, ball mounting, dicing, and PCB assembly)
of using FOW/PLP.
Electrical modeling results and characterization
data for FOW/PLP.
Mechanical & thermal modeling results and
optimization for FOW/PLP.
Reliability data and failure analysis report of
FOW/PLP.
Cost models for FOW/PLP.
The limitations of FOW/PLP.
DELIVERABLES
-
IP Issues
In order to use a prior-art IP (intellectual property), it has to be
voted on by a simple majority by the members of this
consortium prior to its use.
The title, and interest to any IP developed during the course of
this project development shall be owned and the cost of all IPs
will be shared by the members of this consortium who have
contributed to the development of the IP.
Notwithstanding the foregoing, all the members of this
consortium (including those who have not contributed to the
development of the IP during the course of this project
development) shall have the right to use the IP developed
during the course of this project development in their normal
course of business without the need to pay any royalty fee for
their usage thereof.
-
Introduction to
ASM FOW/PLP Membership
-
The Rights and Fee of
FOW/PLP Consortium Members 1. The FOW/PLP consortium members shall
A. have a right to participate any portion of the project.
B. have a right to vote on the project expenses, which come
from the member fee.
C. have a right to jointly work out a future development
roadmap for FOW/PLP project and timeframe.
D. have a right to attend regular 3-month meeting/discussions
of FOW/PLP project.
E. have a right to obtain regular FOW/PLP project meetings,
minutes, and joint development status report on a monthly
basis.
2. Member fee is US$50,000, which covers project
materials (e.g., Si-wafer. UBM, and raw materials) and
sub-contract (e.g., reliability tests) cost.
-
FOW/PLP Consortium
Test Vehicles
-
Chip Size (9mm x 9mm) for Test Vehicles
(12” Wafer)
Pad
Daisy-Chain
Pad
150µm
70µ
m
Passivation UBM (Ti/Cu) Contact
pad
Pad Pad Pad Pad
Polymer
Si
Pad Pad
50µ
m
50µm Pad
CHIP 70µm
9mm
9m
m
Peripheral pads at 150µm
pitch (Staggered)
Area-array pads
at 150µm pitch
> 2500 pads
CHIP Pe
rip
he
ral p
ad
s a
t 1
50
µm
pit
ch
(S
tag
ge
red
)
60µm
-
Chip Size (5mm x 5mm) for Test Vehicles
(12” Wafer)
5mm
5m
m
Si
Passivation
Pad Pad
Peripheral Pads
Daisy-Chain
Pad Pad
70µ
m
100µm
CHIP
Pad Pad
50µ
m
50µm Pad
CHIP 70µm
For the 5x5mm
chip, there are
~200 peripheral
pads on a
100µm-pitch.
50µm
-
Chip Size (3mm x 3mm) for Test Vehicles
(12” Wafer)
Si
Passivation
Pad Pad
Peripheral Pads
Daisy-Chain
Pad Pad
70µ
m
100µm
Pad Pad
50µ
m
50µm Pad
CHIP 70µm
3m
m
3mm
CHIP
For the 3x3mm
chip, there are
~120 peripheral
pads on a
100µm-pitch.
50µm
-
Phase - I
-
300mm (Wafer) Carrier
5m
m
TV9W (Phase-I) >300 9mm
10mm
9mm
5mm
-
TV9 (Phase-I)
14m
m
FO Package (14mm x 14mm)
Line width/spacing of:
1st RDL are 5/5µm
2nd RDL are 10/10µm
3rd RDL are 15/15µm
CHIP
2.5mm
9m
m
14mm
9mm
2.5mm
EMC
-
TVWSiP (Phase-I) >350 300mm (Wafer) Carrier
8.12mm
8.12mm
3.88mm
3.88mm
-
TVSiP (Phase-I)
Line width/spacing of:
1st RDL are 10/10µm
2nd RDL are 15/15µm
12mm
12m
m
1.94mm
1.9
4m
m
1.94mm
1.9
4m
m
FO Package (12mm x 12mm)
5mm
5m
m
3mm
3m
m
120µm
120µ
m
CHIP1
CHIP2
3mm
3m
m
CHIP2
3m
m
3mm
CHIP4
EMC
CHIP3
0402
120µm
-
9mm
9mm
5mm
5mm
9mm
9mm
TV9P (Phase-I) 529 (23x23)
340m
m
340mm
-
TV9 (Phase-I)
14m
m
FO Package (14mm x 14mm)
Line width/spacing of:
1st RDL are 5/5µm
2nd RDL are 10/10µm
3rd RDL are 15/15µm
CHIP
2.5mm
9m
m
14mm
9mm
2.5mm
EMC
-
TVPSiP (Phase-I) 676 (26x26) 8.12mm
8.12mm
3.88mm
3.88mm
14mm
14mm
340m
m
340mm
-
TVSiP (Phase-I)
Line width/spacing of:
1st RDL are 10/10µm
2nd RDL are 15/15µm
12mm
12m
m
1.94mm
1.9
4m
m
1.94mm
1.9
4m
m
FO Package (12mm x 12mm)
5mm
5m
m
3mm
3m
m
120µm
120µ
m
CHIP1
CHIP2
3mm
3m
m
CHIP2
3m
m
3mm
CHIP4
EMC
CHIP3
-
First-Layer of RDL (Die-Down)
(Polymer + ECD)
Pad Pad Pad Pad CHIP
50
µm
10µm (Die-down)
20µm
4µm
Top-View
X-View
Daisy Chain (RDL)
Pad Pad
50µ
m
50µm Pad CHIP Top-View
Daisy Chain
70µm
-
First-Layer of RDL (Die-Up)
(Polymer + ECD)
Pad
Daisy-Chain
Pad
150µm
70
µm
Pad Pad Pad Pad
Si
Pad Pad
50µ
m
50µm Pad CHIP Top-View
Daisy Chain
70µm
Pad Pad Pad Pad
50
µm
5µm (Die-up)
20µm
Daisy Chain (RDL)
60µm
-
First-Layer of RDL (PCB +LDI)
Pad Pad Pad Pad CHIP
30
µm
10µm (Die-down)
15µm
Top-View
X-View
Pad Pad
50µ
m
50µm Pad CHIP Top-View
Daisy Chain
Daisy Chain (RDL)
-
NUCLEUS (ASM)
Molding ORCAS (ASM) ORCAS (ASM) ORCAS (ASM)
P&P
RDL
Ball Mount
PCA
Material
Line width/spacing of:
1st RDL are 5/5µm
2nd RDL are 10/10µm
3rd RDL are 15/15µm
CHIP
JCAP
DEK (ASM)
Huawei
DOW, Indium
Line width/spacing of:
1st RDL are 10/10µm
2nd RDL are 15/15µm
C2
C3 C4
C1
NUCLEUS (ASM),
SiPLACE (ASM)
Unimicron,
JCAP (?)
DEK (ASM)
Huawei
DOW, Indium
Line width/spacing of:
1st RDL are 10/10µm
2nd RDL are 15/15µm
C1 C2
C4 C3
NUCLEUS (ASM),
SiPLACE (ASM)
Unimicron,
JCAP
DEK (ASM)
Huawei
DOW, Indium
Die-Up Die-Down Die-Down
-
Phase - II
-
TV2PSiP (Phase-II) 1813 (49x37)
610mm (24”) 457m
m (
18”)
49 x 37 = 1813 units (packages)
Line width/spacing of RDL are 10/10µm
12mm
12m
m
1.94mm
1.9
4m
m
1.94mm
1.9
4m
m
FO Package (12mm x 12mm)
5mm
5m
m
3mm
3m
m
120µm
12
0µ
m
CHIP1
CHIP
2
3mm
3m
m
CHIP2
3m
m
3mm
CHIP4
EMC
CHIP3
6.5mm
11mm
-
610mm
(24”)
457m
m
(18”)
1813 SiPs
P&P NUCLEUS (ASM)
RDL
SiPLACE (ASM)
Unimicron, JCAP (?)
Molding ORCAS (ASM)
Ball Mount DEK (ASM)
PCA Huawei
Material DOW, Indium
Line width/spacing of RDL are 10/10µm
-
Company Task Assignments
-
Layout the
Test Chips
Fabricate the
Test-Chip Wafers
Backgrind the
Test-Chip Wafers
Dice the Test-
Chip Wafers
Test-Chip Wafer
Test-Chip Wafer Fabrication
0402 Capacitor
+
All
Sub-contract
DOW provide the
materials for making
the test-chip wafers
Sub-contract
Sub-contract
-
Pad
Daisy-Chain
Pad
150µm
70µ
m
Passivation UBM (Ti/Cu) Contact
pad
Pad Pad Pad Pad
Polymer
Si
Pad Pad
50µ
m
50µm Pad
CHIP 70µm
9mm
9m
m
Peripheral pads at 150µm
pitch (Staggered)
Area-array pads
at 150µm pitch
> 2500 pads
CHIP Pe
rip
he
ral p
ad
s a
t 1
50
µm
pit
ch
(S
tag
gere
d)
60µm
Note: Before dicing the test-chip wafer, laminate a die-attach
film (DAF) on the back-side of the test-chip wafer.
9mm x 9mm Test Chip
DAF
-
5mm 5m
m
Si
Passivation
Pad Pad
Peripheral Pads
Daisy-Chain
Pad Pad
70µ
m
100µm
CHIP
Pad Pad
50µ
m
50µm Pad
CHIP 70µm
For the 5x5mm
chip, there are ~200
peripheral pads on
a 100µm-pitch.
50µm
5mm x 5m Test Chip
-
Si
Passivation
Pad Pad
Peripheral Pads
Daisy-Chain
Pad Pad
70
µm
100µm
Pad Pad
50µ
m
50µm Pad
CHIP 70µm
3m
m
3mm
CHIP
For the 3x3mm
chip, there are ~120
peripheral pads on
a 100µm-pitch.
50µm
3mm x 3mm Test Chip
-
TV9W (Phase-I)
>300 Glass or Si Carrier Wafer (ASM)
P&P the Test Chips (face-up) on
the Carrier Wafer (NUCLEUS)
Compression Molding the Test
Chips on Carrier Wafer (ORCAS)
Backgrind the EMC and
Polymer to explore the Cu
Contact Pad (JCAP)
Build-up the RDLs with
Polymer and ECD (JCAP)
Solder-Ball Mounting (DEK)
Dicing the Molded Wafer into
Individual Packages (JCAP)
Remove the Carrier Wafer (ASM) DOW provide materials on
making the RDLs
Indium provide flux on ball
mounting
-
TVWSiP (Phase-I)
>350 Si Carrier Wafer with 2-side thermal release tape (ASM)
P&P the Test Chips
(face-down) on the
Carrier Wafer with
NUCLEUS
Compression Molding the Test Chips and
Capacitors on Carrier Wafer (ORCAS)
Solder-Ball Mounting (DEK)
Dicing the Molded Wafer into
Individual Packages (JCAP)
Remove the Carrier Wafer and tape (?)
P&P the Test Chips
(face-down) on the
Carrier Wafer with
SiPLACE
P&P the Capacitors with SiPLACE
RDLs with Polymer/ECD
JCAP
RDLs with PCB/LDI
UNIMICRON
DOW provide materials on
making the RDLs
Indium provide flux on ball
mounting
-
TVPSiP (Phase-I) 676 (26x26) Steel Panel with 2-side thermal release tape (ASM)
P&P the Test Chips
(face-down) on the
Panel with
NUCLEUS
Compression Molding the Test Chips and
Capacitors on the Panel (ORCAS)
Solder-Ball Mounting (DEK)
Dicing the Panel into Individual
Packages (UNIMICRON)
Remove the Panel and tape (?)
P&P the Test Chips
(face-down) on the
Panel with
SiPLACE
P&P the Capacitors with SiPLACE
RDLs with Polymer/ECD
JCAP (?)
RDLs with PCB/LDI
UNIMICRON
DOW provide materials on
making the RDLs
Indium provide flux on ball
mounting
-
Component Qualification Test
A test socket for BGA-like packages:
14m
m
CHIP
9m
m
14mm
9mm
12mm 12m
m
5mm
5m
m
3mm
3m
m
CHIP1
CHI
P2
3m
m
CHIP2
CHIP4 CHIP3
-
Test Board Layout, Fabrication, Assembly and
Reliability Test
PCB
JESD22-B111 for Drop Test
JESD22-A104D for Temperature Cycling Test
Huawei
Indium
-
Things Needed to be Discussed For the large chip (face-up) Die-attach film (kind, company, de-bond,
shelf life, etc.)
For the large chip (face-up) Polymer (kind, company, can the polymer
backgrind with the EMC? Transparent for alignment mark?)
Carrier materials – glass, Si, metal such as steel, etc.
P&P accuracy for large die with fine (5µm) line width/spacing
P&P accuracy for small die with 10µm line width/spacing
EMC – Sumitomo (solid) and Nagase (liquid)
RDL – JCAP say something
RDL – Unimicron say something
RDL – DOW say something
Solder-Ball Mounting – DEK say something
Removing the carrier wafer (large chip) De-bond the die-attach film
Dicing the molded wafer into individual package
Test socket for the 14x14mm package and the 12x12mm package
Test board layout, fabrication, assembly, and reliability tests – Huawei
and Indium
0402 Termination metal
-
Thank you very much for your
attention!