Fabrication and Characterization of Ultra-narrow RRAM Cells
Byoungil Lee and H.-S. Philip WongElectrical Engineering,
Stanford University
• Motivations• AlOx RRAM typical cell characteristics• Fabrication of ultra-narrow RRAM
cells• Characterization of ultra-narrow cells• Summary and discussion
Outline
• Motivations– Issues with RRAM
• Over-SET by over-shoot current.• Poor LRS uniformity, large reset current, and
device failure.• Current-limiting devices are required.• Implementation of ‘Within-A-Cell-Current-
Limiter’.
– Study of scaling
Ultra-narrow RRAM Cells
– Bipolar switching.– Large variation in LRS and IRESET.
AlOx RRAM Large Cell
AlOx
Pt
PtTiN
10nm
W
w
w
-2 -1 0 1 2-400
-200
0
200
400
Voltage (V)
Cu
rre
nt (
A) W = 10m
AlOx RRAM Large Cell
0 500 1000 1500
103
104
105
Cycles
Re
sis
tan
ce(Ω
)
10m 0.5m
1k 10k0
0.2
0.4
0.6
0.8
1
Partial SETCurrent Overshoot
LRS (Ω)C
um
ula
tive
Fre
qu
en
cy
4.5kΩ
10m0.5m
– Filamentary conduction property. – Does not scale with the size.
AlOx RRAM Large Cell
1k 10k0
0.2
0.4
0.6
0.8
1
Partial SETCurrent Overshoot
LRS (Ω)C
um
ula
tive
Fre
qu
en
cy
4.5kΩ
10m0.5m
– Filamentary conduction property. – Does not scale with the size.– LRS and IRESET are determined by Ilimit
0 2k 4k 6k0
50
100
1500 2k 4k 6k0
50
100
150
Current Overshoot
Partial SET
LRS (Ω)
10m
0.5m
0.1 1 10 100
1
10
100
Limited SET current (mA)
Rese
t Cur
rent
( mA
) [Seo 04]
[Kinoshita 08]
I(RESET) = I(SET)
IRESET ISET in RRAM
1
0.1
0.01 0.1 1 10 100Cell Area (m2)
Rese
t Cur
rent
( mA
) [Lee 08]
This work
1k
Cell Area (m2)LR
S ( Ω
)0.01 0.1 1 10 100
10k
100k [Lee 08]This work
Scaling Trend of RRAM
– Filamentary conduction property. – No scaling with the size in the previous works.– LRS of our RRAM cell does scale with the size!
Ultra-narrow RRAM Cell using ALD AlOx
w
w
100nm
– Top-view SEM of the fabricated devices. – Smallest cell size: 50nm X 50nm
- Top Pt: 40nm, TiN: 40nm- Oxides thickness: 7.4 nm- Bottom Pt: 40nm- Metal width: 100nm- AlOx width: 10nm
TiN
Pt
Pt
10nm
AlOx
SiO2
20nm
Ultra-narrow RRAM Cell using ALD AlOx
Pattern bottom Pt lines
Deposit PECVD SiO2
Deposit reactively sputtered TiN at room temperature
Pattern top Pt lines
Dry-etch TiN and SiO2 usingthe top Pt lines as a mask
Wet-etch 10nm of SiO2
Deposit ALD AlOx at 300C
Dry-etch AlOx
PtSiO2
PtTiN
PtSiO2
PtTiN
PtSiO2
PtTiN
PtPtSiO2
PtTiN
d
w
tAlOx
Process Flow
-4 -2 0 2-600
-400
-200
0
200
400
600
Voltage (V)
Curr
ent (
A) 4.7kΩ 14kΩ
26kΩ
400nm100nm50nm
DC I-V Characteristics
– SET current is limited without any external cur-rent-limiters.
– Due to resistive TiN layer and small contact area.
0 0.01 0.02 0.030
200
400
600
800
1/Line width (1/nm)
100nm
50nm
Resi
stan
ce (Ω
)
300nm
Line Resistance
– Current-limiting is not a result of the long electrode line.
– New device features ‘Within-A-Cell-Current-Limiter.’
0 200 400 600 800 1000
10k
1M
0.1G
Cycles
Resi
stan
ce ( Ω
)
50nm100nm
400nm
1k 10k 100k0
0.2
0.4
0.6
0.8
1
LRS (Ω)C
um
ula
tive
Fre
qu
en
cy
500nmRef. cell 400nm 100nm 50nm
Programming Cycle Test
– 500nm standard cell shows a broad tail in LRS distribu-tion.
– Ultra-narrow cells truncate lower-end of LRS distribution.
1
0.1
0.01 0.1 1 10 100Cell Area (m2)
Rese
t Cur
rent
( mA
) [Lee 08]
This work
1k
Cell Area (m2)LR
S ( Ω
)0.01 0.1 1 10 100
10k
100k [Lee 08]This work
Scaling Trend of Ultra-narrow Cells
– Filamentary conduction property. – IRESET and LRS does scale with the size!
0 50 100 150 200 250 300
10k
1M
100M0 50 100 150 200 250 300
10k
1M
100M
Cycles
Resi
stan
ce ( Ω
)Re
sist
ance
( Ω)
22
7
- SET/RESET: 30ns/1us
- SET/RESET: 4ns/20ns
Programming Speed
0 4000 8000 12000
10k
1M
100M
Cycles
Resi
stan
ce ( Ω
)
Programming Endurance
– 104 programming cycles.