Download - EE3202 Ch11 Memory and Programmable Logic
![Page 1: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/1.jpg)
LOGIC DESIGN
MEMORY AND PROGRAMMABLE LOGIC
EE3202 1Ertuğrul Eriş
![Page 2: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/2.jpg)
EE33201 COURSE ASSESMENT MATRIX
LOGIC DESIGN LEARNING OUTCOMES a b c d e f g h i j k
Will employ Boolean Algebra in logic circuits modelling.
3 3 3 1 2
Wiil carry out aritmetic operations by using 2’s complement reperesentation of negative numbers
3 3
Will analyse Logic Circuits which include Small Scale Integrated components, by using various methods.
3 3 3 1 2
Will design logic circuits which include small scale integrated components, by using various methods.
3 3 3 1 2
Will analyse logic circuits which include medium scale integrated components, by using various methods.
3 3 3 1 2
Will design logic circuits which include medium scale integrated components, by using various methods.
3 3 3 1 2
Will analyse logic circuits which include large scale integrated components, by using various methods.
3 3 3 1 2
Will design logic circuits which include large scale integrated components, by using various methods.
3 3 3 1 2
Will simulate logic circuits by employing " proteus" as a tool.
3 3 3 1 2
![Page 3: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/3.jpg)
CONVENTIONAL AND ARRAY LOGIC DIAGRAMS FOR OR GATE
EE3202 3Ertuğrul Eriş
![Page 4: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/4.jpg)
BLOCK DIAGRAM OF A MEMORY UNIT
EE3202 4Ertuğrul Eriş
![Page 5: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/5.jpg)
CONTENTS OF A 1024 X 16 MEMORY
EE3202 5Ertuğrul Eriş
Is this sequential? State diagram? Mathematical model?
![Page 6: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/6.jpg)
CONTROL INPUTS TO MEMORY CHIP
EE3202 6Ertuğrul Eriş
![Page 7: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/7.jpg)
MEMORY CYCLE TIMING WAVEFORMS
EE3202 7Ertuğrul Eriş
![Page 8: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/8.jpg)
MEMORY CELL
SRAM (Static RAM): Requires 6 transistorsDRAM (Dynamic RAM): Requires a single MOS transistor and and a capacitor, Low power
EE3202 8Ertuğrul Eriş
![Page 9: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/9.jpg)
DIAGRAM OF A 4 X 4 RAM
EE3202 9Ertuğrul Eriş
![Page 10: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/10.jpg)
TWO-DIMENSIONAL DECODING STRUCTURE FOR A 1K-WORD MEMORY
Single Dimention Decoder
Two Dimention
Decoder
Number of AND gates
1024 64
AND gates inputs
10 5
Adsress bits
10 10
EE3202 10Ertuğrul Eriş
![Page 11: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/11.jpg)
ADDRESS MULTIPLEXING FOR A 64K (216) DRAM
• Two dimentional Decoding: 16 address-bit input• Address multiplexing: 8 address-bit input in the IC package
CAS: Column Address StrobeRAS: Row Adsress Strobe
EE3202 11Ertuğrul Eriş
Bir önce devre ile bu devrenin karşılaştırılması:• Bacak sayısıGeçikme
![Page 12: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/12.jpg)
ROM BLOCK DIAGRAM
k: Number of address bits2k: Number of address, number of n-bit-words stored2k x n = Number of connections between AND and OR gates
EE3202 12Ertuğrul Eriş
![Page 13: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/13.jpg)
INTERNAL LOGIC OF A 32 X 8 ROM
k: Number of address bits = 52k: Number of address, number of n-bit-words stored = 32, n = 82k x n = 32 x 8 = 256 connections
EE3202 13Ertuğrul Eriş
![Page 14: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/14.jpg)
PROGRAMMING THE ROM
EE3202 14Ertuğrul Eriş
![Page 15: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/15.jpg)
ROM IMPLEMENTATION OF COMBINATIONAL CIRCUITS
EE3202 15Ertuğrul Eriş
![Page 16: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/16.jpg)
BASIC CONFIGURATION OF THREE PLDs
PLD: Programmable Logic Devices: Combinational, Sequentials
EE3202 16Ertuğrul Eriş
![Page 17: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/17.jpg)
PLA WITH THREE INPUTS, FOUR PRODUCT TERMS, AND TWO OUTPUTS
EE3202 17Ertuğrul Eriş
![Page 18: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/18.jpg)
PLA SECOND EXAMPLE F1(A, B, C) = Σ (0, 1, 2, 4)F2(A, B, C) = Σ (0, 5, 6, 7)
F1 = (AB + AC+ BC)’ F2 = AB + AC+ A’B’C’
EE3202 18Ertuğrul Eriş
![Page 19: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/19.jpg)
PLA SIZE PROGRAMMING n inputs, k product terms, m outputs n buffer-inventor gates, k AND gates, m OR gates,
m XOR gates 2n x k connections between and AND array gates k x m connections between AND and OR gates m connections with the XOR gates Typical: n = 16, k = 48, m = 8 Programming
Mask programmable PLA Field programmable PLA
EE3202 19Ertuğrul Eriş
![Page 20: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/20.jpg)
PAL WITH FOUR INPUTS, FOUR OUTPUTS, AND A THREE-WIDE AND-OR STRUCTURE
• Typical: Four inputs, four outputsFour sections: three wide AND-OR
• Commercial: eigth inputs, eight outputs, eigth section: eigth-wide ABD_OR array
In designing with Pal, The Boolean functions must beSimplified to fit into each section
EE3202 20Ertuğrul Eriş
![Page 21: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/21.jpg)
FUSE MAP FOR PAL AS SPECIFIED IN THE TABLE
EE3202 21Ertuğrul Eriş
w(A, B, C, D) = Σ (2,12,13)x(A, B, C, D) = Σ (7,8,9,10,11,12,13,14,15)y(A, B, C, D) = Σ (0,2,3,4,5,6,7,8,10,11,15)z(A, B, C, D) = Σ (1,2,8,12,13)
w = ABC’ + A’B’CD’x = A + BCDy = A’B + CD + B’D’z = ABC’ + A’B’CD’ +AC’D’ + A’B’C’D = w + AC’D’ + A’B’C’D
![Page 22: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/22.jpg)
SEQUENTIAL PROGRAMMABLE LOGIC DEVICE
EE3202 22Ertuğrul Eriş
![Page 23: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/23.jpg)
BASIC MACROCELL LOGIC
OE: Output enable controls three state output buffer
A typical SPLD 8 to 10 macrocells within one IC package
EE3202 23Ertuğrul Eriş
![Page 24: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/24.jpg)
GENERAL CPLD CONFIGURATION
• (I/O) blocks provide connections to the IC pins. • Each I/O pin is driven by a three state buffer and can be programmed to act as input or output.• The switch matrix receives inputs from I/O the block and directs them to the individual macrocells.• Selected outputs from macrocells are sent to the outputs as required.• unused product terms can be used by other nearby macrocells.• PLDs sometimes called ‘function blocks’
EE3202 24Ertuğrul Eriş
![Page 25: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/25.jpg)
FPGA (FIELD PROGRAMMABLE GATE ARRAY)
Typical FPGA logic block consists of lockup tables, multiplexers, gates, and flip-flops. A lookup table is a truth table stored in an SRAM and provides the combinational circuit functions for the logic block.
Combinational logic section, along with a number of programmable multiplexers, is used to configure the input equations for the flip-flop and the output of the logic block.
Different firm different configurations Requires extensive CAD tools to facilitate synthesis
procedure HDL (Hardware Description Language): ABEL, VHDL,
Verilog
EE3202 25Ertuğrul Eriş
![Page 26: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/26.jpg)
BASIC ARCHITECTURE OF XILINX SPARTAN AND PREDECESSOR DEVICES
EE3202 26Ertuğrul Eriş
CLB: Configurable logic blockIOB: Input/Output block
![Page 27: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/27.jpg)
CLB(CONFIGURABLE LOGIC BLOCK) ARCHITECTURE
EE3202 27Ertuğrul Eriş
![Page 28: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/28.jpg)
CLB ARCHITECTURE CLB (configurable Logic Block) consists of
Look up table, muxs, registers, paths for control signals F, G function generators
Look up tables, generate any four varible function
H function block Can Get its input from look up tables or from external inputs
EE3202 28Ertuğrul Eriş
![Page 29: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/29.jpg)
CELL CONTROLLING A PIP TRANSMISSION GATE
EE3202 29Ertuğrul Eriş
![Page 30: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/30.jpg)
CIRCUIT FOR A PROGRAMMABLE PIP
EE3202 30Ertuğrul Eriş
![Page 31: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/31.jpg)
XC4000 SERIES IOB
EE3202 31Ertuğrul Eriş
![Page 32: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/32.jpg)
DISTRIBUTED RAM CELL FORMED FROM A LOCKUP TABLE
EE3202 32Ertuğrul Eriş
![Page 33: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/33.jpg)
SPARTAN DUAL-PORT RAM
EE3202 33Ertuğrul Eriş
![Page 34: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/34.jpg)
ATRIBUTES OF THE XILINX SPARTAN XL DEVICE FAMILY
EE3202 34Ertuğrul Eriş
![Page 35: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/35.jpg)
SPARTAN 11 DEVICE ATTRIBUTES
EE3202 35Ertuğrul Eriş
![Page 36: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/36.jpg)
COMPARISON OF THE SPARTAN DEVICE FAMILIES
EE3202 36Ertuğrul Eriş
![Page 37: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/37.jpg)
SPARTAN II ARCHITECTURE
EE3202 37Ertuğrul Eriş
![Page 38: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/38.jpg)
SPARTAN 11 CLB SLICE
EE3202 38Ertuğrul Eriş
![Page 39: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/39.jpg)
SPARTAN II IOB
EE3202 39Ertuğrul Eriş
![Page 40: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/40.jpg)
VIRTEX II OVERALL ARCHITECTURE
EE3202 40Ertuğrul Eriş
![Page 41: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/41.jpg)
VIRTEX IOB BLOCK
EE3202 41Ertuğrul Eriş
![Page 42: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/42.jpg)
PROGRAM OUTCOMES
PROGRAM DESIGN
??? CIRCICULUM
???
??? CIRCICULUM
???
Std. questionnaire
Std. questionnaire
Std. questionnaire
STUDENT PROFILE
DEPT, PROGRAM
STUDENTNEWCOMER
STUDENT
QUALITY IMP. TOOLS
EXTRERNAL CONSTITUENT
FACULTY
GOVERNANCE
INTRERNAL CONSTITUENT
STUDENT,
STATE, ENTREPRENEUR
ALUMNI, PARENTS
NGO
GOAL: NATIONAL/INTERNATIONAL ACCREDITION
E
U/N
AT
ION
AL
QU
ALI
FIC
AT
ION
S
EU/NATIONAL
GRADUATE
STUDENT
QUESTIONNAIRES
FIELD QUALIFICATIONS
KNOWLEDGE
SKILLS
COMPETENCES
EXTRERNAL CONSTITUENT REQUIREMENTS
ORIENTIATION
ORIENTIATION
PROGRAM OUTCOMES
PROGRAM
OUTCOMES
PROGRAM
OUTCOMES
FIELDQALIFICATIONS
42
![Page 43: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/43.jpg)
BLOOM’S TAXONOMYANDERSON AND KRATHWOHL (2001)
July 2011 Ertuğrul Eriş 43
http://www.learningandteaching.info/learning/bloomtax.htm
!!Listening !! Doesn’t exits in the original!!!
![Page 44: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/44.jpg)
44
TÜRKİYE YÜKSEKÖĞRETİM ULUSAL YETERLİKLER ÇERÇEVESİ (TYUYÇ)
TYUYÇDÜZEYİ
BİLGİ- Kuramsal- Uygulamalı
BECERİLER- Kavramsal/Bilişsel- Uygulamalı
KİŞİSEL VE MESLEKİ YETKİNLİKLER
Bağımsız Çalışabilme ve Sorumluluk
Alabilme Yetkinliği
Öğrenme Yetkinliği
İletişim ve Sosyal Yetkinlik
Alana Özgü ve Mesleki Yetkinlik
6LİSANS
_____
EQF-LLL:6. Düzey
_____
QF-EHEA:1. Düzey
- Ortaöğretimde kazanılan yeterliklere dayalı olarak alanındaki güncel bilgileri içeren ders kitapları, uygulama araç –gereçleri ve diğer bilimsel kaynaklarla desteklenen ileri düzeydeki kuramsal ve uygulamalı bilgilere sahip olmak
- Alanında edindiği ileri düzeydeki kuramsal ve uygulamalı bilgileri kullanabilmek,
- Alanındaki kavram ve düşünceleri bilimsel yöntemlerle inceleyebilmek, verileri yorumlayabilmek ve değerlendirebilmek, sorunları tanımlayabilmek, analiz edebilmek, kanıtlara ve araştırmalara dayalı çözüm önerileri geliştirebilmek.
- Uygulamada karşılaşılan ve öngörülemeyen karmaşık sorunları çözmek için bireysel ve ekip üyesi olarak sorumluluk alabilmek,
- Sorumluluğu altında çalışanların mesleki gelişimine yönelik etkinlikleri planlayabilmek ve yönetebilmek
- Edindiği bilgi ve becerileri eleştirel bir yaklaşımla değerlendirebilmek, öğrenme gereksinimlerini belirleyebilmek ve öğrenmesini yönlendirebilmek.
- Alanıyla ilgili konularda ilgili kişi ve kurumları bilgilendirebilmek; düşüncelerini ve sorunlara ilişkin çözüm önerilerini yazılı ve sözlü olarak aktarabilmek,
- Düşüncelerini ve sorunlara ilişkin çözüm önerilerini nicel ve nitel verilerle destekleyerek uzman olan ve olmayan kişilerle paylaşabilmek,
- Bir yabancı dili kullanarak alanındaki bilgileri izleyebilmek ve meslektaşları ile iletişim kurabilmek (“European Language Portfolio Global Scale”, Level B1)
- Alanının gerektirdiği düzeyde bilgisayar yazılımı ile birlikte bilişim ve iletişim teknolojilerini kullanabilmek (“European Computer Driving Licence”, Advanced Level).
- Alanı ile ilgili verilerin toplanması, yorumlanması, duyurulması ve uygulanması aşamalarında toplumsal, bilimsel ve etik değerlere sahip olmak,
- Sosyal hakların evrenselliğine değer veren, sosyal adalet bilincini kazanmış, kalite yönetimi ve süreçleri ile çevre koruma ve iş güvenliği konularında yeterli bilince sahip olmak.
ULUSAL LİSANS YETERLİLİKLER ÇERÇEVESİ
BLOOMS TAXONOMY
October 2011 Ertuğrul Eriş
![Page 45: EE3202 Ch11 Memory and Programmable Logic](https://reader036.vdocuments.site/reader036/viewer/2022062320/55cf99c9550346d0339f28dd/html5/thumbnails/45.jpg)
COURSE ASSESMENT MATRIX
EE3202 LOGIC DESIGN a b c d e f g h i j k
1. Will employ Boolean Algebra in logic circuits modelling. 3 3 3 3
2. Will analyse Logic Circuits which include Small Scale Integrated components, by using various methods.
3 3 3 3 1 3
3. Will design logic circuits which include small scale integrated components, by using various methods.
3 3 3 3 1 3
4. Will analyse logic circuits which include medium scale integrated components, by using various methods.
3 3 3 3 1 3
5. Will design logic circuits which include medium scale integrated components, by using various methods.
3 3 3 3 1 3
6. Will analyse logic circuits which include large scale integrated components, by using various methods.
3 3 3 3 1 3
7. Will design logic circuits which include large scale integrated components, by using various methods.
3 3 3 3 1 3
8. Will simulate combinational logic circuits by employing " proteus" as a tools.
3 3 3 3 1 3
1. Will employ Boolean Algebra in logic circuits modelling.3 3 3 3 1 3
EE3202 Ertuğrul Eriş 45
LE
AR
NIN
G O
UT
CO
ME
S