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inst.eecs.berkeley.edu/~ee241b
Borivoje Nikolić
EE241B : Advanced Digital Circuits
Lecture 24 – Clocks
EECS241B L24 CLOCKS 1
Time for course surveys!
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Announcements
• Quiz today
• Final this Thursday, April 29, 9:40-11• In class, 80 min
• Project reports due on Wednesday, May 5, 9pm• Presentations on Thursday 9:30-11
EECS241B L24 CLOCKS 2
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Outline
• Digital PLLs
• Clocks and deskewing
• Supply droop mitigation
3EECS241B L24 CLOCKS
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6.E Digital PLLs
EECS241B L24 CLOCKS 4
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Digital PLL
• Replace analog functions with digital equivalents
PFD Digital LoopFilter
DCO÷N
U
D
fO
fREF
Digitally-controlled oscillator (DCO)
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Practical Digital PLL
• In IBM Power7 processor, per each core
Tierno, VLSI’10
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6.F Deskewing and Synchronization
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Clock Distribution
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Example Clock System
• IBM Power 4
Restle, ISSCC’02
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Clock Grid
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Clock Domain Synchronization
Type Frequency Phase
Synchronous Same Same
Mesochronous Same Constant offset
Plesiochronous Small difference Slowly varying
Asynchronous Different Arbitrary
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Deskew System (Mesochronous)
Geannopoulos, ISSCC’98
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Clock Domain Crossings
• Bowhill, ISSCC’15
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Brute-Force Synchronizer
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Clock Crossing FIFOs
• FIFO for clock crossings
http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf
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6.G Interaction Between Supply and Clock
EECS241B L24 CLOCKS 16
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Power Delivery
• Typical model
Wong, JSSC’06EECS241B L25 SUPPLY
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Supply Resonances
• First droop• Package L + on-die C
• Second droop• Motherboard + package decoupling
• Third droop• Board capacitors
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What happens with supply?http://www.research.ibm.com/people/r/restle/Animations/DAC01top.html
Phillip Restle, IBMEECS241B L25 SUPPLY
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Clock and Supply
• Large digital systems can have large voltage transients• Can we filter impact of voltage on a clock generator?
Kurd, JSSC’09
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How to model
• Abstracted delay line
EECS241B L25 SUPPLYPeriod modulation from successive modulated delays
Wong, JSSC’06
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Clock and Supply
• IBM Power7, with one PLL per core
Lefurgy, MICRO’11
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Droop Detection
• Hashimoto, JSSC 4/18
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Wrap-Up
EECS241B L24 CLOCKS 24
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This Class
• Put design choices in technology perspective
• The design constraints have changed and will be changing• Cost, energy, (power, leakage, …), performance
• Focused on variability, power-performance tradeoffs, power management
• Did not cover arithmetic, domino, I/O, supply generation, packaging, …
EECS241B L25 SUPPLY
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This Field
• Moore’s law will end sometime during your (my?) career• 5nm in 2021 scales to 0.1nm by 2050 with 2-yr cycles (or to 1nm with 5-yr cycles)
• Physics will stop CMOS somewhere ~2nm (?)• Will we see a different (CMOS) device in the meantime
• Economics will likely stop it somewhere while still in single digits• And the nodes will be stretched out
• We will see multi-chip/packaging solutions
• Don’t worry: Creativity is unlimited!• What can you build with 10B/100B/1 trillion transistors?
• Even filling 10B-transistor chips with SRAM is not trivial!
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This Field
• Focus on principles
• Watch out for opportunities
• Stay current!
EECS241B L25 SUPPLY
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Technology Strategy / Roadmap
2000 2005 2010 2015 2020 2025 2030
Plan B: Subsytem Integration
R D
Plan C: Post Si CMOS Options
R R&D
Plan Q:
R D
Quantum Computing
Plan A: Extending Si CMOS
R D
T.C. Chen, Where Si-CMOS is going: Trendy Hype vs. Real Technology, ISSCC’06EECS241B L25 SUPPLY