Download - EE 330 Lecture 44
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EE 330
Lecture 44
Digital Circuits
• Ring Oscillators
• Sequential Logic
• Array Logic
• Memory Arrays
Final: Tuesday Dec 12 12:00 - 2:00
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Dynamic LogicVDD
F
φ
A PDNn
φBasic Dynamic Logic Gate
Any of the PDNs used in complex logic gates would work here !
• Have eliminate the PUN !
• Ideally will have a factor of 4 or more reduction in CIN
• Ideally will have a factor of 4 or more reduction in dynamic power
dissipation relative to that of equal rise/fall !
• Ideally will have a factor of 2 reduction in dynamic power dissipation
relative to that of minimum size!
Review from Last Time
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Dynamic LogicVDD
F
φ
A PDNn
φ
Basic Dynamic Logic Gate
Advantages:
•Lower dynamic power dissipation (Ideally 4X)
• Improved speed (ideally 4X)Limitations:
• Output only valid during evaluate state
• Need to route a clock
(and this dissipates some power)
• Premature Discharge !
• More complicated
• Charge storage on internal nodes of PDN
• No Static hold if output H
Review from Last Time
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Domino Logic
VDD
φ
A PDNn
Fφ
Review from Last Time
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Dynamic Logic
• p-channel logic gate will pre-charge low
• Phasing of PUN and PDN networks is reversed
• Some performance loss with p-channel logic devices
• Direct coupling between alternate type dynamic gates is possible
without causing a premature discharge problem
VDD
F
φ
A PDNn
VDD
F
A PUNn
φ
φ
φ
Review from Last Time
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Zipper Logic
Acceptable Implementation in Zipper
Review from Last Time
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Digital Circuit Design
• Hierarchical Design
• Basic Logic Gates
• Properties of Logic Families
• Characterization of CMOS
Inverter
• Static CMOS Logic Gates
– Ratio Logic
• Propagation Delay
– Simple analytical models• FI/OD
• Logical Effort
– Elmore Delay
• Sizing of Gates
• Propagation Delay with
Multiple Levels of Logic
• Optimal driving of Large
Capacitive Loads
• Power Dissipation in Logic
Circuits
• Other Logic Styles
– Dynamic Logic
– Array Logic
• Ring Oscillators
• Sequential Logic Circuits
• Memory Arrays
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Ring Oscillators
Ring OscillatorXSIG
• Odd number of stages will oscillate (even number will not oscillate)
• Waveform nearly a square wave if n (number of stages) is large
• Output will slightly imbalance ring and device sizes can be compensated if
desired
• Usually use a prime number (e.g. 31)
• Number of stages usually less than 50 (follow by dividers)
• Frequency highly sensitive to process variations and temperature
XSIG
OSCPROP
1f
nt
• n is the number of stages
• tPROP is the propagation delay of a single stage (all assumed
identical)
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Digital Building Blocks
• Combinational Logic
• Sequential Logic
– Shift Registers (stack)
• Array Logic
• Memory Arrays
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Sequential Logic Circuits
• Flip Flops needed for sequential logic
circuit
• Only one type of flip flop is required
• Invariably require clocked edge-triggered
master-slave flop flops
• Flip flop circuits can be very simple
• Flip flops are part of Standard Cell
Libraries
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Sequential Logic Elements
Latch
D Q
LKC
Latch
Pulsed Latch
D Q
LKC
Pulsed
Latch
Flip Flop
XQ
LKC
Flip
FlopQ
D is held on Q when CLK is low
may also be presentQ
D is held on Q when CLK is low
CLK is a pulse
may also be present
Special case of LatchQ
May have one or two inputs
Inputs transferred to output on CLK
Four basic types
J-K, S-R, D, T
Any type can be obtained from other
with simple combinational logic ckts
Often edge triggered and Master-Slave
Most widely used sequential logic element
All can have preset or clear input added
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Latch Flip-Flop Terminology
• Transparent:– Input to Latch Appears on the Latch Output
immediately while in transparent state
• Opaque– Input to the Latch does not appear at the output while
in the opaque state
• Edge Triggered– Input to latch at a clock transition determines when
the input is transferred to the latch output
• Master-Slave– Two-stage cascaded structure where output from one
serves as input to the second stage
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Latches
CX
DQ
C LOAD
CX
DQ
C
•Very simple
•When XC is high, in transparent state (tracks input)
•Negative edge triggered
Limitations:
• Q can get to only VDD-VT
• Leakage of charge will occur when XC is low
• Any loads placed on Q will further degrade held signal
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Latches
• Buffering eliminates loading
• Provides rail-rail output
• Provides signal inversion
• Second inverter will eliminate signal inversion
• Output transparent when XC is high
DQ
C LOAD
CX
D Q
CX
• C is input capacitance to inverter
• Need not show load since buffered
• Charge will eventually leak off of C
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Latches
• Becomes nonvolatile
• Provides complimentary output
• Output transparent when XC is high
• Contention on output when loading
- (must size devices so latch will load)
D Q
CX
Q
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Latches
D Q
CX
CX
Q
• Becomes nonvolatile
• Provides complimentary output
• Output transparent when XC is high
• Contention on output removed
• 6-transistor Cell
• Actually the basic memory element used in many SRAM
arrays
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Flip FlopsFour Basic Flip Flops
QS-R
Flip FlopQ
S
R
LKC
Q
LKC
Q
K
J
J-K
Flip Flop
Q
Q
D
Flip FlopD
LKC
Q
LKC
Q
T
Flip FlopD
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Flip Flops
Implementation of the S-R Flip Flops
QS-R
Flip FlopQ
S
R
LKC
S
R Q
Q S
R Q
Q
• Many different flip flops exist
• Extremely high number of flip flops in a design warrants design
of a good structure
• Not clocked or Master Slave
8 transistor implementations
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Flip Flops
Implementation of the S-R Flip Flops
S
R Q
Q
Clocked S-R flip flop
20 transistor implementation
Output transparent when clock is H
S
RQ
Q
φ
QS-R
Flip FlopQ
S
R
LKC
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Flip Flops
Implementation of the S-R Flip Flops
Clocked S-R flip flop
Clocked Edge-Triggered S-R Master Slave Flip Flop
S
RQ
Q
φ
φφQ Q
RR
S S
SLAVE
FF
MASTER
FF
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Flip FlopsImplementation of the S-R Flip Flops
Clocked Edge-Triggered S-R Master Slave Flip Flop
φφQ Q
RR
S S
SLAVE
FF
MASTER
FF
S
RQ
Q
φ
S
RQ
Q
φ
Master-Slave Edge-triggered Clocked S-R Flip Flop
Large Device Count : 40 transistors
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Flip FlopsD Flip Flop
D
φ
Q
Q D
φ
φ
Q
Q
With static hold5 transistors
6 transistors
Output transparent when in clock is high
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Flip FlopsMaster-Slave Edge-triggered D Flip Flop
Timing Diagram
QD
φ
φφ
φ
MASTER SLAVE
φ
φ
t
CLKTMaster SampleSlave Sample
Output Valid Output Valid
• 12 transistors (but will work with 10)
• Many other simple D Flip-flops exist as well
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Shift Registers
PC PC
SR TR
D Q1Q
• Basic 1-bit dynamic shift register
• Data is stored on parasitic capacitor CP
• CP is generally input capacitance to inverter and omitted from diagram
SR TR
D Q1Q
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Shift Registers
SR TR
D Q1Q
Dynamic Shift Register
• 6 transistor cell
• Must be clocked to retain data
SR
TR
CLKT
D
Q
1Q
Timing Diagram:
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Shift Registers
SR TR
D Q1Q
Dynamic Shift Register
6 transistor cell
SR TR+H
D Q1Q
HDynamic Shift Register with Static Hold
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Shift Registers
SR TR
D Q1Q
Dynamic Shift Register
SR
TR
D Q
Simple redrawing
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Shift RegistersDynamic Shift Register SR
TR
D Q
SR
TR
SR
TR
SR
TR
QD
n=bit Dynamic Shift Register
• FIFO Operation
• Layout so stages can be simply abutted
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Shift RegistersDynamic Shift Register SR
TR
D Q
Bi-directional Dynamic Shift Register
If TL and TR replaced with H•TL and H•TL , have static hold operation
SR
TR
D Q
TL
SL
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Shift RegistersDynamic Shift Register
n-bit Parallel-Load, Parallel-Read Bidirectional Dynamic Shift Register
• Useful for Parallel to Serial and Serial to Parallel Conversion
• Can be put in static hold state if TL and TR replaced with HCTL and
HCTL
SR
TR
D RQ
TL
SL
LQ
SR
TR
TL
SL
SR
TR
TL
SL
SR
TR
TL
SL
1d 2d 3d nd
LX
SR
TR
D RQ
TL
SL
LQ
SR
TR
TL
SL
SR
TR
TL
SL
SR
TR
TL
SL
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Digital Building Blocks
• Combinational Logic
• Sequential Logic
– Shift Registers (stack)
• Array Logic
• Memory Arrays
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Array Logic
• Array logic is often used for sections of logic that may change later in the design or that will be changed for different variants of a product
• FPGA are a special case of array logic
• Can personalize array logic with only one layer of metal
– Very quick turn-around and low incremental costs (as few as one additional mask)
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Array Logic
Will consider only two types
– Gate Array
– Sea of Gates
Variants of the following approach are possible depending upon
process but this will convey the basic concepts
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Array LogicGate Array
• Can add M1 (blue), M2 (purple), contact (M1 to Poly), via (M1 to M2)
• Upper and lower metal shown actually lie above poly and are already
present
• Assume upper M1 is VDD and lower M1 is VSS
• Array can be very large
• Routing channels between segments of array
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Array LogicSea of Gates
• Can add M1 (blue), M2 (purple), contact (M1 to Poly), via (M1 to M2)
• Upper and lower metal shown actually lie above poly and are already
present
• Assume upper M1 is VDD and lower M1 is VSS
• Array can be very large
• Routing channels between segments of array
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Array LogicGate Array
Example: F
GA
B
Via (M1 to M2)
Contact (M1 to diff,Poly)
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Array LogicGate Array
Example: F
GA
B
A
B
FG
VSS
VDD
Via (M1 to M2)
Contact (M1 to diff,Poly)
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Array LogicGate Array
Example: F
GA
B
A
B
FG
VSS
VDD
Via (M1 to M2)
Contact (M1 to diff,Poly)
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Array LogicSea of Gates
Example: F
GA
B
Via (M1 to M2)
Contact (M1 to diff,Poly)
VSS
VDD
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Array LogicSea of Gates
Example: F
GA
B
Via (M1 to M2)
Contact (M1 to diff,Poly)
VSS
VDD
Diffusion Partition
Diffusion Partition
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Array LogicSea of Gates
Example: F
GA
B
Via (M1 to M2)
Contact (M1 to diff,Poly)
A
B
F
G
VSS
VDD
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Digital Building Blocks
• Combinational Logic
• Sequential Logic
– Shift Registers (stack)
• Array Logic
• Memory Arrays
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Typical Memory Structure
MEM
Cell
Sense Amplifier
Column Decoder
Ro
w D
eco
de
r
Memory
Array
VDD
ADR
DATA
n n1
n2
n3
1 2n=n +n
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Row Decoder Architectures
000
001
010
011
100
DDV
DDV
DDV
DDV
DDV
1A 2A 3A
k 1 2 3R = A A A
k 1 2 3R = A A A
Row decoder is Pseudo
n-MOS NOR Gate
Typically n/2 inputs where n is the
address length
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Row Decoder Architectures
000
001
010
011
100
DDV
DDV
DDV
DDV
DDV
1A 2A 3A
Transistor sites typically reserved in the layout for efficient, compact layout
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Mem Cells
Static RAM (SRAM)
• Uses PTL and cross-coupled inverters
• Sizing of “switches” must be strong enough to write to cell
• No static power dissipation in this PTL implementation
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Mem Cells
Static ROM (Mask programmable ROM)
• Site reserved for possible transistor
• Actually programmed with contact to gate and
diffusion
• Can personalize with one or two masks
• Single transistor per bit
• Uses only one column line
Transistor
Present
Transistor
Absent
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Mem CellsEPROM or EEPROM
Control
GateDrainSource
Bulk
n-channel MOSFET
Floating
Gate
Very Thin
Tunneling Oxide
Floating Gate Transistor
• Very thin floating gate
• Charge tunnels onto gate during programming to change VT a lot
• Conceptual diagram only
• Somewhat specialized processing for reliable floating gate devices
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Mem Cells
EPROM or EEPROM
• Floating Gate Transistor
• Programmed by Changing the Threshold Voltage
• Nonvolatile Memory
• Can be electrically programmed with EEPROM
• Limited number of read/write cycles (but enough for
most
applications)
• Uses only one column line
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Mem Cells
DRAM
• Charge stored in small parasitic capacitor
• Very small cells
• Volatile and dynamic
• Special processes to make CP large in very small area
• CP is actually a part of the transistor
• Somewhat tedious architecture (details not shown) needed to
sense very small charge
CP
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End of Lecture 44