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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
1-1
5.0
4.0
3.0
2.0
1.0
0.0Volts
HIGH
LOW
HIGH
LOW
OUTPUT INPUT
Fig. 1-1 An Example of Voltage Ranges for Binary Signals
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
1-2
Memory
Controlunit Datapath
Input/Output
CPU
Fig. 1-2 Block Diagram of a Digital Computer
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
1-3
TABLE 1-1Powers of Two
n 2n n 2n n 2n
0 1 8 256 16 65,5361 2 9 512 17 131,0722 4 10 1,024 18 262,1443 8 11 2,048 19 524,2884 16 12 4,096 20 1,048,5765 32 13 8,192 21 2,097,1526 64 14 16,384 22 4,194,3047 128 15 32,768 23 8,388,608
Table 1-1 Powers of Two
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
1-4
TABLE 1-2Numbers with Different Bases
Decimal(base 10)
Binary(base 2)
Octal(base 8)
Hexadecimal(base 16)
00010203040506070809101112131415
0000000100100011010001010110011110001001101010111100110111101111
00010203040506071011121314151617
0123456789ABCDEF
Table 1-2 Numbers with Different Bases
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
1-5
TABLE 1-3Binary-Coded Decimal (BCD)
DecimalSymbol
BCDDigit
0123456789
0000000100100011010001010110011110001001
Table 1-3 Binary-Coded Decimal (BCD)
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
1-6 TABLE 1-4American Standard Code for Information Interchange (ASCII)
B7B6B5
B4B3B2B1 000 001 010 011 100 101 110 111
0000 NULL DLE SP 0 @ P ` p0001 SOH DC1 ! 1 A Q a q0010 STX DC2 " 2 B R b r0011 ETX DC3 # 3 C S c s0100 EOT DC4 $ 4 D T d t0101 ENQ NAK % 5 E U e u0110 ACK SYN & 6 F V f v0111 BEL ETB 7 G W g w1000 BS CAN ( 8 H X h x1001 HT EM ) 9 I Y i y1010 LF SUB * : J Z j z1011 VT ESC + ; K [ k {1100 FF FS , < L \ l |1101 CR GS - = M ] m }1110 SO RS . > N ^ n ~1111 SI US / ? O _ o DEL
Control Characters:
NULL NULL DLE Data link escapeSOH Start of heading DC1 Device control 1STX Start of text DC2 Device control 2ETX End of text DC3 Device control 3EOT End of transmission DC4 Device control 4ENQ Enquiry NAK Negative acknowledgeACK Acknowledge SYN Synchronous idleBEL Bell ETB End of transmission blockBS Backspace CAN CancelHT Horizontal tab EM End of mediumLF Line feed SUB SubstituteVT Vertical tab ESC EscapeFF Form feed FS File separatorCR Carriage return GS Group separatorSO Shift out RS Record separatorSI Shift in US Unit separatorSP Space DEL Delete
′
Table 1-4 American Standard Code for Information Interchange (ASCII)
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-1
TABLE 2-1Truth Tables for the Three Basic Logic Operations
AND OR NOT
X Y X Y X
0 0 0 0 0 0 0 10 1 0 0 1 1 1 01 0 0 1 0 11 1 1 1 1 1
Z X Yâ‹…= Z X Y+= Z X=
Table 2-1 Truth Tables for the Three Basic Logical Operations
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-2
••X
NOT gate orinverter
XX
YZ = X + Y
(a) Graphic symbols
OR gate
X
YZ = X • Y
AND gate
X 0 0 1 1
Y 0 1 0 1
X • Y 0 0 0 1
0 1 1 1
1 1 0 0
X + Y
(AND)
(NOT)
(OR)
(b) Timing diagram
X
Fig. 2-1 Digital Logic Gates
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-3
ABC
F = A + B + C + D + E + F
(b) Six-input OR gate
ABC
F = ABC
(a) Three-input AND gateDEF
Fig. 2-2 Gates with More than Two Inputs
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-4
TABLE 2-2Truth Table for the Function F � X � YZ
X Y Z F
00001111
00110011
01010101
01001111
Table 2-2 Truth Table for the Function F � X � YZ
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-5
X
••Y
Z
F
Fig. 2-3 Logic Circuit Diagram for F = X + Y ′Z
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-6
TABLE 2-3Basic Identities of Boolean Algebra
1. 2.3. 4.5. 6.7. 8.9.
10. 11. Commutative12. 13. Associative14. 15. Distributive16. 17. DeMorgan’s
X 0+ X= X 1â‹… X=
X 1+ 1= X 0â‹… 0=
X X+ X= X Xâ‹… X=
X X+ 1= X Xâ‹… 0=
X X=
X Y+ Y X+= XY YX=
X Y Z+( )+ X Y+( ) Z+= X YZ( ) XY( )Z=X Y Z+( ) XY XZ+= X YZ+ X Y+( ) X Z+( )=
X Y+ X Yâ‹…= X Yâ‹… X Y+=
Table 2-3 Basic Identities of Boolean Algebra
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-7
TABLE 2-4Truth Tables to Verify DeMorgan’s Theorem
A) X Y X � Y B ) X
0011
0101
0111
1000
0011
0101
1100
1010
1000
X Y+ X YY X Yâ‹…
Table 2-4 Truth Tables to Verify DeMorgan’s Theorem
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-8
TABLE 2-5Truth Table for Boolean Function
X Y Z F
00001111
00110011
01010101
00110101
Table 2-5 Truth Table for Boolean Function
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-9
••
•
X
Y
Z
(a) F = XYZ + XYZ + XZ
(b) F = XY + XZ
•X
Y
F
F
Z
•
••
•
•
Fig. 2-4 Implementation of Boolean Function with Gates
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-10
TABLE 2-6Minterms for Three Variables
X Y ZProductTerm Symbol m0 m1 m2 m3 m4 m5 m6 m7
00001111
00110011
01010101
m0m1m2m3m4m5m6m7
10000000
01000000
00100000
00010000
00001000
00000100
00000010
00000001
X Y ZX YZXYZXYZXY ZXYZXYZXYZ
Table 2-6 Minterms for Three Variables
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-11
TABLE 2-7Maxterms for Three Variables
X Y Z Sum Term Symbol 0 MM 1 M2 M3 M4 M5 M6 M7
00001111
00110011
01010101
M0M1M2M3M4M5M6M7
01111111
10111111
11011111
11101111
11110111
11111011
11111101
11111110
X Y Z+ +X Y Z+ +X Y Z+ +X Y Z+ +X Y Z+ +X Y Z+ +X Y Z+ +X Y Z+ +
Table 2-7 Maxterms for Three Variables
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-12
TABLE 2-8Boolean Functions of Three Variables
(a) X Y Z F F (b) X Y Z E
00001111
00110011
01010101
10100101
01011010
00001111
00110011
01010101
11101100
Table 2-8 Boolean Functions of Three Variables
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-13
Y
XY
X
Y
FZ
Fig. 2-5 Sum-of-Products Implementation
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-14
A
B
C
D
E
(a) AB + C (D + E ) (b) AB + CD + CE
A
B
C
D
C
E
Fig. 2-6 Three-Level and Two-Level Implementation
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-15
X
Z
XYZ
YF
Fig. 2-7 Product-of-Sums Implementation
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-16
m0 m1
m2 m3
(a) (b)
0
1
0 1Y
X
X Y X Y
X YX Y
Fig. 2-8 Two-Variable Map
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-17
0
1
(a) XY
1
0 1Y
X
0
1
(b) X + Y
1
0 1Y
X
11
1
Fig. 2-9 Representation of Functions in the Map
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-18
(a)
m0 m1 m3 m2
m4 m5 m7 m6
YZX
0
00 01
X Y Z X Y Z X Y Z X Y Z
X Y Z X Y Z X Y Z X Y Z
11 10
Y
1X
Z
(b)
Fig. 2-10 Three-Variable Map
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-19
0
1
Y
Z
X 1
00 01 11 10
1
1
YZX XY
XY
1
Fig. 2-11 Map for Example 2-3
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-20
0
1
Y
Z
X
(a)
0
4
00 01 11 10
5
2
YZX
1 3
7 6
XZ
XZ
0
6 4
13
57
2
(b)
Fig. 2-12 Three-Variable Map: Flat and on a Cylinder to Show Adjacent Squares
![Page 884: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/884.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-21
0
1
Y
Z
X
(a)
1
1
00 01 11 10
1
YZX
1
0
1
Y
Z
X
(b)
1
00 01 11 10
1
YZX
1 1
1 1
Y
X
Z
Z
Fig. 2-13 Product Terms Using Four Minterms
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-22
0
1
Y
Z
X
(b) F2(X, Y, Z) = Σm(0, 2, 4, 5, 6) = Z + XY
00 01 11 10
1
YZX
1
1
1 1
0
1
Y
Z
X 1
00 01 11 10
1
YZX
1 1
(a) F1(X, Y, Z) = Σm(3, 4, 6, 7) = YZ + XZ
Fig. 2-14 Maps for Example 2-4
![Page 886: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/886.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-23
0
1
Y
Z
X 1
00 01 11 10YZ
X
11
1 1
Fig. 2-15 Σm(1, 3, 4, 5, 6)=F X Y Z, ,( )
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-24
0
1
Y
Z
X
00 01 11 10
1
YZX
1
1
1
1
Fig. 2-16 F X Y Z, ,( ) Σm 1 2 3 5 7, , , ,( )=
![Page 888: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/888.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-25
(a) (b)
00
01
00 01YZ
WX
m0 m1
m4 m5
m3 m2
m7 m6
m12 m13
m8 m9
m15 m14
m11 m10
Y
Z
W
11 10
11
10
X
Fig. 2-17 Four-Variable Map
![Page 889: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/889.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-26
(a)
00
01
00 01YZ
WX
Y
Z
W
11 10
11
10
X
0 1 3 2
4 5 7 6
8 9 1011
12 13 1415
XZ
02
8 10
1 3911
X Z
(b)
Fig. 2-18 Four-Variable Map: Flat and on a Torus to Show Adjacencies
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-27
00
01
00 01YZ
WX
Y
Z
W
11 10
11
10
X
1 1 1
1 1 1
1 1
1 1 1
Fig. 2-19 Map for Example 2-5: F = Y + WZ + XZ
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-28
00
01
00 01CD
AB
C
D
A
11 10
11
10
B
1 1 1
1
1 1 1
Fig. 2-20 Map for Example 2-6: F = BD + BC + ACD
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-29
00
01
00 01CD
AB
C
D
A
11 10
11
10
B
1
1
1
11 1
1 1
Fig. 2-21 Prime Implicants for Example 2-7: AD, BD, and AB
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-30
00
01
00 01CD
AB
C
D
A
11 10
11
10
B
1
1
1
1 1
1
1
00
01
00 01CD
AB
C
D
A
11 10
11
10
B
1
1
1
1 1
1
1
(a) Plotting the minterms (b) Essential prime implicants
Fig. 2-22 Simplification with Prime Implicants in Example 2-8
![Page 894: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/894.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-31
1 2
3
00
01
00 01CD
AB
C
D
A
11 10
11
10
B
1
1
1
1
1
1
11
1
Fig. 2-23 Map for Example 2-9
![Page 895: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/895.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-32
00
01
00 01CD
AB
C
D
A
11 10
11
10
B
1 01 1
1 00 0
0 00 0
1 01 1
Fig. 2-24 Map for Example 2-10: F = (A + B) (C + D) (B + D)
![Page 896: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/896.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-33
00
01
00 01CD
AB
C
D
A
11 10
11
10
B
X 00
01
00 01CD
AB
C
D
A
11 10
11
10
B
1 1 X X 1 1 X
0 X 1 0 0 X 1 0
0 0 1 0 0 0 1 0
0 0 1 0 0 0 1 0
(b) F = CD + AD(a) F = CD + AB
Fig. 2-25 Example with Don't-Care Conditions
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-34 Graphics Symbols
Name Distinctiveshape
Rectangularshape
Algebraicequation
Truthtable
X
YF F
X
Y
AND F = XY
X Y F0 0 00 1 01 0 01 1 1
&
X
YF F
X
Y
OR F = X + Y
X Y F0 0 00 1 11 0 11 1 1
≥1
••X F • FXNOT(inverter) F = X
X F0 11 0
1
X F FXBuffer F = XX F0 01 1
1
•X
YF F
X
Y
NAND F = X • Y
X Y F0 0 10 1 11 0 11 1 0
&
•X
YF • F
X
Y
NOR F = X + Y
X Y F0 0 10 1 01 0 01 1 0
≥1
X
YF F
X
Y
Exclusive–OR(XOR)
F = XY + XY= X Y
X Y F0 0 00 1 11 0 11 1 0
=1
•X
YF • F
X
Y
Exclusive–NOR(XNOR)
F = XY + XY= X Y
X Y F0 0 10 1 01 0 01 1 1
=1
•
Fig. 2-26 Digital Logic Gates
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-35
•• •NOT X X X X
Y• •AND
XXY = XY
•
• •OR
X
Y
X Y = X + Y
Fig. 2-27 Logical Operations with NAND Gates
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-36
(a) AND - NOT
Y ••X
ZXYZ
•X X
(b) NOT – OR
YX
Z
• XX
(c) NOT
•••X + Y + Z = XYZ
Fig. 2-28 Alternative Graphics Symbols for NAND and NOT Gates
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-37
A
B
C
D
F
••
••
(c)
(b)
A
B
C
D
F
•
•
••
A
B
C
D
F
(a)
Fig. 2-29 Three Ways to Implement F = AB + CD
![Page 901: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/901.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-38
0
1
Y
Z
X 1
00 01 11 10
1
1
YZX
11
1F = XY + XY + Z
(a)
••
•
•
•••
Z
X
Y
X
YF
(b)
•
•
Z
X
Y
X
YF•
(c)
Fig. 2-30 Solution to Example 2-12
![Page 902: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/902.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-39
C
D
B
A
B
C
F
(a) AND – OR gates
C
D
B
A
B
C
F
(b) NAND gates
•••
•
•••
Fig. 2-31 Implementing F = A (CD + B) + BC
![Page 903: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/903.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-40
A
B
A
B
C
D
E
F
(a) AND – OR gates
A
B
A
B
C
D
E
F
(b) NAND gates
X
••
•
•
•
••
•
••
•••
•
Fig. 2-32 Implementing F A B AB+( )E C D+( )=
![Page 904: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/904.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-41
•••Inverter X X X X
Y•OR
XX + Y = X + Y
•
•AND
X
Y
X + Y = XY
•
•
Fig. 2-33 Logic Operations with NOR Gates
![Page 905: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/905.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-42
Y ••
(a) OR – NOT
XX + Y + Z
ZY
(b) NOT – AND
XX Y Z = X + Y + Z
Z
•••
Fig. 2-34 Two Graphic Symbols for NOR Gate
![Page 906: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/906.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-43
••
•
E
A
B
C
DF
•••
Fig. 2-35 Implementing F = (A + B) (C + D) E with NOR Gates
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-44
A
B
C
D
E
FY
••
•
•
•
• ••
••
A
B••
Fig. 2-36 Implementing F = (AB + AB) E (C + D) with NOR Gates
![Page 908: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/908.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-45
•
•
••
••
•X
Y
F = X Y
•
•
Fig. 2-37 Exclusive-OR Constructed with NAND Gates
![Page 909: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/909.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-46
(b) A B C D
00
01
00 01CD
AB
C
D
A
11 10
11
10
B
1
1
1
1
1
1
1
10
1
Y
Z
X
(a) X Y Z
1
00 01 11 10
1
YZX
1
1
Fig. 2-38 Maps for Multiple-Variable Odd Functions
![Page 910: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/910.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-47
TABLE 2-9Truth Table for an Even Parity Generator
Three-Bit Message Parity Bit
X Y Z P
00001111
00110011
01010101
01101001
Table 2-9 Truth Table for an Even Parity Generator
![Page 911: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/911.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-48
X
Y
ZP
X
Y
ZC
P
(a) P = X Y Z (b) C = X Y Z P
Fig. 2-39 Multiple-Input Odd Functions
![Page 912: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/912.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-49
••IN OUT
IN
OUT tPHL tPLH
tpd = max (tPHL, tPLH)
Fig. 2-40 Propagation Delay for an Inverter
![Page 913: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/913.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-50
A
B
A B:
No Delay(ND)
TransportDelay (TD)
InertialDelay (ID)
Time (ns)0 42 6 8 10 12 14 16
a b c d e
Fig. 2-41 Examples of Behavior of Transport and Inertial Delays
![Page 914: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/914.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-51
(a) Positive logic
Signalvalue
Logicvalue
H 1
L 0
(b) Negative logic
Signalvalue
Logicvalue
H 0
L 1
Fig. 2-42 Signal Assignment and Logic Polarity
![Page 915: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/915.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-52
X
YZ
X Y ZL L LL H LH L LH H H
CMOSGate
(a) Truth table with H and L
(b) Gate block diagram
X
YZ
X Y Z0 0 00 1 01 0 01 1 1
(c) Truth table for positive logic
(d) Positive-logic AND gate
X Y Z1 1 11 0 10 1 10 0 0
(e) Truth table for negative logic
(f) Negative-logic OR gate
X
YZ
Fig. 2-43 Demonstration of Positive and Negative Logic
![Page 916: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/916.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-53
X Y
(a)
TG
C
••
C
X Y
C
(d)
•
•
•TG
(b)
X YC = 1 and C = 0
• •
X YC = 0 and C = 1
• •
(c)
Fig. 2-44 Transmission Gate (TG)
![Page 917: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/917.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-54
(b)
C
A
F••• • •
TG0
TG1
•
••
•
(a)
A
0
0
1
1
C
0
1
0
1
TG1
No path
Path
No path
Path
TG0
Path
No path
Path
No path
F
0
1
1
0
Fig. 2-45 Transmission Gate Exclusive-OR
![Page 918: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/918.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-1
Combinationalcircuit
n inputs m outputs•••
•••
Fig. 3-1 Block Diagram of Combinational Circuit
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
Fig. 3-2 Example of Design Hierarchy and Reusable Blocks
B
X0X1X2X3X4X5X6X7X8
ZO0dd
function
9-Input
(a) Symbol for circuit
3-Inputodd
function
A0
A1
A2
BO
3-Inputodd
function
A0
A1
A2
BO
3-Inputodd
function
A0
A1
A2
BO
3-Inputodd
function
A0
A1
A2
O
X0
X1
X2
X3
X4
X5
X6
X7
X8
ZO
(b) Circuit as interconnected 3-input odd
BO
A0A1
A2
(c) 3-input odd function circuit asinterconnected exclusive-OR
(d) Exclusive-OR block as interconnected
function blocks
blocks
NANDs
••
••
3-2
![Page 920: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/920.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-3
3-inputodd function
XOR XOR
-NAND
3-inputodd function
XOR XOR
3-inputodd function
XOR XOR
3-inputodd function
XOR XOR
9-inputodd function
(a)
9-inputodd function
3-inputodd function
XOR
(b)
Fig. 3-3 Diagrams Representing the Hierarchy for Figure 3-2
![Page 921: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/921.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-4
HDL Descriptionof Circuit
Electronic, Speed,and Area Constraints
Translation
IntermediateRepresentation
Optimization/Pre-optimization Technology Mapping
Technology Library
Netlist
Fig. 3-4 High-Level Flow for Synthesis Tool
![Page 922: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/922.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-5
A
B
C
D
••
•
•
•
•
•
T1
T2
T3
T4
T5
F2
F1
Fig. 3-5 Logic Diagram for Analysis Example
![Page 923: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/923.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-6
X
••
•
••
•
•
••
•
YZ
T1
T2T3
S
C•
Fig. 3-6 Logic Diagram for Binary Adder
![Page 924: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/924.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-7
TABLE 3-1Truth Table for Binary Adder
X Y Z C T1 T2 T3 S
00001111
00110011
01010101
00010111
11101000
00000001
01111111
01101000
01101001
C
Table 3-1 Truth Table for Binary Adder
![Page 925: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/925.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-8
OR3
AND3
OR3
AND2
AND2
AND2
INV
AND2
OR2
X
Y
C
S
Z
Fig. 3-7 Xilinx Foundation Schematic for Binary Adder in Figure 3-6
![Page 926: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/926.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-9
20ns0.0 40ns 60ns 80ns 100ns 120ns 140ns
ii
i
oo
XYZ
SC
CsCsCs
Fig. 3-8 Waveforms for the Binary Adder Schematic in Figure 3-7
![Page 927: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/927.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-10
••X
Y
•Z
••
F
(c) Logic diagram
•
(b) Map F = XY + XZ
0
1
Y
Z
X
1
00 01 11 10
1
YZX
1
X Y Z F0 0 0 10 0 1 10 1 0 10 1 1 01 0 0 01 0 1 01 1 0 01 1 1 0
(a) Truth table
Fig. 3-9 Solution to Example 3-1
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-11
TABLE 3-2Truth Table for Code Converter Example
DecimalDigit
InputBCD
OutputExcess-3
A B C D W X Y Z
0123456789
0000000011
0000111100
0011001100
0101010101
0000011111
0111100001
1001100110
1010101010
Table 3-2 Truth Table for Code Converter Example
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-12
00
01
00 01CD
AB
C
D
A
11 10
11
10
B
1 1 1
1
X X X X
1 X X
X = BC + BD + BCD
00
01
00 01CD
AB
C
D
A
11 10
11
10
B1 1 1
X X X X
1 1 X X
W = A + BC + BD
00
01
00 01CD
AB
C
D
A
11 10
11
10
B1
X X X X
1 X X
1
11
Y = CD + CD
00
01
00 01CD
AB
C
D
A
11 10
11
10
B
1 1
1
X X X X
1 X X
Z = D
1
Fig. 3-10 Maps for BCD-to-Excess-3 Code Converter
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-13
••
•
•
•
•
•
••
•
•
A
B
C
D
W
X
Y
Z
•
•
Fig. 3-11 Logic Diagram of BCD-to-Excess-3 Code Converter
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-14
(b) Numeric designation for display(a) Segment designation
a
f b
e cg
d
Fig. 3-12 Seven-Segment Display
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-15
BCD Input Seven-Segment Decoder
A B C D a b c d e f g
0000000011
0000111100
0011001100
0101010101
1011011111
1111100111
1101111111
1011011011
1010001010
1000111011
0011111011
All other inputs 0 0 0 0 0 0 0
TABLE 3-3Truth Table for BCD–to–Seven-Segment Decoder
Table 3-3 Truth Table for BCD–to–Seven-Segment Decoder
![Page 933: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/933.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-16
••
•
D6 = A2 A1 A0
D5 = A2 A1 A0
D4 = A2 A1 A0
D3 = A2 A1 A0
D2 = A2 A1 A0
D1 = A2 A1 A0
D0 = A2 A1 A0
•
•
•
•
••
•
•
•
•
•
••
•
• •
••
D7 = A2 A1 A0
A0
A1
A2
•
•
•
Fig. 3-13 3-to-8-Line Decoder
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(b) Truth table
E
00001
A1
0011X
A0
0101X
D0
01111
D1
10111
D2
11011
D3
11101
(a) Logic diagram
D0
D1
D2
D3
A0
A1
E
D0 = E A1 A0
D1 = E A1 A0
D2 = E A1 A0
D3 = E A1 A0
(c) Logic Equations
•
•
••
•
•
••
•
••
•
•
•
•
•
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-17
Fig. 3-14 A 2–to–4-Line Decoder
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-18
TABLE 3-4Truth Table for 3–to–8-Line Decoder
Inputs Outputs
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
00001111
00110011
01010101
00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000
Table 3-4 Truth Table for 3–to–8-Line Decoder
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-19
••
••
•
A0
A1
A2
2–to–4Decoder
20
21
1
2
3
0
Enable
D1
D2
D3
D0
20
21
1
2
3
0
Enable
D5
D6
D7
D4
2–to–4Decoder
Fig. 3-15 A 3-to-8 Decoder Constructed with Two 2-to-4 Decoders
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-20
Z
Y
X
3–to–8Decoder
20
21
22
S
C
•
01
2
3
4
5
6
7
Fig. 3-16 Implementing a Binary Adder Using a Decoder
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-21
TABLE 3-5Truth Table for Octal–to–Binary Encoder
Inputs Outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000
00001111
00110011
01010101
Table 3-5 Truth Table for Octal–to–Binary Encoder
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-22
Inputs Outputs
D3 D2 D1 D0 A1 A0 V
00001
0001X
001XX
01XXX
X0011
X0101
01111
TABLE 3-6Truth Table of Priority Encoder
Table 3-6 Truth Table of Priority Encoder
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-23
00
01
00 01
D1
D3
11 10
11
10
1 1 1
1 1
A1 = D2 + D3
D2
D0
1
1 1 11
1 1
00
01
00 01
D1
D3
11 10
11
10 1 1
D2
D0
1 1 11
1 1
1 1
A0 = D3 + D1D2
D2D0D3D2
D1D0D3D2
XX
Fig. 3-17 Maps for Priority Encoder
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-24
••
D3
D2
D1
D0
A 0
A 1
V
•
•
•
••
Fig. 3-18 Logic Diagram of a 4-Input Priority Encoder
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-25
S0
S1
D0
D1
D2
D3
•
•
•
•
••
•
•
Function table
S1
0011
S0
0101
Y
D0D1D2D3
Y
Fig. 3-19 4-to-1-Line Multiplexer
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-26
••
•
S0
S1
D0
D1
D2
D3
Y
TG(S0 = 0)
TG(S0 = 1)
TG(S0 = 0)
TG(S0 = 1)
TG(S1 = 1)
TG(S1 = 0)
•
• •
•
• •
•
• •
•
•
• •
•
•
•
•
•
•
Fig. 3-20 4-to-1-Line Multiplexer with Transmission Gates
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-27
A0
A1
A2
A3
B0
B1
B2
B3
S(select)
E(enable)
Y0
Y1
Y2
Y3
Function table
E011
SX01
Output YAll 0'sSelect ASelect B
••
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fig. 3-21 Quadruple 2-to-1-Line Multiplexer
![Page 945: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/945.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-28
4 x 1 MUX
Y
X
Z
0
1
0
1
2
3
F
S0
S1
(b) Multiplexer implementation(a) Truth table
X00001111
Y00110011
Z01010101
F01100011
F = Z
F = 0
F = 1
F = Z Z
Fig. 3-22 Implementing a Boolean Function with a Multiplexer
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-29
A0000000011111111
B0000111100001111
C0011001100110011
D0101010101010101
F = D
F = 0
F = D
F0101100000011111
F = 0
F = D
F = 1
F = 1
F = D • •
••
•
•
C
B
A
D
0
1
0
1
2
3
4
5
6
7
S0
F
S1
S2
8 x 1 MUX
Fig. 3-23 Implementing a Four-Input Function with a Multiplexer
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-30
E
••
••
•
•
••
••
••
S0
S1
D0
D1
D2
D3
Fig. 3-24 1-to-4-Line Demultiplexer
![Page 948: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/948.jpg)
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3-31
Inputs Outputs
X Y C S
0011
0101
0001
0110
TABLE 3-7Truth Table of Half Adder
Table 3-7 Truth Table of Half Adder
![Page 949: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/949.jpg)
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3-32
X ••Y
S
C
Fig. 3-25 Logic Diagram of Half Adder
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3-33
Inputs Outputs
X Y Z C S
00001111
00110011
01010101
00010111
01101001
TABLE 3-8Truth Table of Full Adder
Table 3-8 Truth Table of Full Adder
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-34
S = X YZ + XYZ + XY Z + XY Z = X Y Z
0
1
Y
Z
X
00 01 11 10
1
YZX
1
1 1
0
1
Y
Z
X
00 01 11 10YZ
X
1
1 1 1
C = XY + XZ + YZ = XY + Z ( XY + XY ) = XY + Z ( X Y )
Fig. 3-26 Maps for Full Adder
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3-35
Half adder
••
•
•
Half adder
X
Y
Z
S
C
Fig. 3-27 Logic Diagram of Full Adder
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3-36
B3 A3
FA
S3C4
B2 A2
FA
S2
B1 A1
FA
S1
B0 A0
FA
S0
C3 C2 C1C0
Fig. 3-28 4-Bit Ripple Carry Adder
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-37•
••
B A
S G P C
B3 A3 B2 A2 B1 A1 B0 A0
PFA PFA PFA PFA
• • •
S3 G3 P3 C3 S2 G2 P2 C2 S1 G1 P1 C1 S0 G0 P0
C0•Ripple Carry
C4
G3 P3 C3 G2 P2 C2 G1 P1 C1 G0 P0
C0
Carry Lookahead
G0-3
P0-3
•
•
•
•
•
•
•
•
•
• •
•
•
•
•
•
•
•
• ••
••
•
(a)
(b)
Fig. 3-29 Development of a Carry Lookahead Adder
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3-38
• • • •
• • • •
A B
Binary adder Binary subtractor
Selective2's complementer
Quadruple 2-to-1multiplexer
Result
Borrow
Complement
S0 1Subtract/Add
Fig. 3-30 Block Diagram of Binary Adder-Subtractor
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3-39
FA FA FA FA
S
B3 A3 B2 A2 B1 A1 B0 A0
C3 C2 C1 C0
C4 S3 S2 S1 S0
• • • •
Fig. 3-31 Adder-Subtractor Circuit
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-40
DecimalSigned 2’sComplement
Signed 1’s Complement
SignedMagnitude
�7�6�5�4�3�2�1�0�0�1�2�3�4�5�6�7�8
01110110010101000011001000010000—11111110110111001011101010011000
0111011001010100001100100001000011111110110111001011101010011000—
0111011001010100001100100001000010001001101010111100110111101111—
TABLE 3-9Signed Binary Numbers
Table 3-9 Signed Binary Numbers
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3-41
•
Cn–1
CnC
V
n-bit Adder/Subtractor
Fig. 3-32 Overflow Detection for Addition and Subtraction
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3-42
C3 C2 C1 C0
A0B0A0B1
A1B1 A1B0
A1 A0
B1 B0
C0C3
•
•
HA HA
C2 C1
A0
A1
B1 B0
B1 B0
Fig. 3-33 A 2-Bit by 2-Bit Binary Multiplier
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3-43
Sum
Addend Augend4-bit adder
Sum
Addend Augend
4-bit adder
A0
A1
A2
C6 C5 C4 C3 C2 C1 C0
B0B1B2B3
B0B1B2B3
0
B0B1B2B3
Carryoutput
Carryoutput
••
•
•
•
•
•
•
•
Fig. 3-34 A 4-Bit by 3-Bit Binary Multiplier
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3-44
•
•
•
••
••
Outputcarry
C
0
Addend Augend
Inputcarry
4-bit binary adder
Z3 Z2 Z1 Z0
K
4-bit binary adder
S3 S2 S1 S0
BCD sum
Fig. 3-35 Block Diagram of BCD Adder
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-45
-- 2-to-4 Line Decoder: Structural VHDL Description -- 1-- (See Figure 3-14 for logic diagram) -- 2library ieee, lcdf_vhdl; -- 3use ieee.std_logic_1164.all, lcdf_vhdl.func_prims.all; 4entity decoder_2_to_4 is --
--56port(E_n, A0, A1: in std_logic; --
D0_n, D1_n, D2_n, D3_n: out std_logic); -- 7end decoder_2_to_4; -- 8
-- 9architecture structural_1 of decoder_2_to_4 is -- 10
component NOT1 -- 11port(in1: in std_logic; -- 12
out1: out std_logic); -- 13end component; 14component NAND3 --
--15
port(in1, in2, in3: in std_logic; -- 16out1: out std_logic); -- 17
end component; 18signal E, A0_n, A1_n: std_logic; --
--19
begin -- 20g0: NOT1 port map (in1 => A0, out1 => A0_n); -- 21g1: NOT1 port map (in1 => A1, out1 => A1_n); -- 22g2: NOT1 port map (in1 => E_n, out1 => E); -- 23g3: NAND3 port map (in1 => A0_n, in2 => A1_n, -- 24
in3 => E, out1 => D0_n); -- 25g4: NAND3 port map (in1 => A0, in2 => A1_n, -- 26
in3 => E, out1 => D1_n); -- 27g5: NAND3 port map (in1 => A0_n, in2 => A1, -- 28
in3 => E, out1 => D2_n); -- 29g6: NAND3 port map (in1 => A0, in2 => A1, -- 30
in3 => E, out1 => D3_n); -- 31end structural_1; -- 32
Fig. 3-36 Structural VHDL Description of a 2-to-4 Line Decoder
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-46-- 4-to-1 Line Multiplexer: Structural VHDL Description -- 1-- (See Figure 3-19 for logic diagram) -- 2library ieee, lcdf_vhdl; -- 3use ieee.std_logic_1164.all, lcdf_vhdl.func_prims.all; 4entity multiplexer_4_to_1_st is --
--5
port(S: in std_logic_vector(0 to 1); -- 6D: in std_logic_vector(0 to 3); -- 7Y: out std_logic); -- 8
end multiplexer_4_to_1_st; -- 9-- 10
architecture structural_2 of multiplexer_4_to_1_st is -- 11component NOT1 -- 12
port(in1: in std_logic; -- 13out1: out std_logic); -- 14
end component; 15component AND3 --
--16
port(in1, in2, in3: in std_logic; 17out1: out std_logic); --
--18
end component; 19component OR4 --
--20
port(in1, in2, in3, in4: in std_logic; -- 21out1: out std_logic); -- 22
end component; 23signal S_n: std_logic_vector(0 to 1); --
--24
signal N: std_logic_vector(0 to 3); -- 25begin -- 26
g0: NOT1 port map (S(0), S_n(0)); -- 27g1: NOT1 port map (S(1), S_n(1)); -- 28g2: AND3 port map (S_n(1), S_n(0), D0), N(0)); -- 29g3: AND3 port map (S_n(1), S(0), D(1), N(1)); -- 30g4: AND3 port map (S(1), S_n(0), D(2), N(2)); -- 31g5: AND3 port map (S(1), S(0), D(3), N(3)); -- 32g6: OR4 port map (N(0), N(1), N(2), N(3), Y); -- 33
end structural_2; -- 34
Fig. 3-37 Structural VHDL Description of a 4-to-1 Line Multiplexer
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3-47
-- 2-to-4 Line Decoder: Dataflow VHDL Description -- 1-- (See Figure 3-14 for logic diagram) -- 2Use library, use, and entity entries from 2_to_4_decoder_st; -- 3
-- 4architecture dataflow_1 of decoder_2_to_4 is -- 5
-- 6signal A0_n, A1_n: std_logic; -- 7begin -- 8
A0_n <= not A0; -- 9A1_n <= not A1; -- 10E <= not E_n; -- 11D0_n <= not ( A0_n and A1_n and E); -- 12D1_n <= not ( A0 and A1_n and E); -- 13D2_n <= not ( A0_n and A1 and E); -- 14D3_n <= not ( A0 and A1 and E); -- 15
end dataflow_1; -- 16
Fig. 3-38 Dataflow VHDL Description of a 2-to-4 Line Decoder
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-48
-- 4-to-1 Line Mux: Conditional Dataflow VHDL Description -- 1-- Using When-Else (See Figure 3-19 for function table) -- 2library ieee; -- 3use ieee.std_logic_1164.all; 4entity multiplexer_4_to_1_we is --
--5
port (S : in std_logic_vector(1 downto 0); -- 6 D : in std_logic_vector(0 to 3); -- 7
Y : out std_logic); -- 8end multiplexer_4_to_1_we; -- 9
-- 10architecture function_table of multiplexer_4_to_1_we is -- 11begin -- 12
Y <= D(0) when S = "00" else -- 13D(1) when S = "01" else -- 14D(2) when S = "10" else -- 15D(3) when S = "11" else -- 16'X'; -- 17
end function_table; -- 18
Fig. 3-39 Conditional Dataflow VHDL Description of a 4-to-1 Line Multiplexer Using When-Else
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-49
--4-to-1 Line Mux: Conditional Dataflow VHDL Description -- 1Using When-Else (See Figure 3-14 for logic equations) -- 2library ieee; -- 3use ieee.std_logic_1164.all; 4entity multiplexer_4_to_1_ws is --
--5
port (S : in std_logic_vector(1 downto 0); -- 6 D : in std_logic_vector(0 to 3); -- 7 Y : out std_logic); -- 8
end multiplexer_4_to_1_ws; -- 9-- 10
architecture function_table_ws of multiplexer_4_to_1_ws is -- 11begin -- 12
with S select -- 13Y <= D(0) when "00", -- 14
D(1) when "01", -- 15D(2) when "10", -- 16D(3) when "11", -- 17'X' when others; -- 18
end function_table_ws; -- 19
Fig. 3-40 Conditional Dataflow VHDL Description of a 4-to-1 Line Multiplexer Using With-Select
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-50 -- 4-bit Adder: Hierarchical Dataflow/Structural-- (See Figures 3-27 and 3-28 for logic diagrams)library ieee;use ieee.std_logic_1164.all;entity half_adder is
port (x, y : in std_logic; s, c : out std_logic);
end half_adder;
architecture dataflow_3 of half_adder isbegin
s <= x xor y;c <= x and y;
end dataflow_3;
library ieee;use ieee.std_logic_1164.all;entity full_adder is
port (x, y, z : in std_logic; s, c : out std_logic);
end full_adder;
architecture struc_dataflow_3 of full_adder iscomponent half_adder
port(x, y : in std_logic;s, c : out std_logic);
end component;signal hs, hc, tc: std_logic;begin
HA1: half_adderport map (x, y, hs, hc);
HA2: half_adderport map (hs, z, s, tc);
c <= tc or hc;end struc_dataflow_3;
library ieee;use ieee.std_logic_1164.all;entity adder_4 is
port(B, A : in std_logic_vector(3 downto 0);C0 :
in std_logic;S : out std_logic_vector(3 downto 0);C4: out std_logic);
end adder_4;
Fig. 3-41 Hierarchical Structural/Dataflow Description of a 4-Bit Adder
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3-51
architecture structural_4 of adder_4 iscomponent full_adder
port(x, y, z : in std_logic;s, c : out std_logic);
end component;signal C: std_logic_vector(4 downto 0);begin
Bit0: full_adderport map (B(0), A(0), C(0), S(0), C(1));
Bit1: full_adder port map (B(1), A(1), C(1), S(1), C(2));
Bit2: full_adderport map (B(2), A(2), C(2), S(2), C(3));
Bit3: full_adderport map (B(3), A(3), C(3), S(3), C(4));
C(0) <= C0;C4 <= C(4);
end structural_4;
Fig. 3-42 Hierarchical Structural/Dataflow Description of a 4-Bit Adder (Continued)
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3-52
-- 4-bit Adder: Behavioral Descriptionlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity adder_4_b isport(B, A : in std_logic_vector(3 downto 0);
C0 : in std_logic;S : out std_logic_vector(3 downto 0);C4: out std_logic);
end adder_4_b;
architecture behavioral of adder_4_b issignal sum : std_logic_vector(4 downto 0);begin
sum <= ('0' & A) + ('0' & B) + ("0000" & C0);C4 <= sum(4);S <= sum(3 downto 0);
end behavioral;
Fig. 3-43 Behavioral Description of a 4-Bit Adder
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3-53
// 2-to-4 Line Decoder: Structural Verilog Description // 1// (See Figure 3-14 for logic diagram) // 2module decoder_2_to_4_st_v(E_n, A0, A1, D0_n, D1_n, D2_n, D3_n);// 3
input E_n, A0, A1; // 4output D0_n, D1_n, D2_n, D3_n; // 5
// 6wire A0_n, A1_n; // 7not // 8
go(A0_n, A0), // 9g1(A1_n, A1); // 10g2(E, E_n); // 11
// 12nand // 13
g3(D0_n, A0_n, A1_n, E), // 14g4(D1_n, A0, A1_n, E), // 15g5(D2_n, A0_n, A1, E), // 16g6(D3_n, A0,A1, E); // 17
// 18endmodule // 19
Fig. 3-44 Structural Verilog Description of a 2-to-4 Line Decoder
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-54
// 4-to-1 Line Multiplexer: Structural Verilog Description // 1// (See Figure 3-19 for logic diagram) // 2module multiplexer_4_to_1_st_v(S, D, Y); // 3
input [1:0] S; // 4input [3:0] D; // 5output Y; // 6
// 7wire [1:0] not_S; // 8wire [0:3] N; // 9
// 10not // 11
gn0(not_S[0], S[0]), // 12 gn1(not_S[1], S[1]); // 13
// 14 and // 15
g0(N[0], not_S[1], not_S[0], D[0]), // 16g1(N[1], not_S[1], S[0], D[1]), // 17g2(N[2], S[1], not_S[0], D[2]), // 18g3(N[3], S[1], S[0], D[3]); // 19
// 20or go(Y, N[0], N[1], N[2], N[3]); // 21
// 22endmodule // 23
Fig. 3-45 Structural Verilog Description of a 4-to-1 Line Multiplexer
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-55
// 2-to-4 Line Decoder: Dataflow Verilog Description // 1// (See Figure 3-14 for logic diagram) // 2module decoder_2_to_4_df_v(E_n, A0, A1, D0_n, D1_n, D2_n, D3_n); // 3
input E_n, A0, A1; // 4output D0_n, D1_n, D2_n, D3_n; // 5
// 6assign D0_n = ~(~E_n & ~A1 & ~A0); // 7assign D1_n = ~(~E_n & ~A1 & A0); // 8assign D2_n = ~(~E_n & A1 & ~A0); // 9assign D3_n = ~(~E_n & A1 & A0); // 10
// 11endmodule // 12
Fig. 3-46 Dataflow Verilog Description of a 2-to-4 Line Decoder
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3-56
TABLE 3-10Bitwise Verilog Operators
Operation Operator
~&|^
^~ or ~^
Bitwise NOTBitwise ANDBitwise OR
Bitwise XORBitwise XNOR
Table 3-10 Bitwise Verilog Operators
![Page 974: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/974.jpg)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-57
// 4-to-1 Line Multiplexer: Dataflow Verilog Description// (See Figure 3-19 for logic diagram)module multiplexer_4_to_1_df_v(S, D, Y);
input [1:0] S;input [3:0] D;output Y;
assign Y = (~ S[1] & ~ S[0] & D[0])| (~ S[1] & S[0] & D[1])| (S[1] & ~ S[0] & D[2]) | (S[1] & S[0] & D[3]);
endmodule
Fig. 3-47 Dataflow Verilog Description of a 4-to-1 Line Multiplexer Using a Boolean Equation
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-58
// 4-to-1 Line Multiplexer: Dataflow Verilog Description// (See Figure 3-19 for function table)module multiplexer_4_to_1_cf_v(S, D, Y);
input [1:0] S;input [3:0] D;output Y;
assign Y = (S == 2'b00) ? D[0] :(S == 2'b01) ? D[1] :(S == 2'b10) ? D[2] :(S == 2'b11) ? D[3] : 1'bx ;
endmodule
Fig. 3-48 Conditional Dataflow Verilog Description of a 4-to-1 Line Multiplexer Using Combinations
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3-59
// 4-to-1 Line Multiplexer: Dataflow Verilog Description// (See Figure 3-19 for logic diagram)module multiplexer_4_to_1_tf_v(S, D, Y);
input [1:0] S;input [3:0] D;output Y;
assign Y = S[1] ? (S[0] ? D[3] : D[2]) :(S[0] ? D[1] : D[0]) ;
endmodule
Fig. 3-49 Conditional Dataflow Verilog Description of a 4-to-1 Line Multiplexer Using Binary Decisions
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
3-60 // 4-bit Adder: Hierarchical Dataflow/Structural// (See Figures 3-27 and 3-28 for logic diagrams)
module half_adder_v(x, y, s, c);input x, y;output s, c;
assign s = x ^ y;assign c = x & y;
endmodule
module full_adder_v(x, y, z, s, c);input x, y, z;output s, c;
wire hs, hc, tc;
half_adder_v HA1(x, y, hs, hc),HA2(hs, z, s, tc);
assign c = tc | hc;
endmodule
module adder_4_v(B, A, C0, S, C4);input[3:0] B, A;input C0;output[3:0] S;output C4;
wire[3:1] C;
full_adder_v Bit0(B[0], A[0], C0, S[0], C[1]),Bit1(B[1], A[1], C[1], S[1], C[2]),Bit2(B[2], A[2], C[2], S[2], C[3]),Bit3(B[3], A[3], C[3], S[3], C4);
endmodule
Fig. 3-50 Hierarchical Dataflow/Structural Description of a 4-Bit Adder
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3-61
// 4-bit Adder : Behavioral Verilog Description
module adder_ 4_b_v(A, B, C0, S, C4);
input [3:0] A, B;
input C0;
output [3:0] S ;
output C4;
assign {C4, S } = A + B + C0;
endmodule
Fig. 3-51 Behavioral Description of a 4-Bit Adder Using Verilog
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
4-1
Inputs
Combinationalcircuit
Nextstate Storage
elements
Outputs
Presentstate
Fig. 4-1 Block Diagram of a Sequential Circuit
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
4-2
•tpd
(b)
0 0
•tpd
(c)
1 1
tpd
(a)
•••
(d)
tpd12 tpd
12
Fig. 4-2 Logic Structures for Storing Information
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
4-3
(a) Block diagram
(b) Timing diagram of clock pulses
InputsCombinational
circuit
Clock pulses
Flip-flops
Outputs
Fig. 4-3 Synchronous Clocked Sequential Circuit
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
4-4
(a) Logic diagram
••
•
•
•
R (Reset)
S (Set)
Q
Q
(b) Function table
S
1
0
0
0
1
R
0
0
1
0
1
Q
1
1
0
0
0
Q
0
0
1
1
0
Set state
Reset state
Undefined
Fig. 4-4 SR Latch with NOR Gates
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4-5
10ns0.0 20ns 30ns 40ns 50ns 60ns 70ns
ii
oo
SRQQ_B
CsCsCs
80ns
Fig. 4-5 Logic Simulation of SR Latch Behavior
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
4-6
(a) Logic diagram
•
•R (Reset)
S (Set)Q
Q
•
•
(b) Function table
S
0
1
1
1
0
R
1
1
0
1
0
Q
1
1
0
0
1
Q
0
0
1
1
1
Set state
Reset state
Undefined
Fig. 4-6 Latch with NAND Gates
S R
S R
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
4-7
•
•
••
••
•
(a) Logic diagram
S
C
R
Q
Q
(b) Function table
C
0
1
1
1
1
S
X
0
0
1
1
R
X
0
1
0
1
Next state of Q
No change
No change
Q = 0; Reset state
Q = 1; Set state
Undefined
Fig. 4-7 SR Latch with Control Input
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4-8
(b) Function table
C
0
1
1
D
X
0
1
Next state of Q
No change
Q = 0; Reset state
Q = 1; Set state
(a) Logic diagram
•
•
••
••
•
D
C
Q
Q
•
•
S
R
Fig. 4-8 D Latch
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4-9
• •
• •
•
•
•••
••
C
D TG
TG Q
Q
Fig. 4-9 D Latch with Transmission Gates
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4-10
•• •
•
•
QY
S
C
R
QY
S
C
R
S
C
R
Fig. 4-10 SR Master-Slave Flip-Flop
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4-11
50ns0.0 100ns 150ns 200ns
ii
o
CSRY
CsCsCs
Qo
i
Fig. 4-11 Logic Simulation of a Master-Slave Flip-Flop
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4-12
Next Stateof Q
Q01Q
J0011
K0101
(b)
•
•••
•
Q
•
(a)
JCK
QS
C
R
S
C
R
Fig. 4-12 Master-Slave JK Flip-Flop
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4-13
•• •
•
• Q•
D
C
QS
C
R
D
C
Fig. 4-13 D-Type Positive Edge-Triggered Flip-Flop
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4-14
••
•• •
D
C •
S
C
R•
•
•
J
C
KQ
Q
Fig. 4-14 Positive Edge-Triggered JK Flip-Flop
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4-15
(a) Latches
(b) Master-Slave Flip-Flops
(c) Edge-Triggered Flip-Flops
SR
S
R ••
•
Triggered SR
S
R
C
•
Triggered D
D
C •
•
•
•
SR
S
R •
Triggered SR
S
R
C
•
Triggered D
D
C •
D with 1 Control
D
C •
Triggered JK
J
K
C
•
Triggered JK
J
K
C
•
D with 1 Control
D
C •
Triggered JK
J
K
C
••
Triggered JK
J
K
C
•
•
•
Fig. 4-15 Standard Graphic Symbols for Latch and Flip-Flops
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4-16
(a) JK Flip-Flop (b) SR Flip-Flop
J K Q (t � 1) Operation S R Q (t � 1) Operation
0 0 Q(t) No change 0 0 Q(t) No change0 1 0 Reset 0 1 0 Reset1 0 1 Set 1 0 1 Set1 1 Complement 1 1 ? Undefined
(c) D Flip-Flop (d) T Flip-Flop
D Q (t � 1) Operation T Q (t � 1) Operation
0 0 Reset 0 Q(t) No change
1 1 Set 1 Complement
Q t( )
Q t( )
TABLE 4-1Flip-Flop Characteristic Tables
Table 4-1 Flip-Flop Characteristic Tables
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4-17
(b) Function table
S0101111
R1001111
CXXX
JXXX0011
KXXX0101
Q10UndefinedNo change01Complement
Q01
10
��
��
••
S
1J
C1
1K
R
Q
Q
•
•(a) Graphic symbols
Fig. 4-16 JK Flip-Flop with Direct Set and Reset
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4-18
••
• •
J
C
K
A
A
XB
Y
C
•
•
•
Clock
Fig. 4-17 Implementing Input Equations
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4-19
D
C
A
A
D
C
B
B
X
Clock
Y
••
•
•
•
•
••
•
•
Fig. 4-18 Example of a Sequential Circuit
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4-20
TABLE 4-2State Table for Circuit of Figure 4-18
Present State Input Next State Output
A B X A B Y
00001111
00110011
01010101
00010101
01010000
00101010
Table 4-2 State Table for Circuit of Figure 4-18
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4-21
TABLE 4-3Two-Dimensional State Table for the Circuit in Figure 4-
Presentstate
Next state Output
X � 0 X � 1 X � 0 X � 1
A B A B A B Y Y
0011
0101
0000
0000
0111
1100
0111
0000
Table 4-3 Two-Dimensional State Table for the Circuit in Figure 4-18
18
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4-22
(b) State table
Z00001111
OutputA01101001
NextstateInputs
X00110011
Y01010101
A00001111
Presentstate
Clock
•
•
D
C
ZX
Y
(a)
A
Fig. 4-19 Logic Diagram and State Table for DA A X Y⊕ ⊕=
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4-23
TABLE 4-4State Table for Circuit with JK Flip-Flops
Present state Input Next state Flip-flop inputs
A B X A B JA KA JB KB
00001111
00110011
01010101
00111101
10101001
00110011
00100010
10101010
01011010
Table 4-4 State Table for Circuit with JK Flip-Flops
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4-24
(b)(a)
0/0 1/0
0/1
0/1 0/1
1/01/0
1/0
00 01
10 11
00,11
01,10
01,10
00,110/0 1/1
Fig. 4-20 State Diagrams
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4-25
(a) (b)
(c)
(d)
A B1/0
C1/0
D0/0 1/1
A B1/0
C1/0
D0/0
1/0
1/1
0/0
0/0
0/0
A B1/0
A B1/0
C1/0
Fig. 4-21 Construction of a State Diagram
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4-26
TABLE 4-5State Table for State Diagram in Figure 4-21
Present State
Next State Output Z
X � 0 X � 1 X � 0 X � 1
ABCD
AADA
BCCB
0000
0001
Table 4-5 State Table for State Diagram in Figure 4-21
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4-27
TABLE 4-6Sequence Tables for Code Converter Example
Sequences in Order of Digits Represented Sequences in Order of Common Prefixes
BCD Input Excess-3 Output BCD Input Excess-3 Output
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
0101010101
0011001100
0000111100
0000000011
1010101010
1001100110
0111100001
0000011111
0000011111
0001100011
0010100101
0100001000
1111100000
1110000011
0011011010
0100101101
Table 4-6 Sequence Tables for Code Converter Example
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4-28
(b)
0/0 or 1/1
0/1
B1=0
Init
B1=1
1/0
(a)
0/1
B1=0
Init
B1=1
1/0
B2=1B2=0
0/1 1/0
B2=X
0/1
B1=0
Init
B1=1
1/0
B2=1B2=0
0/1 1/0 0/0 or 1/1
B2=X
B3=0 B3=1
0/0 or 1/1
0/1 or 1/10/1
B1=0
Init
B1=1
1/0
B2=1B2=0
0/1 1/0 0/0 or 1/1
B2=X
B3=0 B3=1
0/0 or 1/1
0/1 or 1/1 0/1
B1=0
Init
B1=1
1/0
B2=1B2=0
0/1 1/0 0/0 or 1/1
B2=X
B3=0 B3=1
0/0 or 1/1
0/1 or 1/1
(c) (d)
0/0 or 1/10/1
1/01/0
0/1
Fig. 4-22 Construction of a State Diagram
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4-29
TABLE 4-7Table 4-5 with Names Replaced by Binary Codes
Present State
Next State Output Z
X � 0 X � 1 X � 0 X � 1
00011110
00001000
01111101
0000
0001
Table 4-7 Table 4-5 with Names Replaced by Binary Codes
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4-30
TABLE 4-8State Table for Design Example
Present State Input Next State Output
A B X A B Y
00001111
00110011
01010101
00101110
01010110
01000100
Table 4-8 State Table for Design Example
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4-31
0/0
00
1/0 010/0
11
0/0
10
0/0
1/1
1/1
1/0
Fig. 4-23 State Diagram for Design Example
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4-32
DA = AB + BX
BXA
1
10
1
B
X
A 1 1
00 01 11 10
DB = AX + BX + ABX
1
11
1
Y = BX
1
1
BXA
0
1
B
X
A
00 01 11 10BX
A
0
1
B
X
A
00 01 11 10
Fig. 4-24 Maps for Input Equations and Output Y
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4-33
••• •
•
•
•
•
•
•
•
•
•
•
•D
C
•D
C
Clock
A
A
B
B
Y
X
Fig. 4-25 Logic Diagram for Sequential Circuit with D Flip-Flops
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4-34
TABLE 4-9State Table for Second Design Example
Present State Input Next State
A B C X A B C
0000001111
0011110000
1100110011
0101010101
0001011101
0110000000
1010101010
Table 4-9 State Table for Second Design Example
![Page 1013: Digital Logic Circuit Analysis and Design,Victor P. Nelson](https://reader033.vdocuments.site/reader033/viewer/2022061202/547b963cb4af9f2b2b8b4654/html5/thumbnails/1013.jpg)
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4-35
00
01
00 01CX
AB
C
X
A
11 10
11
10
B
XX
1 1
X XX X
1 11
DA = AX + BX + BC DB = ACX + ABX
XX
1
1
X XX X
DC = X
XX
1
X XXX
1
1
1
1
Fig. 4-26 Maps for Simplifying Input Equations
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4-36
TABLE 4-10Flip-Flop Excitation Tables
(a) JK Flip-Flop (b) SR Flip-Flop
Q (t ) Q (t � 1) J K Q (t ) Q (t � 1) S R
0011
0101
01XX
XX10
0011
0101
010X
X010
(c) D Flip-Flop (d) T Flip-Flop
Q (t) Q (t � 1) D Q (t) Q (t � 1) T
0011
0101
0101
0011
0101
0110
Table 4-10 Flip-Flop Excitation Tables
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4-37
TABLE 4-11State Table with JK Flip-Flop Inputs
Present State Input Next State Flip-Flop Inputs
A B X A B JA KA JB KB
00001111
00110011
01010101
00101110
01010110
0010XXXX
XXXX0001
01XX01XX
XX10XX01
Table 4-11 State Table with JK Flip-Flop Inputs
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4-38
JA = BX
BXA
X
10
1
B
X
A X X
00 01 11 10
X
JB = X
BXA
X10
1
B
X
A
X
X
00 01 11 10
X1
KA = BX
BXA
X
1
0
1
B
X
A
X X
00 01 11 10
X
BXA
X 10
1
B
X
A
X
X
00 01 11 10
X 1
KB = AX + AX = A X
Fig. 4-27 Maps for J and K Input Equations
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4-39
FJKC
FJKC
AND2
AND2
AND2
INV
XNOR2
INV
X
CLK
R
Y
A
B
Fig. 4-28 Logic Diagram for Sequential Circuit with JK Flip-Flops
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4-40
(b) Simulation results
R:
X:
A:
B:
Y:
0
0
X
X
0
0
0
X
X
0
0
1
0
0
1
0
1
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
1
0
1
0
0
1
1
0
0
1
1
1
0
0
1
0
0
1
0
0
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0*
0*
0*
0
0
0
0
0
* These responses are asynchronous with the clock and thus do not w ait for the next positiveclock edge.
(a) Circuit test and expected results
1
0
0*
0*
0*
20ns0.0 40ns 60ns 80ns
ii
o
CLKRXA
CsCsCs
Bo
i
Yo
100ns 120ns 140ns 160ns 180ns 200ns 220ns 240ns 260ns 280ns
Fig. 4-29 Logic Simulation Verification for the Circuit in Figure 4-28
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4-41
-- Positive Edge-Triggered D Flip-Flop with Reset:-- VHDL Process Descriptionlibrary ieee;use ieee.std_logic_1164.all;entity dff is port(CLK, RESET, D : in std_logic; Q : out std_logic);end dff;
architecture pet_pr of dff is-- Implements positive edge-triggered bit state storage-- with asynchronous reset.
beginprocess (CLK, RESET) begin if (RESET = '1') then Q <= '0'; elsif (CLK'event and CLK = '1') then Q <= D; end if; end if; end process;end;
Fig. 4-30 VHDL Process Description of Positive Edge-Triggered Flip-Flop with Reset
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
4-42-- Sequence Recognizer: VHDL Process Description-- (See Figure 4-21 for state diagram)library ieee;use ieee.std_logic_1164.all;entity seq_rec is port(CLK, RESET, X: in std_logic; Z: out std_logic);end seq_rec;
architecture process_3 of seq_rec is type state_type is (A, B, C, D); signal state, next_state : state_t ype;begin
-- Process 1 - state_register: implements positive edge-triggered-- state storage with asynchronous reset. state_register: process (CLK, RESET) begin if (RESET = '1') then state <= A; elsif (CLK’event and CLK = '1') then state <= next_state; end if; end if;end process;
-- Process 2 - next_state_function: implements next state as-- a function of input X and state. next_state_func: process (X, state) begin case state is when A =>
if X = '1' then next_state <= B; else next_state <= A;
end if; when B =>
if X = '1' then next_state <= C; else next_state <= A;
end if;
Fig. 4-31 VHDL Process Description of a Sequence Recognizer
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4-43-- Sequence Recognizer: VHDL Process Description (continued)
when C =>
if X = '1' then next_state <= C; else next_state <= D;
end if; when D =>
if X = '1' then next_state <= B; else next_state <= A;
end if; end case; end process;
-- Process 3 - output_function: implements output as function-- of input X and state. output_func: process (X, state) begin case state is when A =>
Z <= '0'; when B => Z <= '0'; when C => Z <= '0';
when D => if X = '1' then Z <= '1'; else Z <= '0';
end if; end case; end process;end;
Fig. 4-32 VHDL Process Description of a Sequence Recognizer (continued)
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
4-44
TABLE 4-12Illustration of generation of storage in VHDL
Inputs Action
RESET = 1 CLK = 1 CLK’event
FALSE FALSE FALSE Unspecified
FALSE FALSE TRUE Unspecified
FALSE TRUE FALSE Unspecified
FALSE TRUE TRUE Q <= D
TRUE — — Q <= '0'
Table 4-12 Illustration of generation of storage in VHDL
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4-45
// Positive Edge-Triggered D Flip-Flop with Reset:// Verilog Process Description
module dff_v(CLK, RESET, D, Q); input CLK, RESET, D; output Q; reg Q;
always @(posedge CLK or posedge RESET)begin if (RESET) Q <= 0; else Q <= D;endendmodule
Fig. 4-33 Verilog Process Description of Positive Edge-Triggered Flip-Flop with Reset
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
4-46// Sequence Recognizer: Verilog Process Description// (See Figure 4-21 for state diagram)module seq_rec_v(CLK, RESET, X, Z);
input CLK, RESET, X;output Z;reg [1:0] state, next_state;parameter A = 2'b00, B = 2'b01, C = 2 'b10, D = 2'b11;reg Z;
// state register: implements positive edge-triggered// state storage with asynchronous reset.always @(posedge CLK or posedge RESET)begin
if (RESET == 1)state <= A;
elsestate <= next_state;
end// next state function: implements next state as funct ion// of X and statealways @(X or state) begin
case (state)A: if (X == 1)
next_state <= B;else
next_state <= A;B: if(X) next_state <= C;else next_state <= A;C: if(X) next_state <= C;else next_state <= D;D: if(X) next_state <= B;else next_state <= A;
endcaseend// output function: implements output as function// of X and statealways @(X or state)
(state) begin
caseA: Z <= 0;B: Z <= 0;C: Z <= 0;D: Z <= X ? 1 : 0;
endcaseendendmodule
Fig. 4-34 Verilog Process of a Sequence Recognizer
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© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
4-47
TABLE 4-13Illustration of generation of storage in Verilog
Inputs Action
posegdge RESET and RESET = 1 posedge CLK
FALSE FALSE Unspecified
FALSE TRUE Q <= D
TRUE FALSE Q <= 0
0TRUE TRUE Q <=
Table 4-13 Illustration of generation of storage in Verilog