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Digital Integrated Circuits – EECS 312
http://robertdick.org/eecs312/
Teacher: Robert DickOffice: 2417-E EECSEmail: [email protected]: 734–763–3329Cellphone: 847–530–1824
GSI: Shengshou LuOffice: 2725 BBBEmail: [email protected]
HW engineers SW engineers
0
1
2
3
4
5
6
7
8
9
10
200 220 240 260 280 300
Cu
rre
nt
(mA
)
Time (seconds)
Typical Current Draw 1 sec Heartbeat
30 beats per sample
Sampling andRadio Transmission
9 - 15 mA
Heartbeat1 - 2 mA
Radio Receive for
Mesh Maintenance
2 - 6 mA
Low Power Sleep0.030 - 0.050 mA
Year of announcement
1950 1960 1970 1980 1990 2000 2010
Pow
er d
ensi
ty (
Wat
ts/c
m2 )
0
2
4
6
8
10
12
14
Bipolar
CMOS
VacuumIBM 360
IBM 370 IBM 3033
IBM ES9000
Fujitsu VP2000
IBM 3090S
NTT
Fujitsu M-780
IBM 3090
CDC Cyber 205IBM 4381
IBM 3081Fujitsu M380
IBM RY5
IBM GP
IBM RY6
Apache
Pulsar
Merced
IBM RY7
IBM RY4
Pentium II(DSIP)
T-Rex
Squadrons
Pentium 4
Mckinley
Prescott
Jayhawk(dual)
IBM Z9
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Review
1 Explain each transistor operating region.
2 What is pinch-off?
3 How does body bias work?
4 What is velocity saturation?
5 What is sub-threshold operation?
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Lecture plan
1. Device trends
2. Fabrication
3. Layout and design rules
4. Packaging and board-level integration
5. Homework
3 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Process variation
Given our current knowledge of transistor operation, what impact willvariation in
dopant concentrations,
oxide thickness,
transistor width, and
interconnect width
have?
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
FinFETs
From Freescale.
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Carbon nanotubes and nanowires
From AIST.
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Quantum cellular automata
Binary information encoded in device configuration.
Signals are propagated through nearest neighbor interaction.
From Professor Xiaobo Sharon Hu.
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Quantum cellular automata arithmetic-logic unit
From Professor Xiaobo Sharon Hu.
8 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Single-electron tunneling transistors
Source(S)
Optionalsecond
gate (G2) Drain(D)
(G)Gate
Insulator
Island
Junctions
9 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Common problems
Difficult to get high-quality devices where they are needed.
High susceptibility to thermal noise.
High susceptibility to charge trap offsets.
Low gain.
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
What does the future hold
CMOS for another decade or so, until devices consist of a smallinteger number of atoms.
Nobody knows what comes next.
Nothing? New device technology?
Implications for information technology?
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Lecture plan
1. Device trends
2. Fabrication
3. Layout and design rules
4. Packaging and board-level integration
5. Homework
12 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Review
1 List a few different alternatives to CMOS for use in digitalsystems.
2 Indicate their advantages and disadvantages relative to CMOS.
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
NMOSFET
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Insulator properties
Low-κ: reduced capacitance, useful for isolating wires.
High-κ: increased capacitance, useful for maintaining k despiteincreased gate thickness.
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
High-level fabrication process overview
16 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Schematic of circuit to fabricate
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Layout of circuit to fabricate
18 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Overview of fabrication process
19 Robert Dick Digital Integrated Circuits
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Fabrication process details
From Richard C. Jaeger. Introduction to Microelectronic Fabrication.Addison-Wesley, 1993.
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
SiO2 patterning
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Etching
From Richard C. Jaeger. Introduction to Microelectronic Fabrication.Addison-Wesley, 1993.
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Summary of processing steps
1 Define active areas.
2 Etch and fill trenches.
3 Implant well regions.
4 Deposit and pattern polysilicon/metal gate layer.
5 Implant source and drain regions, and substrate contacts.
6 Create contacts and via windows.
7 Deposit and pattern metal layers.
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Step 1: epitaxial layer
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Step 2: gate oxide and sacrificial nitride layer deposition
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Step 3: plasma etching
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Step 4: trench filling, CMP, etching, SiO2 deposition
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Step 5: n-well and VTn adjustment implants
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Step 6: p-well and VTp adjustment implants
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Step 7: polysilicon/metal deposition and etch
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Step 8: n+ and p+ source, drain, and poly implantation
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Step 9: SiO2 deposition and contact etch
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Step 10: deposit and pattern first interconnect layer
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Step 11: deposit SiO2, etch contacts, deposit and patternsecond interconnect layer
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Interconnect layers
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Al vs. Cu
For Al, can deposit and etch metal layers.
Cu alloys with Si.
Cannot safely deposit Cu directly on Si.
Cu difficult to controllably etch.
Instead, build SiO2 shield and etch contact regions.
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Damascene process
From IBM.
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Interconnect layers
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Lecture plan
1. Device trends
2. Fabrication
3. Layout and design rules
4. Packaging and board-level integration
5. Homework
39 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Layout production
Must define 2-D structure for each mask/layer.
Initial topology planning often done.
Can be partially or fully automated.
Must adhere to design rules.
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Stick diagrams
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Faults and variation
Clearly cannot have two wires crossing each other.
Variation imposes further constraints.
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Possible faults
z
b
a
VDD
za
b
VDD
VSS
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Possible faults
bridgingfault
z
b
a
VDD
za
b
VDD
VSS
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Possible faults
z
b
a
VDD
za
b
VDD
VSS
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Possible faults
stuck−openfault
z
b
a
VDD
za
b
VDD
VSS
43 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Possible faults
z
b
a
VDD
za
b
VDD
VSS
43 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Possible faults
stuck−at
fault
z
b
a
VDD
za
b
VDD
VSS
43 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Possible faults
z
b
a
VDD
za
b
VDD
VSS
43 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Design rules
Summary
Automatically-checked layout rules.
Reduce fault probabilities.
Generally regarded as necessary.
Caveats
Recent studies show many rules are not beneficial.
Interaction range is increasing relative to λ.
Complicates design rules, making manual comprehension difficult.
Design rule checking can be slow.
44 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Meanings of colors in layouts
45 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Layout layers
46 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Intra-layer design rules
47 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Via design rules
48 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Layout editor
49 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Design rule checker
50 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Lecture plan
1. Device trends
2. Fabrication
3. Layout and design rules
4. Packaging and board-level integration
5. Homework
51 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Packaging requirements
Electrical: Good insulators and conductors.
Mechanical: Reliable, doesn’t stress IC.
Thermal: Low thermal resistance to ambient. In some cases,consistency more important.
Cost.
52 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Wire bonding
53 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Tape automated bonding
54 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Tape automated bonding die attachment
55 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Flip-chip bonding
56 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Through-hole PCB mounting
57 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Surface mount
58 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Example package types
59 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Chip cap
60 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Heat pipe
61 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Heat pipe details
62 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Example of variation in package parameters
Type C (pF) L (nH)
68-pin plastic DIP 4 3568-pin ceramic DIP 7 20
256-pin PGA 5 15Wire bond 1 1
Solder bump 0.5 0.1
63 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
System-on-chip
Instead of integrating more ICs, put more on an IC.
Advantages: Lower cost per device, compact.
Disadvantages: Requires integration of devices fabricated withdifferent processes.
64 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Move from lead solder
Tin–lead solder was commonly used.
Lead is toxic, accumulates in the body, and is difficult to disposeof.
Pure tin works in the short term.
May be acceptable as solder in the long term.
Problems with plating.
65 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Tin whiskers
Screw dislocations, primarily caused by plating.
66 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Multi-chip modules
Better C than board-levelintegration.
Integrate multiple processes.
Somewhat compact.
Expensive.
67 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Multiple active layer 3-D integration
2-D chip-multiprocessor 3-D chip-multiprocessor
Heat sink
Silicon layer
PCB layer
Carrier layer
Potential for thermal problems.
68 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Heterogeneous system 3-D integration
Integrate
Logic.
Memory.
Analog.
Research on discrete components (with soldering).
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Microchannel cooling
Credit to David Atienza at EPFL.70 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Vapor-phase cooling
Credit to Michael J. Ellsworth, Jr. and Robert E. Simons at IBM.
71 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Summary
CMOS is the most economical way to build digital logic now, butpotential alternatives being developed.
Fabrication process is essentially repeated deposition, masking,etching, and polishing steps to dope and build material layers.
Al→Cu.
SiO2 → High-κ and Low-κ.
Cu interconnects use damascene process.
Poly-Si→metal.
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Upcoming topics
MOSFET dynamic behavior.
Wires.
CMOS inverters.
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Lecture plan
1. Device trends
2. Fabrication
3. Layout and design rules
4. Packaging and board-level integration
5. Homework
74 Robert Dick Digital Integrated Circuits
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Device trendsFabrication
Layout and design rulesPackaging and board-level integration
Homework
Homework assignment
24 September: Read Mark T. Bohr, Robert S. Chau, Tahir
Ghani, and Kaizad Mistry. The High-k Solution.IEEE Spectrum, October 2007.
24 September: Homework 1.
3 October: Lab 2.
75 Robert Dick Digital Integrated Circuits