Digital block implementation methodology for a 130nm process
Microelecronics User Group meeting TWEPP 2009 – Paris
Sandro Bonacini CERN PH/ESE
Sandro Bonacini - PH/ESE - [email protected]
Motivation
Implementation of digital blocks for small (~200 kgate) logic cores for digital or mixed signal ASICs
Using the IBM 130 nm standard cell library Separate substrate/ground and n-well/VDD biasing for mixed
signal designs
Defined methodology compatible with mixed signal design flows Open Access based
Sandro Bonacini - PH/ESE - [email protected]
Design flow components Tools
Virtuoso 6.1.3 (OA based) SOC Encounter 7.1 Conformal 7.2 EXT 7.1.2 (QRC) Assura 3.2 Calibre 2008.3
Design Kits IBM CMOS8RF DM design kit V1.6
3 thin, 2 thick, 3 RF metals. IBM CMOS8RF LM design kit V1.6
6 thin, 2 thick metals.
Sandro Bonacini - PH/ESE - [email protected]
Digital design flow RTL synthesis
Floorplanning & power routing
Placement
Congestion analysis
Logical Equivalence
Checking
Timing optimization
Signoff RC extraction
Timing analysis
DRC
DFM
LVS
Logical Equivalence
Checking Clock tree synthesis
Routing
Timing optimization
Timing optimization
Tape-out
Automated task User task
Sandro Bonacini - PH/ESE - [email protected]
RTL compiler script [.tcl]
Abstract layout Definition [.lef]
Capacitance tables [.CapTbl]
Max timing Liberty libraries
[.lib]
Synthesis
RTL synthesis
RTL description [.v] / [.vhd]
Timing constraints
[.sdc]
Mapped netlist [.v]
Conformal script [.lec]
Synthesis, mapping and timing reports
Timing constraints: Clock definitions Input delays,
fanout, transition, etc.
Output load, etc.
Sandro Bonacini - PH/ESE - [email protected]
RTL Compiler [rc]
Sandro Bonacini - PH/ESE - [email protected]
Digital design flow RTL synthesis
Floorplanning & power routing
Placement
Congestion analysis
Logical Equivalence
Checking
Timing optimization
Signoff RC extraction
Timing analysis
DRC
DFM
LVS
Logical Equivalence
Checking Clock tree synthesis
Routing
Timing optimization
Timing optimization
Tape-out
Automated task User task
Logical Equivalence
Checking
Sandro Bonacini - PH/ESE - [email protected]
Logic Equivalence Checking
Tool: Conformal
Logical Equivalence
Checking
Max timing Liberty libraries
[.lib]
Mapped netlist [.v]
Conformal script [.lec]
RTL description [.v] / [.vhd]
LEC report
Sandro Bonacini - PH/ESE - [email protected]
Digital design flow RTL synthesis
Floorplanning & power routing
Placement
Congestion analysis
Logical Equivalence
Checking
Timing optimization
Signoff RC extraction
Timing analysis
DRC
DFM
LVS
Logical Equivalence
Checking Clock tree synthesis
Routing
Timing optimization
Timing optimization
Tape-out
Automated task User task
Floorplanning & power routing
Sandro Bonacini - PH/ESE - [email protected]
Tool: Encounter
Design import and floorplanning
Mapped netlist [.v]
RTL description [.v] / [.vhd]
Open Access Standard cells
library [.oa]
QX tech file [.tch]
Capacitance tables [.CapTbl]
Min/Max timing Liberty libraries
[.lib]
Open Access Floorplanned
Design [.oa]
Reports Floorplanning
& power routing
Sandro Bonacini - PH/ESE - [email protected]
Design import
Sandro Bonacini - PH/ESE - [email protected]
Floorplanning & power routing
Define Chip/core size target area utilization I/O placement module placement in
case of TMR or other special constraints
Power planning/routing Core/block rings and
stripes
Sandro Bonacini - PH/ESE - [email protected]
Digital design flow RTL synthesis
Floorplanning & power routing
Placement
Congestion analysis
Logical Equivalence
Checking
Timing optimization
Signoff RC extraction
Timing analysis
DRC
DFM
LVS
Logical Equivalence
Checking Clock tree synthesis
Routing
Timing optimization
Timing optimization
Tape-out
Automated task User task
Placement
Sandro Bonacini - PH/ESE - [email protected]
Placement
Encounter command file
Placement
Scan-chain reorder
Open Access Floorplanned Design [.oa]
Connect cells power/ground
Add tap cells
Open Access Placed
Design [.oa]
Reports
Sandro Bonacini - PH/ESE - [email protected]
Power/ground connections
Placement
Tap cells Standard cells
Sandro Bonacini - PH/ESE - [email protected]
Digital design flow RTL synthesis
Floorplanning & power routing
Placement
Congestion analysis
Logical Equivalence
Checking
Timing optimization
Signoff RC extraction
Timing analysis
DRC
DFM
LVS
Logical Equivalence
Checking Clock tree synthesis
Routing
Timing optimization
Timing optimization
Tape-out
Automated task User task
Congestion analysis
Sandro Bonacini - PH/ESE - [email protected]
Congestion analysis
Use Encounter Trialroute to estimate congested areas
Manually add placement partial blockage
Change position of I/Os or blocks
…or increase number of routing metals
Open Access Placed
Design [.oa]
Congestion analysis
Placement optimization
Open Access Placed
Design [.oa]
Sandro Bonacini - PH/ESE - [email protected]
Digital design flow RTL synthesis
Floorplanning & power routing
Placement
Congestion analysis
Logical Equivalence
Checking
Timing optimization
Signoff RC extraction
Timing analysis
DRC
DFM
LVS
Logical Equivalence
Checking Clock tree synthesis
Routing
Timing optimization
Timing optimization
Tape-out
Automated task User task
Timing optimization
Clock tree synthesis
Routing
Timing optimization
Timing optimization
Sandro Bonacini - PH/ESE - [email protected]
Automatic P&R steps
Timing optimization
Open Access Placed
Design [.oa]
Clock tree synthesis
Routing
Open Access Routed
Design [.oa]
Timing optimization
Timing optimization
Reports
Sandro Bonacini - PH/ESE - [email protected]
Clock tree synthesis & signal routing
Sandro Bonacini - PH/ESE - [email protected]
Digital design flow RTL synthesis
Floorplanning & power routing
Placement
Congestion analysis
Logical Equivalence
Checking
Timing optimization
Signoff RC extraction
Timing analysis
DRC
DFM
LVS
Logical Equivalence
Checking Clock tree synthesis
Routing
Timing optimization
Timing optimization
Tape-out
Automated task User task
Signoff RC extraction
Timing analysis
DFM
Sandro Bonacini - PH/ESE - [email protected]
Design for manufacturing
Signoff RC extraction
Cells & metal fill
Open Access Routed
Design [.oa]
Antenna fix
Via optimization
Timing analysis
Open Access Final
Design [.oa]
Signoff timing report
Delay file [.sdf]
Final netlist [.v]
Signal integrity analysis
Sandro Bonacini - PH/ESE - [email protected]
Antenna fix
Re-routes long nets
Inserts tie-down diodes
Sandro Bonacini - PH/ESE - [email protected]
Via optimization
Sandro Bonacini - PH/ESE - [email protected]
Cells & metal fill
Sandro Bonacini - PH/ESE - [email protected]
Timing closure
If signoff timing analysis reports violations increase buffer sizes add extra buffers reroute signals check constraints exploit useful skew annotate native post-route RC
extraction tool re-run optimization
Sandro Bonacini - PH/ESE - [email protected]
Digital design flow RTL synthesis
Floorplanning & power routing
Placement
Congestion analysis
Logical Equivalence
Checking
Timing optimization
Signoff RC extraction
Timing analysis
DRC
DFM
LVS
Logical Equivalence
Checking Clock tree synthesis
Routing
Timing optimization
Timing optimization
Tape-out
Automated task User task
DRC
LVS
Logical Equivalence
Checking
Sandro Bonacini - PH/ESE - [email protected]
Virtuoso
OA design is present in Virtuoso Easily
included in a mixed-signal chip
Sandro Bonacini - PH/ESE - [email protected]
Thank you…
Design flow …is soon to be available
Implementation of digital blocks Using the IBM 130 nm standard cell library Defined methodology compatible with mixed signal design
flows
Open Access based