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© K
LMH
Lien
ig
Detail Routing
Presented By:Sridhar H RangarajanIBM STG India Enterprise Systems Development
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Detailed RoutingTerminologyHorizontal and Vertical Constraint Graphs
Horizontal Constraint GraphsVertical Constraint Graphs
Channel Routing AlgorithmsLeft-Edge AlgorithmDogleg Routing
Switchbox RoutingTerminologySwitchbox Routing Algorithms
Over-the-Cell Routing AlgorithmsOTC Routing MethodologyOTC Routing Algorithms
Modern Challenges in Detailed Routing
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Timing-Driven Routing
GlobalRouting
DetailedRouting
Large Single-Net Routing
Coarse-grain assignment of routes to routing regions
Fine-grain assignment of routes to routing tracks
Net topology optimization and resource allocation to critical nets
Power (VDD) and Ground (GND)routing
Routing
Geometric Techniques
Non-Manhattanand clock routing
Multi-Stage Routing of Signal Nets
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n The objective of detailed routing is to assign route segments of signal nets to specific routing tracks, vias, and metal layers in a manner consistent with given global routes of those nets
n Similar to global routing¨ Use physical wires to do connections¨ Estimating the wire resistance and capacitance, which determines whether the design
meets timing requirements
n Detailed routing techniques are applied within routing regions, such as ¨ Channels¨ switchboxes, and ¨ global routing cells
n Detailed routers must account for ¨ manufacturing rules and ¨ the impact of manufacturing faults
Detailed Routing
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5
n Detailed Routing Stages¨ Assign routing tracks¨ Perform entire routing – no open connection left¨ Search and repair – resolving all the physical design rules¨ Perform optimizations, e.g. add redundant vias (reduce resistivity, better yield)
Detailed Routing
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Cell Area
A A
B B
B
B
BC
C
C
CD
Three-Layer OTC RoutingOTC: Over the cell
A A
B B
B
B
BC
C
C
CD
Two-Layer Channel Routing
Cell Area
Metal3
Via
Metal1
Metal2
Terminology
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Columns
Tracks
Cha
nnel
H
eigh
t
A A
B B
B
B
BC
C
C
CD
a b c d e f g
1
2
3
Pin Locations
Horizontal Segment(Trunk)
Vertical Segment(Branch)
Terminology
0
0
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Horizontal Constraint
n Assumption: one layer for horizontal routing n A horizontal constraint exists between two nets
if their horizontal segments overlap
Terminology
A
A
B
BC
C
Horizontally unconstrained
Horizontallyconstrained
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Vertical Constraint
Terminology
n A vertical constraint exists between two nets if they have pins in the same column
Þ The vertical segment coming from the top must “stop” before overlapping with the vertical segment coming from the bottom in the same column
Vertically constrained with a vertical conflict
Vertically constrained without conflict
B A
A B
B A
A BB
AB
A
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Horizontal and Vertical Constraint Graphs
n The relative positions of nets in a channel routing instance can be modeled by horizontal and vertical constraint graphs
n These graphs are used to ¨ initially predict the minimum number of tracks that are required¨ detect potential routing conflicts
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n Let S(col) denote the set of nets that pass through column coln S(col) contains all nets that either (1) are connected to a pin in column col
or (2) have pin connections to both the left and right of coln Since horizontal segments cannot overlap, each net in S(col) must be
assigned to a different trackn S(col) represents the lower bound on the number of tracks in colum col;
lower bound of the channel height is given by maximum cardinality of any S(col)
A C E C E A F H H G0
0 B D E B GF 0 D 0 0Column a b c d e f g h i j k
S(b) = {A, B, C}
Horizontal Constraint Graphs
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BA
CD
EF
GH
A C E C E A F H H G0
0 B D E B GF 0 D 0 0Column a b c d e f g h i j k
A C E C E A F H H G0
0 B D E B GF 0 D 0 0
Horizontal Constraint Graphs
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BA
CD
EF
GH
A C E C E A F H H G0
0 B D E B GF 0 D 0 0Column a b c d e f g h i j k
A C E C E A F H H G0
0 B D E B GF 0 D 0 0
Horizontal Constraint Graphs
S(c) S(f)S(g) S(i)S(a)S(b) S(d)S(e) S(h) S(j)S(k) S(a) = {A}S(b) = {A,B,C}S(c) = {A,B,C,D,E}S(d) = {A,B,C,D,E}S(e) = {A,B,D,E}S(f) = {A,D,F}S(g) = {D,F,G}S(h) = {D,G,H}S(i) = {D,G,H}S(j) = {G,H}S(k) = {G}
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S(c) S(f)S(g) S(i)0 B D E B GF 0 D 0 0
S(a)S(b) S(d)S(e) S(h) S(j)S(k)
0 B D E B GF 0 D 0 0Column a b c d e f g h i j k
A C E C E A F H H G0
A C E C E A F H H G0
BA
CD
EF
GH
Horizontal Constraint Graphs
S(a) = {A}S(b) = {A,B,C}S(c) = {A,B,C,D,E}S(d) = {A,B,C,D,E}S(e) = {A,B,D,E}S(f) = {A,D,F}S(g) = {D,F,G}S(h) = {D,G,H}S(i) = {D,G,H}S(j) = {G,H}S(k) = {G}
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S(c) S(f)S(g) S(i)
S(c) S(f) S(g) S(i)ABCD
FG
H
E
0 B D E B GF 0 D 0 0Column a b c d e f g h i j k
A C E C E A F H H G0
0 B D E B GF 0 D 0 0
A C E C E A F H H G0
BA
CD
EF
GH
Horizontal Constraint Graphs
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Lower bound on the number of tracks = 5
0 B D E B GF 0 D 0 0Column a b c d e f g h i j k
A C E C E A F H H G0
S(c) S(f) S(g) S(i)ABCD
FG
H
E
Horizontal Constraint Graphs
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0 B D E B GF 0 D 0 0Column a b c d e f g h i j k
A C E C E A F H H G0
S(c) S(f) S(g) S(i)ABCD
FG
H
E
F
G
H CE
B
A
D
Horizontal Constraint Graphs
Graphical Representation
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n A directed edge e(i,j) Î E connects nodes i and jif the horizontal segment of net i must be located above net j
B
A
A
B
Vertical Constraint Graphs
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19
A
Vertical Constraint Graphs
0 B D E B GF 0 D 0 0
A C E C E A F H H G0
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20
B
C
A
Vertical Constraint Graphs
0 B D E B GF 0 D 0 0
A C E C E A F H H G0
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21
E
D
A
Vertical Constraint Graphs
0 B D E B GF 0 D 0 0
A C E C E A F H H G0
B
C
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22
Vertical Constraint Graphs
0 B D E B GF 0 D 0 0
A C E C E A F H H G0
E
D
A
B
C
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Vertical Constraint Graph (VCG)
Vertical Constraint Graphs
0 B D E B GF 0 D 0 0
A C E C E A F H H G0
Note: an edge that can be derived by transitivity is not included,such as edge (B,C)
E
D
A
B
C
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Vertical Constraint Graphs
0 B D E B GF 0 D 0 0
A C E C E A F H H G0
FE
D
A
B
C
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25
Vertical Constraint Graphs
0 B D E B GF 0 D 0 0
A C E C E A F H H G0
G
FE
D
A
B
C
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Vertical Constraint Graphs
0 B D E B GF 0 D 0 0
A C E C E A F H H G0
H
G
FE
D
A
B
C
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B
E
C
D
A
F
G
H
Vertical Constraint Graphs
0 B D E B GF 0 D 0 0
A C E C E A F H H G0
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A B B
B 0 A
A
B
B A
A B B
Cyclic conflict
Net splitting
Vertical Constraint Graphs
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Left-Edge Algorithm
n Based on the VCG and the zone representation, greedily maximizes the usage of each track ¨ VCG: assignment order of nets to tracks¨ Zone representation: determines which nets may share the same
track
n Each net uses only one horizontal segment (trunk)
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Input: channel routing instance CROutput: track assignments for each net
curr_track = 1 // start with topmost tracknets_unassigned = Netlistwhile (nets_unassigned != Ø) // while nets still unassigned
VCG = VCG(CR) // generate VCG and zoneZR = ZONE_REP(CR) // representationSORT(nets_unassigned,start column) // find left-to-right ordering
// of all unassigned netsfor (i =1 to |nets_unassigned|)
curr_net = nets_unassigned[i]if (PARENTS(curr_net) == Ø && // if curr_net has no parent
(TRY_ASSIGN(curr_net,curr_track)) // and does not cause// conflicts on curr_track,
ASSIGN(curr_net,curr_track) // assign curr_netREMOVE(nets_unassigned,curr_net)
curr_track = curr_track + 1 // consider next track
Left-Edge Algorithm
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0 A D E A GF 0 D I J J
B C E C E B F H I H G I
Left-Edge Algorithm – Example
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1. Generate VCG and zone representation
A
E
C
JD
B
F
G
H
I
A G
B H
C I
D J
E F
0 A D E A GF 0 D I J J
B C E C E B F H I H G I
Left-Edge Algorithm – Example
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A G
B H
C I
D J
E F
2. Consider next track3. Find left-to-right ordering of all unassigned nets
If curr_net has no parents and does not cause conflicts on curr_trackassign curr_net
curr_track = 1: Net JNet A
E
C
D
B
F
G
H
I
JA
4. Delete placed nets (A, J ) in VCG and zone represenation
Left-Edge Algorithm – Example
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34
B C E C E B F H I H G I
curr_track = 12
3
4
5
0 A D E A GF 0 D I J J
Left-Edge Algorithm – Example
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curr_track = 2:
E
C
B
F
G
H
I
G
H
C I
D
E F
Net D
4. Delete placed nets (D ) in VCG and zone representation
B
2. Consider next track3. Find left-to-right ordering of all unassigned nets
If curr_net has no parents and does not cause conflicts on curr_trackassign curr_net
D
Left-Edge Algorithm – Example
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36
B C E C E B F H I H G I
1curr_track = 2
3
4
5
0 A D E A GF 0 D I J J
Left-Edge Algorithm – Example
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curr_track = 3:
E
C
B
F
G
H
I
G
H
C I
E F
Net E Net G
4. Delete placed nets (E, G ) in VCG and zone representation
B
2. Consider next track3. Find left-to-right ordering of all unassigned nets
If curr_net has no parents and does not cause conflicts on curr_trackassign curr_net
Left-Edge Algorithm – Example
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38
B C E C E B F H I H G I
12
curr_track = 3
4
5
0 A D E A GF 0 D I J J
6.3.1 Left-Edge Algorithm – Example
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curr_track = 4:
C
B
FH
IH
C I
F
Net C Net F Net I
4. Delete placed nets (C, F, I ) in VCG and zone representation
B
2. Consider next track3. Find left-to-right ordering of all unassigned nets
If curr_net has no parents and does not cause conflicts on curr_trackassign curr_net
Left-Edge Algorithm – Example
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40
B C E C E B F H I H G I
12
3
curr_track = 4
5
0 A D E A GF 0 D I J J
Left-Edge Algorithm – Example
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curr_track = 5:
B
H
B H
Net B Net H
4. Delete placed nets (B, H ) in VCG and zone representation
2. Consider next track3. Find left-to-right ordering of all unassigned nets
If curr_net has no parents and does not cause conflicts on curr_trackassign curr_net
Left-Edge Algorithm – Example
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42
B C E C E B F H I H G I
12
3
4
curr_track = 5
Routing result
0 A D E A GF 0 D I J J
Left-Edge Algorithm – Example
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n Improving left-edge algorithm by net splittingn Two advantages:
¨ Alleviates conflicts in VCG¨ Number of tracks can often be reduced
A B B
B 0 A
Net splitting
Dogleg
Dogleg Routing
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A
B
A B B
B 0 A
B A
A B B
Conflict alleviation using a dogleg
Dogleg Routing
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A A B
0 B 0
B 0
C C
A A B
0 B 0
B 0
C C
Track reduction using a dogleg
Dogleg Routing
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n Splitting p-pin nets (p > 2) into p -1 horizontal segments n Net splitting occurs only in columns that contain a pin of the
given netn After net splitting, the algorithm follows the left-edge algorithm
B1 B2
Net splittingA A B
0 B 0
B 0
C C
A
C
Dogleg Routing
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Net splitting
B2B1
C
A
A A B B 0
B 0 C C0
Dogleg Routing
Channel routing problem
A A B B 0
B 0 C C0
VCG without net splitting Channel routing solution
A
B
C
A A B B 0
B 0 C C0
VCG with net splitting
A
B1
B2
C
Channel routing solution
A A B B 0
B 0 C C0
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n Standard cells are placed back-to-back or without routing channelsn Metal layers are usually represented by a coarse routing grid
made up of global routing cells (gcells)
Metal1(Without routing channels)
Metal3
Metal4 etc.
gcells
Metal2 (Cell ports)
Over-the-Cell Routing Algorithms
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n Standard cells are placed back-to-back or without routing channelsn Metal layers are usually represented by a coarse routing grid
made up of global routing cells (gcells)n Layers that are not obstructed by standard cells
are typically used for over-the-cell (OTC) routingn Nets are globally routed using gcells and then detail-routed
Over-the-Cell Routing Algorithms
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Metal3Cell Area
B B
B
B
BC C
CD
Cell Area
Metal1
A A
CMetal2
Over-the-Cell Routing Algorithms
Three-layer approachn Metal3 is used for over-the-cell (OTC) routing
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Metal1
Metal2
Metal3
Channel routing in Metal1, Metal2 and Metal3
OTC routing in Metal3
Ports in Metal2
GND
Standard cell(only ports shown)
Channel
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n Manufacturers today use different configurations of metal layers and widths to accommodate high-performance designs
n Detailed routing is becoming more challenging, for example: ¨ Vias connecting wires of different widths inevitably block additional
routing resources on the layer with the smaller wire pitch ¨ Advanced lithography techniques used in manufacturing require
stricter enforcement of preferred routing direction on each layer
Modern Challenges in Detailed Routing
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n Semiconductor manufacturing yield is a key concern in detailed routing ¨ Redundant vias and wiring segments as backups
(via doubling and non-tree routing)¨ Manufacturability constraints (design rules) become more restrictive¨ Forbidden pitch rules prohibit routing wires at certain distances apart,
but allows smaller or greater spacings
n Detailed routers must account for manufacturing rules and the impact of manufacturing faults ¨ Via defects: via doubling during or after detailed routing ¨ Interconnect defects: add redundant wires to already routed nets ¨ Antenna-induced defects: detailed routers limit the ratio of metal to gate
area on each metal layer
Modern Challenges in Detailed Routing
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Modern Challenges in Detailed Routing
54
Antenna Effect
Source: http://en.wikipedia.org/wiki/Antenna_effect
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Modern Challenges in Detailed Routing
55
Antenna Effect Fix
Source: http://en.wikipedia.org/wiki/Antenna_effect
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Modern challenges in Detail routing
n Redundant Via¨ Via open defect is one of the major cause of failure.¨ Can happen due to random defect, cut misalignment, electro-migration
etc.¨ This significantly reduces yield and in some cases performance
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n Detailed routing is invoked after global routing
n Usually takes about as much time as global routing ¨ For heavily congested designs can take much longer
n Generates specific track assignments for each connection ¨ Tries to follow "suggestions" made by global routing,
but may alter them if necessary ¨ A small number of failed global routed (disconnected, overcapacity)
can be tolerated
n More affected by technology & manufacturing constraints than global routing ¨ Must satisfy design rules
Summary
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n Variable-pitch wire stacks ¨ Not addressed in the literature until 2008
n Satisfying more complex design rules ¨ Min spacing between wires and devices ¨ Forbidden pitch rules ¨ Antenna rules
n Soft rules ¨ Do not need to be satisfied¨ Can improve yield by decreasing the probability of defects
n Redundant vias ¨ In case some vias are poorly manufactured
n Redundant wires ¨ In case some wires get disconnected
Summary – Modern Challenges