Download - Design of Ultra Low Power SRAM
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Design Of Ultra Low Power
SRAMVivek Nautiyal, Ashok Mishra
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Confidential
Agenda
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Why Low Power??
Low power design is one of the key focus area today in very
deep sub-micron designs.
Because CONSUMER want their cell phones to be recharged
only once a week.
Because CONSUMER want to see at least a dozen movies onthe go before they think of recharging it.
Because CONSUMER may sound UNREASONABLE but
can never be wrong
Because we all are driven by WHAT CONSUMER WANTS
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Power Consumption: A Perspective
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Active Power
Leakage Power
Leakage power has transformed itself from a non-issue to nightmare.
Moral of the STORY:
You save little power when you are not talking your on
your mobile phone; better keep talking
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Why Low Power SRAM??
On chip usage of SRAM is
increasing with increasing
processor capacity.
The Power consumed by SRAMs
are significant portion of overall
chip power consumption.
Cache array
PIII chip Snapshot
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Power Components in SRAM
Total power in a CMOS SRAM can be represented by:
Dynamic and short circuit power constitutes the totalactive power.
Dynamic power occurs due to Charge/Discharge of CAPs
Short circuit power occurs during switching of CMOS Txs.
Leakage power occurs primarily due to subthresholdleakage, diode leakage & gate leakage.
Becoming increasingly dominant in deep submicron era.
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Active Power Reduction Techniques
Active Power:
P = .C.V.clk
Active Power can be saved:
1. By reducing activity & amount of switching cap in memory
Banking of memory array into smaller sub-arrays can reduce
both & switching C.
2. By reducing operating voltage
Operating voltage can be reduced, where ever possible.
Introduce voltage islands
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Memory Partitioning
Partition the memory to divide
the overall CAPs into smaller
ones.
Restrict the activity into a
smaller sub-array.
Consider the case of a 64k
density memory arranged in a
single array.
While in operation all the 256bitlines will discharge, with
each bitline routed length equal
to the height of 256 bitcells.
256 rows
256 cols
Bit cell array
Periphery logic
Periphe
rylogic
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128 rows
128 cols
Periphery Logic
Bit cell array
128 rows
128 cols
Bit cell array
128 rows
128 cols
Bit cell array
128 rows
128 cols
Bit cell array
Memory Partitioning
The same memory, divided into 4 sub-arrays.
There would be only 1/4th of BL CAP charge and discharge wrt un-partitioned memory.
Moral of the STORY:
DIVIDEem AND YOU RULE
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Memory Partitioning: DATA
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32768X16m32 16384x8m32 1024x16m32
Monolithic
Two Bank
Four Bank
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Voltage Island
Memory Readability/Writability dictates the minimum operating voltage of
memory.
Periphery can work at lower voltages than memory bit cells.
Create voltage islands: Periphery operates at lower operating voltage than
bit cell array.
Core
Lower Vdd High Vdd
L
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WL
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Periphery
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Voltage Island
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i_read i_write i_leak
32768x16m32,VDDP=VDDC=1.32
32768x16m32,VDDP=1.0, VDDC=1.32
Moral of the story:
BE STINGY, GIVE ONLY AS MUCH AS ONE REALLY
NEEDS
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Leakage Power; The Trouble Infinite
It is a worst kind of nightmare
It comes to fore while sleep
Leakage power poses one of
the biggest challenges as
technology scales.
Primarily three kind of leakage
components:
Sub-threshold Leakage
Gate Leakage
Diode Leakage
Gate Leakage
Gate
Subthreshold
Leakage
Source Drain
Reverse Biased
Junction BTBT
Bulk
n+ n+
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Controlling Leakage
Sub-threshold leakage
Grows exponentially with the
lowering of Vth
Grows exponentially with
increasing T
Grows linearly with total width
of transistors
Gate Leakage Increases exponentially with
decrease of Tox
Can be solved by high-k
materials
Diode Leakage
Leakage proportional todiffusion area
Exponentially sensitive to high
temperature and high voltage
/ /
1 (1 )th
V nkT V kT
subI K We e
2
/
2oxT V
ox
ox
VI K W e
T
, ( 1)qV
kTpn leakage p nI J e A
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Controlling Memory Leakage
The following techniques could be
employed to check leakage in
SRAMs
Multi Vt design (HVT reduces
leakage)
Usage of non-minimum gate length
transistors in design (It increasesthe channel resistance to reduce
leakage)
Back gate biasing (Increased Vt
results in lower leakage)
Power gating to facilitate different
operating voltage modes.
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Multi-Threshold Transistor Design
Use combination of HVT, RVT or LVT transistors in design.
HVT gives lowest leakage, LVT gives highest performance. Carefully analyze critical paths in memory
Use RVT, LVT in critical paths as needed
Use HVT transistors in non critical paths of memory
One can judiciously select high Vt transistors for the devices whichcontribute more towards leakage like core cells and big drivers.
Performance critical circuits such as pre-charges, sense-amplifiers
etc. should use high speed devices.
Moral of the story:
Choose horses for courses, It helps..
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Multi-Threshold Transistor Design: Data
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32768X16m32 16384x8m32 1024x16m32
HVT RVT
RVT Only
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Non-Minimum Gate lengths in design
Non minimum gate lengths results in higher threshold voltages
which in turn reduces leakage.
Just like using HVT transistors in non-critical paths, use bigger
gate length transistors.
Non minimum gate lengths provides better control in hands of
designer over Vt granularity.
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Non-Minimum Gate lengths in design
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Back Gate Biasing
The other way threshold can be raised to reduce leakage is by
body biasing.
During standby, when the memory operation is not going on,
through back gate bias, the threshold of the devices could be
raised.
Using back gate bias during active operation of memory is
pretty complicated to handle
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Power Gating
Power gating is all about controlling supply voltage based on
the state of SRAM. The SRAM can be operated under following modes once
power gating is introduces:
Active Mode : Normal operation
Retention mode : periphery power switched OFF, core supply ON Without power gating : Full core supply
With power gating : Restricted core supply
Sleep mode : All power switched off ; data lost
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Where to gate ????
CORE
RETN
CORE
RETN
CORE
RETN
CORE
RETN
CORE
RETN
RET
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Leakage data with power gating
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32768X16m32 16384x8m32 1024x16m32
Standard
Retention
Power gating
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Design consideration with power gating