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Delayed Branch
All problems solved?
NO, what will happen if......
b loop
add $4 $6 $1
..
.
loop sub
![Page 2: Datorteknik DelayedBranch bild 1 Delayed Branch All problems solved? NO, what will happen if...... b loop add $4 $6 $1... loop sub](https://reader036.vdocuments.site/reader036/viewer/2022062511/551c5b7b5503469d6a8b5125/html5/thumbnails/2.jpg)
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Branch
logic
Sgn/Ze
extend
Zero ext.
ALU
A
B
31
0
4+
+
= =
= =
B loopAdd
![Page 3: Datorteknik DelayedBranch bild 1 Delayed Branch All problems solved? NO, what will happen if...... b loop add $4 $6 $1... loop sub](https://reader036.vdocuments.site/reader036/viewer/2022062511/551c5b7b5503469d6a8b5125/html5/thumbnails/3.jpg)
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Branch
logic
Sgn/Ze
extend
Zero ext.
ALU
A
B
31
0
4+
+
= =
= =
B loopAdd sub
![Page 4: Datorteknik DelayedBranch bild 1 Delayed Branch All problems solved? NO, what will happen if...... b loop add $4 $6 $1... loop sub](https://reader036.vdocuments.site/reader036/viewer/2022062511/551c5b7b5503469d6a8b5125/html5/thumbnails/4.jpg)
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Delayed Branch
- Throughput might decrease, (nop).
- Assembler/Compiler dependent.
+ Keep critical path short
![Page 5: Datorteknik DelayedBranch bild 1 Delayed Branch All problems solved? NO, what will happen if...... b loop add $4 $6 $1... loop sub](https://reader036.vdocuments.site/reader036/viewer/2022062511/551c5b7b5503469d6a8b5125/html5/thumbnails/5.jpg)
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All problems solved now?
NO, what will happen if......
..
bal loop
add $4 $6 $1
xor ....
loop: sub ...
..
j $ra
![Page 6: Datorteknik DelayedBranch bild 1 Delayed Branch All problems solved? NO, what will happen if...... b loop add $4 $6 $1... loop sub](https://reader036.vdocuments.site/reader036/viewer/2022062511/551c5b7b5503469d6a8b5125/html5/thumbnails/6.jpg)
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Branch
logic
Sgn/Ze
extend
Zero ext.
ALU
A
B
31
0
4+
+
= =
= =
> ADDR 0x00400000 bal loop
bal loop
ADDR 0x00400004
![Page 7: Datorteknik DelayedBranch bild 1 Delayed Branch All problems solved? NO, what will happen if...... b loop add $4 $6 $1... loop sub](https://reader036.vdocuments.site/reader036/viewer/2022062511/551c5b7b5503469d6a8b5125/html5/thumbnails/7.jpg)
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Branch
logic
Sgn/Ze
extend
Zero ext.
ALU
A
B
31
0
4+
+
= =
= =
ADDR 0x00400000 bal loop
> ADDR 0x00400004 add
ADDR 0x00400004
bal loopadd
![Page 8: Datorteknik DelayedBranch bild 1 Delayed Branch All problems solved? NO, what will happen if...... b loop add $4 $6 $1... loop sub](https://reader036.vdocuments.site/reader036/viewer/2022062511/551c5b7b5503469d6a8b5125/html5/thumbnails/8.jpg)
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Branch
logic
Sgn/Ze
extend
Zero ext.
ALU
A
B
31
0
4+
+
= =
= =
ADDR 0x00400004
ADDR 0x00400004
bal loopadd
ADDR 0x00400000 bal loop
ADDR 0x00400004 add >loop: sub
sub
![Page 9: Datorteknik DelayedBranch bild 1 Delayed Branch All problems solved? NO, what will happen if...... b loop add $4 $6 $1... loop sub](https://reader036.vdocuments.site/reader036/viewer/2022062511/551c5b7b5503469d6a8b5125/html5/thumbnails/9.jpg)
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Branch
logic
Sgn/Ze
extend
Zero ext.
sub
.. .. j $ra
ALU
A
B
31
0
4+
+
= =
= =
ADDR 0x00400004
jr $ra
![Page 10: Datorteknik DelayedBranch bild 1 Delayed Branch All problems solved? NO, what will happen if...... b loop add $4 $6 $1... loop sub](https://reader036.vdocuments.site/reader036/viewer/2022062511/551c5b7b5503469d6a8b5125/html5/thumbnails/10.jpg)
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Branch
logic
Sgn/Ze
extend
Zero ext.
Oooh not again!!!
ALU
A
B
31
0
4+
+
= =
= =
0x00400004 add
![Page 11: Datorteknik DelayedBranch bild 1 Delayed Branch All problems solved? NO, what will happen if...... b loop add $4 $6 $1... loop sub](https://reader036.vdocuments.site/reader036/viewer/2022062511/551c5b7b5503469d6a8b5125/html5/thumbnails/11.jpg)
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Branch
logic
Sgn/Ze
extend
Zero ext.
ALU
A
B
31
4
4+
+
= =
= =
ADDR 0x00400004
ADDR 0x00400008
Continue at 0x00400008bal loopadd sub
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Branch
logic
Sgn/Ze
extend
Zero ext.
sub
.. .. j $ra
ALU
A
B
31
0
4+
+
= =
= =
ADDR 0x00400008
jr $ra
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All Hazards Fixed but:
One “delayed branch” slot
![Page 14: Datorteknik DelayedBranch bild 1 Delayed Branch All problems solved? NO, what will happen if...... b loop add $4 $6 $1... loop sub](https://reader036.vdocuments.site/reader036/viewer/2022062511/551c5b7b5503469d6a8b5125/html5/thumbnails/14.jpg)
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What about “delayed Branch”
Can we avoid it? How?
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IM
Reg DM Reg
Delayed Branch
Direct Branch
BranchLogic
IM
Reg DM Reg
BranchLogic
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Branch
logic
Sgn/Ze
extend
Zero ext.
ALU
A
B
31
0
4+
+
= =
= =
Delayed Branch
![Page 17: Datorteknik DelayedBranch bild 1 Delayed Branch All problems solved? NO, what will happen if...... b loop add $4 $6 $1... loop sub](https://reader036.vdocuments.site/reader036/viewer/2022062511/551c5b7b5503469d6a8b5125/html5/thumbnails/17.jpg)
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Branch
logic
Sgn/Ze
extend
Zero ext.
ALU
A
B
31
0
4+
+
= =
= =
Branch
logic
Direct Branch
![Page 18: Datorteknik DelayedBranch bild 1 Delayed Branch All problems solved? NO, what will happen if...... b loop add $4 $6 $1... loop sub](https://reader036.vdocuments.site/reader036/viewer/2022062511/551c5b7b5503469d6a8b5125/html5/thumbnails/18.jpg)
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What about the instruction set?
beq $t0 $t0 label? jr $ra? NO, DE is not in path! b label? OK, but the new branch logic needs an ALU
to compute the address
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Different branch logic?
Can both branch types coexist? Yes, no problem, but: Old type still uses “delay slot”