DAC - Digital to Analog ConversionADC - Analog to Digital Conversion
RS485 - Modbus
Digital To Analog Converter
To output analog voltage from a PC or µC, the numerical value(integer) must be converted to the analog voltage equivalent bya D/A converter. Analog outputs are much simpler than analoginputs. This process is very fast, and does not experience thetiming problems of sampling and conversion with analog inputs.However, analog outputs are still subject to quantization errors.
DAC - Digital to Analog ConversionADC - Analog to Digital Conversion
RS485 - Modbus
Weighted Resistor Summing DAC
Develop an analytical model for 3-bit DAC output in terms of theresistances, reference voltage and the switch positions.
DAC - Digital to Analog ConversionADC - Analog to Digital Conversion
RS485 - Modbus
Ladder Resistor Network DAC
2R
2R
2R
R
Vr
A1
A0
Vo
V o
R 1
R 2
R 3
R4
R5
R6
21
A 2
3
21
A 1
3
21
A 0
3
+-G
1
2 R
2 R
2 R
2R
RR
S W
S W
S W
BA
T
G N D
Ex: Develop a model for 2-bit DAC output, via superposition.Prelab L1-1: Develop an analytical model for 3-bit DAC outputin terms of the R-2R resistances, reference voltages and theswitch positions.Prelab L1-2: Develop a model for the switch currents.Prelab L1-3: Install Arduino IDE ∼masek/arduino01.pdf
DAC - Digital to Analog ConversionADC - Analog to Digital Conversion
RS485 - Modbus
Ladder Resistor Network DAC - cont’d
Solution to Prelab L1-1:
v0
Vref=
R22 + 5R1R2 + 2R2
1
4R22 + 7R1R2 + 2R2
1D2 +
+R2(R2 + 2R1)
4R22 + 7R1R2 + 2R2
1D1 +
+R2
2
4R22 + 7R1R2 + 2R2
1D0
DAC - Digital to Analog ConversionADC - Analog to Digital Conversion
RS485 - Modbus
Ladder Resistor Network DAC - cont’d
Test of the solution to Prelab L1-1:
R2 = 2R1
v0
Vref=
D2
2+
D1
4+
D0
8
DAC - Digital to Analog ConversionADC - Analog to Digital Conversion
RS485 - Modbus
Uncertainty
Maximum uncertainty1:
∆MAXVDAC
=
∣∣∣∣∂VDAC
∂R1
∣∣∣∣∆R1 +
∣∣∣∣∂VDAC
∂R2
∣∣∣∣∆R2 + . . .+
∣∣∣∣∂VDAC
∂RN
∣∣∣∣∆RN
Probable uncertainty2:
∆PROBVDAC
=
√(∂VDAC
∂R1∆R1
)2
+
(∂VDAC
∂R2∆R2
)2
+ . . .+
(∂VDAC
∂RN∆RN
)2
Assignment A1-1,2: Calculate DAC uncertainty for both, (1)3-bit Weighted Resistor Summing DAC and (2) 3-bit LadderResistor Network DAC, assuming 1% tolerances.
1represents the worst case uncertainty2represents a more realistic uncertainty
DAC - Digital to Analog ConversionADC - Analog to Digital Conversion
RS485 - Modbus
A1-1 Solution
Vo = −(RR2
D2 +RR4
D1 +RR8
D0)VR
∆MAXVo
∣∣∣D0=D1=D2=1
=
∣∣∣∣ RR2
VR
∣∣∣∣ ∆R2
R2+
∣∣∣∣ RR4
VR
∣∣∣∣ ∆R4
R4+
∣∣∣∣ RR8
VR
∣∣∣∣ ∆R8
R8
∆MAXVo
= (12× 1% +
14× 1% +
18× 1%)VR
∆MAXVo
=78× 1%VR=0.87%VR
DAC - Digital to Analog ConversionADC - Analog to Digital Conversion
RS485 - Modbus
A1-2 Solution
∆MAXVo
∣∣∣D0=D1=D2=1
=
∣∣∣∣ R22(7R2 + 4R1)
(4R22 + 7R1R2 + 2R2
1)2VR
∣∣∣∣∆R1 +
+
∣∣∣∣ R1R2(7R2 + 4R1)
(4R22 + 7R1R2 + 2R2
1)2VR
∣∣∣∣∆R2
∆MAXVo
∣∣∣R2=2R1
= (9
128×
∆R1
R1+
9256×
∆R2
R1)VR
∆MAXVo
∣∣∣R2=2R1
= (9
128×
∆R1
R1+
9128×
∆R2
2R1)VR
∆MAXVo
=9
64× 1%VR=0.14%VR
The three bit R-2R DAC exhibits over six times less uncertaintyin comparison to the three bit weighted resistor DAC.
DAC - Digital to Analog ConversionADC - Analog to Digital Conversion
RS485 - Modbus
PWM to Voltage - filter design
Required Attenuation in terms of the ripple voltage:
AdB = 20× logVRIP
VPWM(1)
Required Attenuation in terms of the slope S (-20, -40, ...):
AdB = S × logfPWM
f3dB(2)
f3dB = fPWM × 10−AdBS (3)
RC filter:f3dB =
12π × RF × CF
(4)
DAC - Digital to Analog ConversionADC - Analog to Digital Conversion
RS485 - Modbus
PWM to Voltage - filter design cont’d
DAC - Digital to Analog ConversionADC - Analog to Digital Conversion
RS485 - Modbus
PWM to Voltage - IC
MILPITAS, CA - August 12, 2014 - Linear TechnologyCorporation introduces the LTC2645, a quad-channel12-bit/10-bit/8-bit PWM-to-voltage output digital-to-analogconverter (DAC) with 10ppm/A◦C reference. These partsconvert PWM input signals to 12-bit accurate, stable, bufferedvoltage outputs in less than 8 microseconds, eliminating theripple and delay typically associated with analog filters. ...
The LTC2645 measures the period and pulse width of the PWM inputsignals and updates the DACs after each PWM input rising edge,accepting PWM input frequencies from 30Hz up to 100kHz. AnIDLSEL pin provides flexibility to set the outputs to idle at zero or fullscale, power-down with high-impedance output, or hold the previousstate indefinitely in response to an idle PWM input. This convenientmode has the advantage over analog filter implementations, whichrequire the PWM to run continuously.
DAC - Digital to Analog ConversionADC - Analog to Digital Conversion
RS485 - Modbus
Analog to Digital Conversion - definitions
To input an analog voltage into a PC or µcontroller, thecontinuous voltage value must be first sampled and thenconverted to a numerical value by an A/D converter.
The process of sampling the data is not instantaneous, soeach sample has a start and stop time. The time requiredto acquire the sample is called the sampling time ts.A/D converters can only acquire a limited number ofsamples per second. The time between samples is calledthe sampling period TS, and the inverse of the samplingperiod is the sampling frequency/rate. Ts < TSThe maximum Vmax and minimum Vmin readable voltagesare a function of the control hardware such as 0V to 5V.The number of bits of the A/D converter is the number ofbits in the result word. If the A/D converter is 8 bit then theresult can read up to 256 different voltage levels.
DAC - Digital to Analog ConversionADC - Analog to Digital Conversion
RS485 - Modbus
Sampling
Sample & Hold (S/H) circuitry takes a snapshot of the inputsignal and holds the value for the A/D converter to have a stablesignal. Often a FET switch connects capacitor to buffered inputat the beginning of every sample period. The capacitor thenholds the voltage value sampled until a new sample is acquired.This voltage slowly decreases over time despite of the highimpedance output buffer. It is then necessary to perform theA/D conversion quickly in a short period of time.
DAC - Digital to Analog ConversionADC - Analog to Digital Conversion
RS485 - Modbus
S&H Chopper Circuit
DAC - Digital to Analog ConversionADC - Analog to Digital Conversion
RS485 - Modbus
Flash ADC
consist of a set of comparators and reference voltages,and a digital encodertypically 4 to 8 bit designs due to the required number ofcomparatorsfast scanning ratestypically used in TV, fast measurement instrumentsoften a bubble error correction is applied prior to digitalencoding
DAC - Digital to Analog ConversionADC - Analog to Digital Conversion
RS485 - Modbus
Successive Approximation ADC
> 7.5> 7
< 6.5> 6
> 5.5< 5
< 4.54
> 3.5> 3
< 2.5< 2
> 1.5< 1
< 0.5MSB 22 21 LSB 20 ±0.5V = LSB/2
DAC - Digital to Analog ConversionADC - Analog to Digital Conversion
RS485 - Modbus
Timer/Counter based ADC’sRC network with a comparator
VC = VR(1− e− tτ )
τ = RC
Charging a capacitor method is a simple time-interval basedtechnique, however, the accuracy is low due to non-linearity,and VR / RC stability.
DAC - Digital to Analog ConversionADC - Analog to Digital Conversion
RS485 - Modbus
Timer/Counter based ADC’s - cont’dDual Slope Integrating ADC
applications that do not require high speed samplingimmune to non-linearity of the integratorcan be very accurate provided a longer time of conversionis acceptable
An integrator is the core element in the dual-slope ADC. Azeroed integrator (Vint = 0) is first connected to the measuredvoltage VS&H for a fixed time duration (run-up time T1 =const).This causes the integrator to wind up to a certain voltage, sayV u
int . Then a fixed reference voltage VR of the opposite polaritythan VS&H is connected to the integrator which causes theintegrator to back-integrate from V u
int to zero voltage. Thisphase is often referred to as run-down phase of time durationT2.
DAC - Digital to Analog ConversionADC - Analog to Digital Conversion
RS485 - Modbus
Timer/Counter based ADC’s - cont’dDual Slope Integrating ADC - SUMMARY
Two voltage signal integration phases:1 integration of the input voltage VS&H over a constant time
period T1 starting at zero (0V)2 (back) integration of the constant reference voltage VR over
a variable time T2 until zero level crossing occurs (0V)
Using a ratiometric method, the non-linearity and drift ofRC is not critical as was the case of RC network ADC or asingle slope ADC.
VS&H = VR ×T2
T1(5)
DAC - Digital to Analog ConversionADC - Analog to Digital Conversion
RS485 - Modbus
Assignment II.
1 Specify all components in the dual slope ADC circuit anddefine the timing sequence of control lines S-H, RES, INT,DEINT.
2 Simulate the analog to digital conversion using SPICEtransient analysis and provide these waveforms: S-H(t),RES(t), INT(t), DEINT(t), VINT (t), COMP(t).
3 Propose a solution to minimize the transient ’spikes’ at theintegrator’s input.
4 Derive an expression for the measured voltage in terms ofthe design parameters and the measured time ofde-integration.
DAC - Digital to Analog ConversionADC - Analog to Digital Conversion
RS485 - Modbus
Assignment II. - cont’d
Four digital outputs are required to control the conversionprocess assuming only uni-polar voltage being measured. Onedigital output controls S&H operation, two digital outputs controlswitching of VS&H and VR to the integrator input, and one digitaloutput is used to discharge the capacitor at the beginning ofeach conversion cycle.
LTspice: ∼masek/dual-slope-ADC.asc
DAC - Digital to Analog ConversionADC - Analog to Digital Conversion
RS485 - Modbus
Assignment II. - solution