Download - CS 162 Discussion Section Week 6
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CS 162Discussion Section
Week 6
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Administrivia
• Project 2 Deadlines– Initial Design Due: 3/1– Review Due: 3/5– Code Due: 3/15
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Project 2 Overview
• Part I – Implement file system calls– like create, open, read, write, close etc.
• Part II – Implement support for multiprogramming– Play with allocating memory, virtual memory
• Part III – Implement system calls– like exec, join and exit
• Part IV – Implement lottery scheduling
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Recap
Why do we have a virtual address space?
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Recap
How is a virtual address translated into a physical address?
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Recap
Why do we have multiple levels of page tables?
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What is the size of the page table in a 64bit system if each
page is 4K in size? – 16 PB
How many levels would you need if you had 1024 entry
page tables?
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TLB
• Caching Applied to Address Translation
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Caching
• caching is to store copies of data at places that can be accessed more quickly than accessing the original.
• Locality:– Temporal locality• Example: recently accessed files
– Spatial locality• Example: ls command
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Memory Hierarchy
Image Source: http://www.sal.ksu.edu/faculty/tim/ossg/
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Issues in Caching
• Cache Hit• Cache Miss• effective access time is defined with the
following equation:
T = P(cache hit)*(cost of hit) + P(cache miss)*(cost of miss)
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Problem
What is the effective access time for TLB with 80% hit rate, 20ns TLB access time and 100 ns Memory access time (assume two-level page table that is not in L2 cache)?
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Is there any way to make the page table smaller?
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Linear inverted page tables
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Hashed inverted page table
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Hashed inverted page table
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Design Issues in Caching
• The design of a caching mechanism needs to answer the following questions:
– How is a cache entry lookup performed? – If the data is not in the cache, which cache entry
should be replaced? – How does the cache copy maintain consistency with
the real version of data?
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Types of Cache
• Direct Mapped Cache• Fully Associative Cache• N way Set Associative Cache
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2-Way Associative Cache in TLB