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Instructor: Alexander Stoytchev
http://www.ece.iastate.edu/~alexs/classes/
CprE 281: Digital Logic
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T Flip-Flops &
JK Flip-Flops
CprE 281: Digital LogicIowa State University, Ames, IACopyright © Alexander Stoytchev
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Administrative Stuff
• Homework 8 is due next Monday.
• The second midterm exam is next Friday.
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Administrative Stuff• Midterm Exam #2
• When: Friday November 1 @ 4pm.
• Where: This classroom
• What: Chapters 1, 2, 3, 4 and 5.1-5.8
• The exam will be closed book but open notes (you can bring up to 3 pages of handwritten notes).
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Midterm 2: Format
• The exam will be out of 130 points
• You need 95 points to get an A for this exam
• It will be great if you can score more than 100 points.§ but you can’t roll over your extra points L
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Midterm 2: Topics
• Binary Numbers and Hexadecimal Numbers• 1’s complement and 2’s complement representation• Addition and subtraction of binary numbers• Circuits for adders and fast adders
• Single and Double precision IEEE floating point formats• Converting a real number to the IEEE format• Converting a floating point number to base 10
• Multiplexers (circuits and function)• Synthesis of logic functions using multiplexers• Shannon’s Expansion Theorem
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Midterm 2: Topics• Decoders (circuits and function)• Demultiplexers• Encoders (binary and priority)• Code Converters• K-maps for 2, 3, and 4 variables
• Synthesis of logic circuits using adders, multiplexers, encoders, decoders, and basic logic gates
• Synthesis of logic circuits given constraints on the available building blocks that you can use
• Latches (circuits, behavior, timing diagrams)• Flip-Flops (circuits, behavior, timing diagrams)• Registers and Register Files
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T Flip-Flop
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Motivation
A slight modification of the D flip-flop that can be used for some nice applications.
In this case, T stands for Toggle.
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[ Figure 5.15a from the textbook ]
T Flip-Flop
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[ Figure 5.15a from the textbook ]
T Flip-Flop
Positive-edge-triggered D Flip-Flop
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[ Figure 5.15a from the textbook ]
T Flip-Flop
What is this?
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What is this?
Q
Q
TD
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It is a 2-to-1 Multiplexer
Q
Q
TD
T
D
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What is this?
T
D
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T
0
1 D Q
Q Clock
It is a T Flip-Flop
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T
0
1 D Q
Q Clock
It is a T Flip-Flop
Q
Q
Note that the two inputs to the multiplexer are inverses of each other.
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T
0
1 D Q
Q Clock
Another Way to Draw This
Q
Q
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T
0
1 D Q
Q Clock
Another Way to Draw This
Q
Q
What is this?
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What is this?
Q
T
D
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What is this?
Q
T
D
D = QT + QT
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It is an XOR
Q
T
D
D = Q + T
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DQT
It is an XOR
D = Q + T
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What is this?
+ = ?
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T D Q
Q Clock
It is a T Flip-Flop too
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T Q D
0 0 00 1 11 0 11 1 0
T D Q
Q Clock
It is a T Flip-Flop too
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T D Q
Q Clock
It is a T Flip-Flop too
T Q D
0 0 00 1 11 0 11 1 0
Q
Q
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If T=0 then it stays in its current state
If T=1 then it reverses its current state
In other words the circuit “toggles” its state when T=1. This is why it is called T flip-flop.
T Flip-Flop(how it works)
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[ Figure 5.15a,b from the textbook ]
T Flip-Flop(circuit and truth table)
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[ Figure 5.15a,c from the textbook ]
T Flip-Flop(circuit and graphical symbol)
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[ Figure 5.15d from the textbook ]
T Flip-Flop (Timing Diagram)
1
10
01 1
1
011
1
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[ Figure 5.15d from the textbook ]
1
10
01 1
1
011
0
1
Decision Point
T Flip-Flop (Timing Diagram)
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[ Figure 5.15d from the textbook ]
1
10
01 1
1
011
0
1
T Flip-Flop (Timing Diagram)
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[ Figure 5.15d from the textbook ]
1
10
01 1
1
011
0
1
T Flip-Flop (Timing Diagram)
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[ Figure 5.15d from the textbook ]
1
10
01 1
1
011
0
1
T Flip-Flop (Timing Diagram)
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JK Flip-Flop
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[ Figure 5.16a from the textbook ]
JK Flip-Flop
D = JQ + KQ
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[ Figure 5.16 from the textbook ]
JK Flip-Flop
J Q
Q
K01
Q t 1+( )Q t( )
0
(b) Truth table (c) Graphical symbol
J00
0 111 Q t( )1
K
D Q
Q
Q
Q
J
Clock
(a) Circuit
K
Hold
Reset
Set
Toggle
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JK Flip-Flop(how it works)
A versatile circuit that can be used both as aSR flip-flop and as a T flip flop
If J=0 and S =0 it stays in the same state
Just like SR It can be set and reset J=S and K=R
If J=K=1 then it behaves as a T flip-flop
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JK Flip-Flop(timing diagram)
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JK Flip-Flop(timing diagram)
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JK Flip-Flop(timing diagram)
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JK Flip-Flop(timing diagram)
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Complete Wiring Diagrams
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Positive-Edge-Triggered D Flip-Flop
![Page 46: CprE 281: Digital Logic - Computer EngineeringToggle. JK Flip-Flop (how it works) A versatile circuit that can be used both as a SR flip-flop and as a T flip flop If J=0 and S =0 it](https://reader035.vdocuments.site/reader035/viewer/2022070111/6050f4530f33fb364021cbc9/html5/thumbnails/46.jpg)
Negative-Edge-Triggered D Flip-Flop
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The Complete Wiring Diagram for a Positive-Edge-Triggered D Flip-Flop
D
Clock
Q
Q
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The Complete Wiring Diagram for a Negative-Edge-Triggered D Flip-Flop
Q
Q
D
Clock
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The Complete Wiring Diagram for a Negative-Edge-Triggered D Flip-Flop
Q
Q
D
Clock
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T D Q
Q Clock
Positive-Edge-Triggered T Flip-Flop
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Negative-Edge-Triggered T Flip-Flop
T D Q
Q Clock
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The Complete Wiring Diagram for a Positive-Edge-Triggered D Flip-Flop
T
Clock
Q
Q
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The Complete Wiring Diagram for a Negative-Edge-Triggered D Flip-Flop
T
Clock
Q
Q
![Page 54: CprE 281: Digital Logic - Computer EngineeringToggle. JK Flip-Flop (how it works) A versatile circuit that can be used both as a SR flip-flop and as a T flip flop If J=0 and S =0 it](https://reader035.vdocuments.site/reader035/viewer/2022070111/6050f4530f33fb364021cbc9/html5/thumbnails/54.jpg)
D Q
Q
Q
Q
J
Clock
K
Positive-Edge-Triggered JK Flip-Flop
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D Q
Q
Q
Q
J
Clock
K
Negative-Edge-Triggered JK Flip-Flop
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The Complete Wiring Diagram for a Positive-Edge-Triggered JK Flip-Flop
Q
Q
Clock
J
K
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The Complete Wiring Diagram for a Negative-Edge-Triggered JK Flip-Flop
Q
Q
Clock
J
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Questions?
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THE END