Download - Computer Organization - Gordon College
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Slide 4-1
Computer Organization
Slide 4-2Stored Program Computers andElectronic Devices
Pattern
Fixed Electronic Device
VariableProgram
Stored Program Device
Jacquard Loom
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Slide 4-3Program Specification
int a, b, c, d;. . .a = b + c;d = a - 100;
Source
; Code for a = b + c load R3,b load R4,c add R3,R4 store R3,a
; Code for d = a - 100 load R4,=100 subtract R3,R4 store R3,d
Assembly Language
Slide 4-4Machine Language
; Code for a = b + c load R3,b load R4,c add R3,R4 store R3,a
; Code for d = a - 100 load R4,=100 subtract R3,R4 store R3,d
Assembly Language
10111001001100…110111001010000…010100111001100…010111010001100…110111001010000…010100110001100…010111001101100…1
Machine Language
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Slide 4-5The von Neumann Architecture
Control Unit(CU)
Central Processing Unit (CPU)
Device
Address BusData Bus
Arithmetical Logical Unit(ALU)
Primary Memory Unit(Executable
Memory)
Slide 4-6The ALU
R1R2
Rn. . .
Status RegistersFunctional Unit
Left OperandRight Operand
Result
To/from Primary Memory
load R3,bload R4,cadd R3,R4store R3,a
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Slide 4-7Control Unit
3046305030543058
Primary Memory
Fetch Unit
Decode Unit
Execute Unit
PC
IR
Control Unit
load R3,bload R4,cadd R3,R4store R3,a
10111001001100…110111001010000…010100111001100…010111010001100…1load R4, c
3050
Slide 4-8Control Unit Operation
PC = <machine start address>;IR = memory[PC];haltFlag = CLEAR;while(haltFlag not SET) { execute(IR); PC = PC + sizeof(INSTRUCT); IR = memory[PC]; // fetch phase};
• Fetch phase: Instruction retrieved frommemory
• Execute phase: ALU op, memory datareference, I/O, etc.
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Slide 4-9Primary Memory Unit
MAR
MDR
Command
012
n-1
1234 98765Read Op:
1234
1. Load MAR with address
read
2. Load Command with “read”
98765
3. Data will then appear in the MDR
Slide 4-10The Device-Controller-SoftwareRelationship
Application Program
Device Controller
Device
Softw
are
in th
e C
PU
Abstract I/O Machine
•Device manager•Program to manage device controller•Supervisor mode software
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Slide 4-11Device Controller Interface
Command Status Data 0
Data 1
Data n-1Logic
busy done Error code . . .. . .busy done 0 0 idle 0 1 finished 1 0 working 1 1 (undefined)
Busy/done bits used to signal event occurrences to software andsoftware to device
Slide 4-12Performing a Write Operation
while(deviceNo.busy || deviceNo.done) <waiting>;deviceNo.data[0] = <value to write>deviceNo.command = WRITE;while(deviceNo.busy) <waiting>;deviceNo.done = TRUE;
• Devices much slower than CPU• CPU waits while device operates• Would like to multiplex CPU to a different
process while I/O is in process
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Slide 4-13CPU-I/O Overlap
CPU
Device
…
Rea
dy P
roce
sses
CPU
Device
…
Rea
dy P
roce
sses
I/O Operation
CPU
Device
…
Rea
dy P
roce
sses
Uses CPU
Slide 4-14
Determining When I/O is Complete
CPU
Device Device Device
Interrupt Pending
• CPU incorporates an “interrupt pending” flag• When device.busy → FALSE, interrupt pending flag is set• Hardware “tells” OS that the interrupt occurred• Interrupt handler part of the OS makes process ready to run
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Slide 4-15Control Unit with Interrupt(Hardware)
PC = <machine start address>;IR = memory[PC];haltFlag = CLEAR;while(haltFlag not SET) { execute(IR); PC = PC + sizeof(INSTRUCT); IR = memory[PC]; if(InterruptRequest) { memory[0] = PC; PC = memory[1]};
memory[1] contains the address of the interrupt handler
Slide 4-16Interrupt Handler (Software)
interruptHandler() { saveProcessorState(); for(i=0; i<NumberOfDevices; i++) if(device[i].done) goto deviceHandler(i); /* something wrong if we get to here … */
deviceHandler(int i) { finishOperation(); returnToScheduler();}
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Slide 4-17A Race Condition
saveProcessorState() { for(i=0; i<NumberOfRegisters; i++) memory[K+i] = R[i]; for(i=0; i<NumberOfStatusRegisters; i++) memory[K+NumberOfRegisters+i] = StatusRegister[i];}
PC = <machine start address>;IR = memory[PC];haltFlag = CLEAR;while(haltFlag not SET) { execute(IR); PC = PC + sizeof(INSTRUCT); IR = memory[PC]; if(InterruptRequest && InterruptEnabled) { disableInterupts(); memory[0] = PC; PC = memory[1]};
What happens if a secondinterrupt comes in the middleof the first?
Block other interruptwhile processing first
Slide 4-18
Revisiting the trap Instruction(Hardware)
executeTrap(argument) { setMode(supervisor); switch(argument) { case 1: PC = memory[1001]; // Trap handler 1 case 2: PC = memory[1002]; // Trap handler 2 . . . case n: PC = memory[1000+n];// Trap handler n};
• The trap instruction dispatches a traphandler routine atomically
• Trap handler performs desired processing• “A trap is a software interrupt”
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Slide 4-19Direct Memory Access
PrimaryMemory
CPU
Controller
Device
PrimaryMemory
CPU
Controller
Device
Slide 4-20Addressing Devices
PrimaryMemory
Device 0
Device 1
Device n-1
PrimaryMemory
Device 0
Device 1
Device n-1
Dev
ice
Add
ress
esM
emor
y A
ddre
sses
Mem
ory
Add
ress
es
copy-in R3, 0x012, 4 Load R3, 0xFFFF0124
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Slide 4-21Polling I/O…// Start the device…While((busy == 1) || (done == 1)) wait();// Device I/O complete…done = 0;
…while((busy == 0) && (done == 1)) wait();// Do the I/O operationbusy = 1;…
busy done
Softw
are
Har
dwar
e
Slide 4-22Fetch-Execute Cycle with an Interrupt
while (haltFlag not set during execution) { IR = memory[PC]; PC = PC + 1; execute(IR); if (InterruptRequest) { /* Interrupt the current process */ /* Save the current PC in address 0 */ memory[0] = PC; /* Branch indirect through address 1 */ PC = memory[1]; }}
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Slide 4-23Detecting an Interrupt
CPU
Device Device Device
InterruptRequest flag
Slide 4-24The Interrupt Handler
Interrupt_Handler{ saveProcessorState(); for (i=0; i<Number_of_devices; i++) if (device[i].done == 1) goto device_handler(i); /* Something wrong if we get here */}
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Slide 4-25Disabling Interrupts
if(InterruptRequest && InterruptEnabled) {/* Interrupt current process */ disableInterrupts(); memory[0] = PC; PC = memory[1];}
Slide 4-26The Trap Instruction Operation
SMode
TrustedCode
trap
User Supervisor
Branch Table
2
3
1
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Slide 4-27Intel System Initialization
ROM
CMOS
RAM
Boot DevicePOST
BIOS
Boot Prog
Loader
OS…Hardware Process
Data Flow
Power Up
Slide 4-28Bootstrapping
Bootstrap loader (“boot sector”)
Primary Memory
1
0x0001000
Fetch Unit
Decode Unit
Execute Unit
0000100
…
PC
IR
BIOS loader 0x0000100
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Slide 4-29
BootstrappingBootstrap loader (“boot sector”)
Primary Memory
Loader
1
2
Fetch Unit
Decode Unit
Execute Unit
0001000
…
PC
IR
BIOS loader 0x00001000x0001000
0x0008000
Slide 4-30
BootstrappingBootstrap loader (“boot sector”)
Primary Memory
Loader
OS
12
3Fetch Unit
Decode Unit
Execute Unit
0008000
…
PC
IR
BIOS loader 0x00001000x0001000
0x0008000
0x000A000
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Slide 4-31Bootstrapping
Bootstrap loader (“boot sector”)
Primary Memory
Loader
OS
12
3
4. Initialize hardware5. Create user environment6. …
Fetch Unit
Decode Unit
Execute Unit
000A000
…
PC
IR
BIOS loader 0x00001000x0001000
0x0008000
0x000A000
Slide 4-32A Bootstrap Loader Program
FIXED_LOC: // Bootstrap loader entry pointload R1, =0load R2, =LENGTH_OF_TARGET
// The next instruction is really more like // a procedure call than a machine instruction// It copies a block from FIXED_DISK_ADDRESS// to BUFFER_ADDRESS
read BOOT_DISK, BUFFER_ADDRESSloop: load R3, [BUFFER_ADDRESS, R1]
store R3, [FIXED_DEST, R1]incr R1bleq R1, R2, loopbr FIXED_DEST
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Slide 4-33A Pipelined Function Unit
Function UnitOperand 1Operand 2
Result
Operand 1Operand 2
Result
(a) Monolithic Unit
(b) Pipelined Unit
Slide 4-34A SIMD MachineALU Control
Unit
ALU ControlUnit
ALU
ALU
ALU
…
(a) Conventional Architecture
(b) SIMD Architecture