0CIC National Science CouncilCh ip Implem entation Center
CIC 訓練課程
Layout Verification with DraculaTraining Manual
國科會國家晶片系統設計中心
1CIC National Science CouncilCh ip Implem entation Center
Objectives of Course
• Know the concept of layout verification
• Familiar with running Dracula 4.7• Capability of reading a command file
• Learn to debug your design
• Modify command file according to design’s need
2CIC National Science CouncilCh ip Implem entation Center
Contents1. Introduction2. Structure of Command File3. Layer Processing4. Design Rule Check5. Device Extraction6. Electrical Rule Check7. Layout vs. Schematic Check8. Layout Parameter Extraction9. Parasitic Resistance Extraction
10. Extraction Interface and Reduction
3CIC National Science CouncilCh ip Implem entation Center
Design FlowsSystem
Specification
Behavior Design
Structure Design
Synthesis
sim / correct
P & RData insim / correct
Lay editLayout
Verification post-sim
Manufacture
Package
Testing
CellLibrary
Deviceparameter
Processrule
4CIC National Science CouncilCh ip Implem entation Center
The Need of Layout Verification
• Functional Design verification is only for designer • Physical design must meet process rules for manufacture
reliability• Even commercial placement & route tool can introduce error • Converting layout database to foundry acceptable format
may introduce error• The performance of design after layout need to be verified
5CIC National Science CouncilCh ip Implem entation Center
Layout Verification
• DRC(Design Rule Check):checks physical layout data against fabrication-specific rules
• ERC(Electrical Rule Check):checks for electrical violations• LVS(Layout Versus Schematic):checks the connectivity of a
physical layout design to its related schematic• LPE(Layout Parasitic Extraction): extracts the parasitic effect
resulted from the interconnection of layout design• PRE(Parasitic Resistance Extraction):extracts the parasitic
resistance resulted from interconnection of layout design• InQuery:a graphic tool which is used to analysis the violations
of Dracula verification
6CIC National Science CouncilCh ip Implem entation Center
Basic of Layout Verification• Layout verification is process dependent
Need a database for describing process information• Input for layout verification
layout database - GDS2 format (CIF , Cadence )netlist information (For LVS / backannotated LPE)process specified information
• Layout Verification
Incremental vs Full chipHierarchical vs Flattenonline vs offline
7CIC National Science CouncilCh ip Implem entation Center
Commercial Verification Tools
• CadenceDracula, Vampire, DIVA(online)
• Avanti Corp.Hercules
• MentorCalibre, Xcalibre(extraction)
• TannerDRC(online), LVS
8CIC National Science CouncilCh ip Implem entation Center
What is Dracula ?
吸 血 鬼 ?吸 血 鬼 ?
IC Verification tools for
Design Rule Check(DRC)Electrical Rule Check(ERC)Layout v.s. Schematic cross check(LVS)Layout Parasitic Extraction(LPE)Layout plotting(PLOT)Pattern Generation(PG/E)
9CIC National Science CouncilCh ip Implem entation Center
What is Dracula ?(cont’d)
• Dracula is not a command, it is a tool. • The operation of verification is guided by command file.• Command file is a ASCII file containing Dracula rules used to
perform IC verification.• The execution of Dracula consists of a sequence of commands
(they are gathered in a file thus named command file).• Dracula use disk files as intermediate data• Dracula is not truly hierarchical, the basic mode is flatten mode.
10CIC National Science CouncilCh ip Implem entation Center
Why Needs Dracula ?
• Final sign-off for the hand-out data• Need a tool for double check over DIVA(interactive check)• Need a widely used and reliable verification tool• Need a tool with acceptable runtime and resource usage for
whole chip verification
11CIC National Science CouncilCh ip Implem entation Center
How to Use Dracula
• Create/Obtain command files• Fill in design database information• Compile the command files• Submit the run file• Consult the checked reports and correct the violations
12CIC National Science CouncilCh ip Implem entation Center
Internal Flow
LayoutDatabase
DRC
DeviceExtract
ERC
LPE/PRE
LVS
Textand
GraphicError
Reports
NetlistDatabase
13CIC National Science CouncilCh ip Implem entation Center
Operational Overview
Layout database
Netlistdatabase
LOGLVSNetlist processor
CommandFile
PDRACULACommand file
processor
jxrun.com /jxsub.com
Run file
Draculaprograms
Command filesyntax error
Textand
GraphicError
Report
14CIC National Science CouncilCh ip Implem entation Center
PDRACULA A DRACULA command file interpreter%PDRACULA:/get command_file_name n {file} - fetchs the used command file
:/f - finishes compilation and produce UNIX run files
:/next - fetches the next file without clearing the buffer
:/a - aborts all processing
:/cl - clears buffer of all information
:PRIMARY = New_cell - 暫時修改部份內容:/STORE new_file.com - 將buffer的內容存成新檔
:FROM break1 - 指定Dracula執行的範圍
:TO break2:/quit
Note: If the syntax errors happen, the error or warning messages will be stored in *.lis
15CIC National Science CouncilCh ip Implem entation Center
PDRACULA Output
#!/bin/csh#BUILT FROM THE FOLLOWING GET FILES:# ../drc.flatcd /raid/raid09/wjhsu/COURSE/Dracula/rundrc//bin/cat <<!CREATED ON 31-JAN-97 11:30:19 PDRACULA REV 4.3 302!set nonomatchtimeDRACLM $0 $1 $2if ($status != 0) exit 1goto ENDcd /raid/raid09/wjhsu/COURSE/Dracula/rundrc/if ($1 == "" ) goto PREBEGIN/bin/cat <<!
** RUNNING FROM: $1 TO: $2!goto $1......
jxrun.com , jxsub.com , ats.com, jxsort.com ...
16CIC National Science CouncilCh ip Implem entation Center
Internal Flow(cont’d)
GDS2IN
EXPAND
SYSORT
LOGICAL
GDS2OUT
STAGE 1
STAGE 2
STAGE 3
STAGE ...
MT1.DAT ...
6POLY1.DAT ...
17CIC National Science CouncilCh ip Implem entation Center
LOGLVS A netlist processor for DRACULA check.%LOGLVS:transistor n -allocates additional virtual memory
:htv -generates InQuery files for cross-probing
:case -turns on case sensitivity
:ver filename -compile VERILOG netlist file
:cir -compile CDL/SPICE/HSPICE netlist file
:link -generate complete logic network
:con cellname -produces LVSLOGIC.DAT file for LVS
:summary -displays element summary by types
:exit
PRINT.OUT(log file) IMAGE.LIS(net-names)
18CIC National Science CouncilCh ip Implem entation Center
1. Introduction
2. Structure of Command File3. Layer Processing4. Design Rule Check5. Device Extraction6. Electrical Rule Check7. Layout vs. Schematic Check8. Layout Parameter Extraction9. Parasitic Resistance Extraction
10. Extraction Interface and Reduction
19CIC National Science CouncilCh ip Implem entation Center
About command file
• The contents of command file specify source data informationdata integrity check and processing process rules for verificationdevice parameterschecking commands
• Command files must be consistent with process• Use the most updated command files(read the header)
• Command files can be applied from CIC
20CIC National Science CouncilCh ip Implem entation Center
Structure of Command File
Description Block
Input Layer Block
Operation Block
Command files
Define database name,format, I/O informationdata integrity check.
Define input layer numbertext sequence, connection .
Define layer operationverification type...
Heading
21CIC National Science CouncilCh ip Implem entation Center
Description Block•format of input data(system)•Input and output file names(indisk, outdisk)•checked cell-name(primary)•verification report file name(printfile)•location of program executables(prodram-dir)•managing the Dracula created internal files(keepdata) •scale and working resolution of the database(scale, resolution )•case sensitivity(cname-csen)•assignment of the child cell that need not to be checked(delcell)•assignment of the checked or unchecked region(window, windel)•keep/cut the crossover-trapezoid outside the window(window-cut) •specify the directory to run job(work-dir)•specify the depth that text attached(text-level)
22CIC National Science CouncilCh ip Implem entation Center
Description Block (cont’d)
Description Block
DataSpecification
SystemInformation
Data HandlingSpecification
*DESCRIPTIONindisk = <path>/mydesign.gds system = GDS2 [GDS2,CIF,CADENCE_44dd,APPLE,EBES]primary = my_topcellschematic = LVSLOGICoutdisk = check.outprintfile = reports
program-dir = $DRAC4 keepdata = INQUERY [YES,NO,SMART,INQUERY]cnames-csen = NO [YES,NO] ;case sensitivitylist-error = NO [YES,NO] ;list error locationscale = 0.01 micron resolution = 0.01 microntext-level = 0flagnon45 = NO [YES,NO] list error locationdelcell = cellnamewindow = 10 10 500 500status = “date; time; du -sk”;output the run time and disk space usage of each stage
*END
23CIC National Science CouncilCh ip Implem entation Center
Description Block (cont’d)• For Cadence data
indisk = <my_path> ; The path of librarylibrary = mylib ; The library name for primary cell
• The reports of Dracula job are saved with prefix defined by printfile
• Specify appropriate keepdata for available diskspace / debug information
• The format of outdisk is consistent with system formatGDS2 - GDS2 CIF - CIFCadence_44dd - Skill code
24CIC National Science CouncilCh ip Implem entation Center
Input Layer Block•layer name definitionsuse layer name/purpose(purpose defaults to all layer purpose except pin)use layer_number/datatype_number(the default is all datatypes)
•text to layer associations•defining a substrate layer •interconnect sequence in mask order(text attached sequence)•assign attached layer sequence of text
25CIC National Science CouncilCh ip Implem entation Center
Input Layer Block
Input Layer Block
InternalLayer Name
Text to Layerassociation
ConnectionSequence
*INPUT-LAYERNNWELL = 2 THIN = 4MT1 = 16 TEXT 61VIA = 17 offgrid = 0.5MT2 = 18 TEXT 63 ATTACH MT2TEXT = TEXTSUBSTRACT = BULK 99connect-layer= PSUB NNWELL PDIFF NDIFF GPOLY MT1 MT2text-sequence= MT1 MT2 GPOLY
*END
26CIC National Science CouncilCh ip Implem entation Center
Operation Block
•layer processing•interconnect definitions•rule checking commands•checking options •elements extraction•parasitic elements extraction
27CIC National Science CouncilCh ip Implem entation Center
Operation Block
Operation Block
LayerProcessing
InterconnectDefinition
DesignRules
ExtractionCommands
ERC/LVSCommands
*operationAND GPOLY THIN GATEAND GATE NIMP NGATEAND GATE PIMP PGATE....CONNECT MT1 GPOLY BY CONT.....WIDTH GPOLY LT 0.6 OUT D3C 50 ; PO.W.3EXT[H] GPOLY LT 0.75 OUT D3D 50 ; PO.S.1EXT[T] GPOLY THIN LT 0.3 OUT D3E 50 ; PO.C.1ENC[T] GPOLY THIN LT 0.8 OUT D3F 50 ; PO.C.2.....ELEMENT MOS[N] NGATE GPOLY NDIFF PSUB.....MULTILAB OUT ESHORT 49 ;same node with diff labelSAMELAB OUT EOPEN 49 ;diff node with same labelLVSCHK[SCRA] WPERCENT=1 LPERCENT=1 CAPVAL=5*end
28CIC National Science CouncilCh ip Implem entation Center
1. Introduction2. Structure of Command File
3. Layer Processing4. Design Rule Check5. Device Extraction6. Electrical Rule Check7. Layout vs. Schematic Check8. Layout Parameter Extraction9. Parasitic Resistance Extraction
10. Extraction Interface and Reduction
29CIC National Science CouncilCh ip Implem entation Center
Data Integrity CheckIn Description Block•flag-acuteangle = yes•flag-non45 = yes•flag-offgrid = yes 0.25 ;(works with the flag-pth-offgrid and resolutioncommand sets the grid step size)•flag-pth-offgrid = yes ;report the coordinates of path-center(if offgrid)•flag-selfinters = yes•flag-selftouch = yes•path-w-offgrid = yes 0.25 ;path width offgrid check
violation object will be reported in “Problem Geometries”section of summary file
30CIC National Science CouncilCh ip Implem entation Center
Basic Operation• Original layers are defined in input layer block• Use operations for generating temporary layers and output
layers• Basic Command syntax
Operator source1 [source2] derived_layer
source1[2] is a original layer or derived layer
• Command Groups:•Logical - Create Shapes by Layer Interaction•Selection - Select Shapes by Attribute or Relation•Sizing - Create Shapes by Changing Layer Dimension
31CIC National Science CouncilCh ip Implem entation Center
Logical CommandsGPOLY
NDIFF
AND NDIFF GPOLY NGATE
OR GPOLY NDIFF AMASK XOR GPOLY NDIFF BMASK
NOT NDIFF GPOLY NSD
ANDNOT NDIFF GPOLY NGATE NSD
32CIC National Science CouncilCh ip Implem entation Center
Selecting Shapes• Select command output the entire shape of the first input layer
when the selection condition is met.• Command syntax
select layer1 condition [layer2] outlayer
conditions include :inside : select layer1 totally inside layer2outside : select layer1 totally outside layer2enclose[n1:n2 ]: select layer1 which cover shapes of layer2touch[n1:n2] : select layer1 that butt with layer2cut[n1:n2] : select layer1 that partly covered by layer2overlap[n1:n2 : select layer1 that intersect with layer2vertex[n1:n2] : select layer1 matched with range of verticeshole : select layer1 with all edge touch with layer2label{[R]} : select layer1 with the specified net-name{label}angle[n1] :select layer1 with the specified angle(90,45,-90,-45)
33CIC National Science CouncilCh ip Implem entation Center
Selecting Shapes(cont’d)
select ndiff inside nwell wcnt select ndiff outside nwell nsd
select res enclose[1:1] cnt badres
select lay1 hole lay2 lay3
select diff cut[1:2] poly sd
node ‘clk’
select poly label clk driver
34CIC National Science CouncilCh ip Implem entation Center
Sizing ShapesCommand syntax:
SIZE layer by value outlayervalue > 0 oversizevalue < 0 undersize
SIZE operation is four direction
Additional usage of SIZE operation :
1.5u
merge object
SIZE lay1 by 1.5u lay2SIZE lay2 by -1.5u lay3
lay2
lay1
35CIC National Science CouncilCh ip Implem entation Center
Sizing Shapes (cont’d)Usage of size operation : split object
SIZE layer1 by -1 layer2SIZE layer2 by 1 layer3
GROWSHRINK
oversize two perpendicular edgesUndersize two perpendicular edges
grow lay1 2 1 lay2 shrink lay1 -1.5 1 lay2
1u2u 1u1.5u
Size layer1 down-up 1 layer3
36CIC National Science CouncilCh ip Implem entation Center
1. Introduction2. Structure of Command File3. Layer Processing
4. Design Rule Check5. Device Extraction6. Electrical Rule Check7. Layout vs. Schematic Check8. Layout Parameter Extraction9. Parasitic Resistance Extraction
10. Extraction Interface and Reduction
37CIC National Science CouncilCh ip Implem entation Center
Design Rule Check
• 檢查佈局設計與製程規則的一致性• 基本設計規則包含各層之 Width, Spacing 及不同層間之spacing 、enclosure 等關係
• Design rule 的規定是基於 process variation, equipment limitation, circuit reliability 等之考量
• 在特殊的設計需求下,Design rule 允許部份的彈性。但設計者需掌握rule violation 對電路的影響。
38CIC National Science CouncilCh ip Implem entation Center
DRC Overview
DRC CommandFile
PDRACULA
Design RuleChecker
Text Output
Graphic Output
LayoutDatabase
39CIC National Science CouncilCh ip Implem entation Center
Finding DRC Errors with InQuery(Dracula Interactive)
Overlay Error Flagson Layout Database
Run DRC andCreate Error Files .sum File
Graphic Output
Search For andFix Errors
40CIC National Science CouncilCh ip Implem entation Center
DRC Commands
Command[mod] lay1 [lay2] cond_chk value {trapfile} {OUTPUT cellname lay# {d#}}
Type 1 : output check mark
Command: width, area, ext, enc, int, overlap, plength
cond_chk : lt, le, eq, range, gt, ge
cellname : output to cell namelay# : output with layer numberd#: output with datatype number
Command[mod] lay1 [lay2] sel_cond_chk value trapfile
Type 2 : output selected object of first layer
sel_cond_chk : sellt, selle, selra, selgt, selge, seleq, selne
mod : c, c’, n, n’, p, p’, r, r’, t, o, e, s… … command modifiers
41CIC National Science CouncilCh ip Implem entation Center
Typical Design Rules
abc
d
ef
a : WIDTHb,c : EXT
d,f : ENC
e : INTAREA
minimum width of geometry
minimum spacing of objects - outer edge to outer edge
minimum spacing of objects - outer edge to inner edge
minimum spacing of objects - inner edge to inner edge
area range check
42CIC National Science CouncilCh ip Implem entation Center
DRC Command Modifiersc, c’ : parallel, not paralleln, n’: different net, same netp, p’: projection, no projectionr, r’ : error region generationt, t’ : touch(butt), touch at vertexo : overlaye : not encloseds : square corner checkl : exact sizes checkx : x direction check onlyy : y direction check onlyh :notch check
43CIC National Science CouncilCh ip Implem entation Center
Command Modifiers
c : parallelc’: not parallel
ext[c] ext[c’]
n : same netn’: different net
p : projection(x,y direction)p’: not projection
r : region output r’: outer region
ext[n] ext[n’]
ext[p] ext[p’]
ext[r] ext[r’]
t : touch e : not enclosedo : overlap s : square corner
44CIC National Science CouncilCh ip Implem entation Center
l : width-length chek
x : x direction check
Command Modifiers
y : y direction check
h : notch check
45CIC National Science CouncilCh ip Implem entation Center
DRC Commands(cont’d)
ext[T] GPOLY THIN LT 0.3 OUT D3E 50 ; PO.C.1
0.4u
ext[T] THIN GPOLY SELLT 0.3 TMP1
One check per command lineCan be conjuncted with ‘&’mark
ENC[T] GATE&G1 GPOLY LT 0.005 & ENC[PT] &G1 PIMP LT 0.75 OUT D4E 50 ; PP.C.3
(&G1:outputs the results to the first layer, which is used as a temporary name)
46CIC National Science CouncilCh ip Implem entation Center
DRC Commands(cont’d)Latch-up CheckAnd pdifpsb cont psbcnt Ext(t) nmos psbcnt selgt 40 lnmosAnd lnmos psub llnmos out D6Y 60; nmos is far from p-sub cont
Size psbcnt by 40 tmp1Not pwell tmp1 latup out D6Y 60;
Contact Size Checkwidth [l] cont selne A badcntSize badcont by 0 out errcnt 60
width [l] cont rect = M by N goodcntnot cont goodcnt badcont output errcnt 60
A
A
M
N
47CIC National Science CouncilCh ip Implem entation Center
Rule Mapping of DRC
OD.W.1 Minimum width of OD region to define the width of NMOS/PMOS
AND GPOLY THIN GATE ENC[TR] GATE GPOLY LT 0.005 GATEWPLENGTH GATEW RANGE 0.01 0.749 OUT D2A 50 ;
GATE
48CIC National Science CouncilCh ip Implem entation Center
% PDRACULA********************************************************************************/N* DRACULA3 ( REV. 4.51 / SUN-4 /GENDATE: 6-AUG-99/12 )
*** ( Copyright 1995, Cadence ) ****/N* EXEC TIME =16:07:10 DATE = 4-OCT-00*******************************************************************************:/g drc25.com n:/f
** NOTE : PARTIAL DELETIONS OF FILES WILL BE PERFORMED
** CREATING : COMMAND FILE : jxrun.com
** NOTE : THIS JOB HAS 122 STAGES
END OF DRACULA COMPILATIONS* .086 Mbytes allocated to the current process.* .045 Mbytes is still in use.* THE END OF PROGRAM TIME = 15:57:48 DATE = 4-OCT-00 *
%jxrun.com > drc.log & (Submit the run file)
順利run 結束後會產生 *.sum file, 若 abort , 則須由log file(drc.log)找其原因 .由 log file亦可得知 DRACULA是否確實抓讀到 text(因Dracula由text獲知node name)
The running procedure of DRC/ERCAfter the assignment of the file name and top-cell name of layout in command file, compile command file by
49CIC National Science CouncilCh ip Implem entation Center
********************************************************************************/N* IDLABL ( REV. 4.51 / SUN-4 /GENDATE: 6-AUG-99/10 )
*** ( Copyright 1999, Cadence ) ****/N* EXEC TIME =09:33:41 DATE =10-SEP-99********************************************************************************/L* Q1 X= -25.70 Y= -14.90*/L* Q3 X= -92.70 Y= -14.10*/L* VSS X= 19.30 Y= 7.50*/L* CLK X= -195.10 Y= 60.40*/L* TC X= 30.10 Y= 83.10*/L* Q2 X= -194.20 Y= 121.30*/L* Q0 X= 32.50 Y= 181.60*/L* RESET X= -194.20 Y= 270.90*/L* VDD X= -173.10 Y= 356.70*/L* COUNTEN X= -133.60 Y= 369.90
在log file(top.log) 中 IDLABL stage(search character “IDLABL” ) 檢查是否所有要讓DRACULA抓讀的 text都有被抓讀
在log file(top.log) 中 POSATT stage(search character “POSATT” ) 檢查是否不同的 text均在不同的 node
********************************************************************************/N* POSATT ( REV. 4.51 / SUN-4 /GENDATE: 6-AUG-99/10 )
*** ( Copyright 1999, Cadence ) ****/N* EXEC TIME =09:33:51 DATE =10-SEP-99*******************************************************************************
Q1 X -25.70 Y -14.90 NODE 1 ATTACH MT2Q3 X -92.70 Y -14.10 NODE 2 ATTACH MT2CLK X -195.10 Y 60.40 NODE 22 ATTACH MT2TC X 30.10 Y 83.10 NODE 43 ATTACH MT2Q2 X -194.20 Y 121.30 NODE 41 ATTACH MT2
50CIC National Science CouncilCh ip Implem entation Center
Q0 X 32.50 Y 181.60 NODE 32 ATTACH MT2RESET X -194.20 Y 270.90 NODE 53 ATTACH MT2COUNTEN X -133.60 Y 369.90 NODE 74 ATTACH MT2.. . ..
GENERATE SHORTED NODES DIRECTORY : MULTILAB WITH 0 ENTRIES
GENERATE OPENED NODES DIRECTORY : SAMELAB WITH 0 ENTRIES
.. LIST OF EXTRACTED PAD NAMES AND NODE NUMBERS :
CLK 22COUNTEN 74Q0 32Q1 1Q2 41Q3 2RESET 53TC 43VDD 23 PVSS 6 G
node #
無short ckt 發生
無open ckt 發生
***唯有在無short ckt與open ckt之情況下ERC 才會確實執行 , 故須先解決short,open ckt後重新作ERC
51CIC National Science CouncilCh ip Implem entation Center
由summary file(*.sum )中之 OUTPUT CELL SUMMARY 部份可見一些因違犯 design rule而得的error CELL-NAME list, 如下例
---------------------------- OUTPUT CELL SUMMARY -----------------------------
CELL-NAME LAYER # ---------- W I N D O W ----------DATATYPE # OF POLYGONS TEXTS
(LINE SEGMENTS)
D11M50 50/ 0 -154.50 -138.50 126.00 137.50 1 0E349 50/ 0 -54.50 -123.00 75.50 -102.50 2 0E449 49/ 0 -75.50 100.50 54.50 120.00 2 0E749 49/ 0 52.50 4773.50 4925.50 4946.00 92 0E849 49/ 0 52.50 4773.50 4925.50 4946.00 92 0
OUTDISK PRIMARY CELL : OUTTOP WINDOW : -1.00 -1.00 5001.00 5001.00
ENDED AT TIME =16:26:13 DATE = 4-OCT-98****** PROBLEM GEOMETRY ERROR LISTING ******
***** END OF PROBLEM GEOMETRY LISTING *****
error CELL-NAME
**** The notice of texts on layout view(1) text origin must on layout object(2) text所有I/O pad,power&gnd pad,important internal node(3) 以A-Z,a-z,0-9 text較佳, 且text以字母起始(4) Appending a colon(:) to text will define “virtual wire” to Dracula.
Location of errors whichhave been found by dataintegrity check
The region of all error cells
D preceding 為DRC errorE preceding 為ERC error
Window size of error cell name of error top-cell
52CIC National Science CouncilCh ip Implem entation Center
Debug the DRC ErrorDracula output is consistent with input specificationThe output can be overlaid into design for debugOverlay Error mark into design
1. Cell Based Debug approach
2. Chip level Debug approach - a easy way
Import Error Mark via physical cell , the output name isspecified by OUTDISKSTREAMIN/CIFIN or load skill codeAdd error cell instanceFind / fix errors
Set KEEPDATA= INQUERYIn Layout edit window choose : Tools-> InquerySelect DRC -> Setup : define Dracula data directoryFind / fix errors
53CIC National Science CouncilCh ip Implem entation Center
Chip Level Debug Method
Invoke Inquery
54CIC National Science CouncilCh ip Implem entation Center
55CIC National Science CouncilCh ip Implem entation Center
Select Error Files
56CIC National Science CouncilCh ip Implem entation Center
Find/FixErrors
58CIC National Science CouncilCh ip Implem entation Center
1. Introduction2. Structure of Command File3. Basic Operation4. Design Rule Check
5. Device Extraction6. Electrical Rule Check7. Layout vs. Schematic Check8. Layout Parameter Extraction9. Parasitic Resistance Extraction
10. Extraction Interface and Reduction
59CIC National Science CouncilCh ip Implem entation Center
Device Extraction
AB
G
G
A
B
Cap1=2pF
M1 1.2/0.6
* The geometry data is physically a representation of a circuit
* Need a procedure to extract the netlist information from a layout for further processing
60CIC National Science CouncilCh ip Implem entation Center
Device Extraction(cont’d)• GDS2 Data is only geometrical information, such as rectangle, path,
polygon ...• Using device extraction for creating electrical information• Define the connection properties of layers• Define the device structure of a layout database• Create electrical connectivity and node names with text label• The extracted devices include MOS,BJT,DIO,RES,CAP,BOX,PAD• Device extraction for further usage : ERC, LVS, LPE
61CIC National Science CouncilCh ip Implem entation Center
Labeling TextText information is extensively used for creating electrical properties of layout. It will affect the results of ERC,LVS,LPEEDTEXT file in the OPERATION block can specify texts.Its format is: vdd: x=0 y=22 attach metal2
clk x=53 y=24 •Text all input and output pads,power and ground nodes,and important internal nodes•Text must be matched between netlist/ layout for LVS, LPE •Append :O to the text for output,:B for the text of bidirectional terminal,:I for the text
of input(default),:P for power,and :G for ground. •Text origin should be inside or at the edge of a geometry.•Text may contain up to 12 characters
.Mytext.Mytext
.No_use(attach to substrate)
62CIC National Science CouncilCh ip Implem entation Center
Define Electrical Properties
CONNECT-LAYER = PSUB NNWELL PDIFF NDIFF GPOLY MT1 MT2TEXTSEQUENCE = MT1 MT2 GPOLY ; assign text attach sequence
CONNECT-LAYER : Define mask order for conducting layers, assign text attached priority in the reverse order.
TEXTSEQUENCE : Redefine text attach priority , must be after connect-layer command.
The above commands are defined in the INPUT-LAYER block
.CLK
MT1
MT2
CLK is assigned to MT2
63CIC National Science CouncilCh ip Implem entation Center
Define Connect PropertiesCONNECT : Define the interlayer connectivity, the contact layer must
correspond to one upper-layer name
SCONNECT : Define the interlayer connectivity, the contact layer must correspond to one upper-layer name. Sconnect pass connectivity to lower-layer for soft-connect checking
CONNECT MT1 GPOLY BY CONTCONNECT MT1 NDIFF BY CONTCONNECT MT2 MT1 BY VIA1SCONNECT NDIFFC NNWELLC BY NWLCNT
VDD
64CIC National Science CouncilCh ip Implem entation Center
Basic Extraction Steps
Find the Recognition Layer - a layer which can uniquely define the device1.
2.Derive Terminal Layers
3. Create Substrate/Well Layer - a layer which define the 4th terminal
65CIC National Science CouncilCh ip Implem entation Center
Basic Extraction Steps(cont’d)
4. Establish connectivity
5. Extract Device and measure device parameter
W=1.2, l=0.6
2
14
3The parameter must be defined priorly.(e.g.)10fF/um2 for C 2 Ohm/square for R
66CIC National Science CouncilCh ip Implem entation Center
Extract MOSFET
element mos[n] ngate gpoly ndiff pwell
G
D
S
B
SiO2
PWELL
p+n+n+
67CIC National Science CouncilCh ip Implem entation Center
Extract ResistorsR+ R-
poly resistor
SELECT GPOLY CUT Resis GPOLYRAND GPOLYR Resis GPRES ;define GPOLY resistorNOT GPOLYR GPRES GPRT ;GPRT=GPOLY resistor terminalCONNECT MT1 GPRT BY CONTELEMENT RES[GP] GPRES GPRTPARAMETER RES[GP] 7.28
POLY
68CIC National Science CouncilCh ip Implem entation Center
Extract Capacitors
poly capacitor
c+ c-
ELEMENT CAP[CP] CAPT CPOLYC GPOLYCPARAMETER CAP[CP] 6.495e-4 8.38e-5
AND GPOLY CPOLY CAPT
69CIC National Science CouncilCh ip Implem entation Center
1. Introduction2. Structure of Command File3. Basic Operation4. Design Rule Check5. Device Extraction
6. Electrical Rule Check7. Layout vs. Schematic Check8. Layout Parameter Extraction9. Parasitic Resistance Extraction
10. Extraction Interface and Reduction
70CIC National Science CouncilCh ip Implem entation Center
Electrical Rule Check
• Check for open/short of interconnect wires• Check for connection characteristic of devices• Check for connection characteristic of layers• Check for charge/discharge path of node
71CIC National Science CouncilCh ip Implem entation Center
ERC CommandsSAMELAB : Check for open circuit fault
MULTILAB : Check for short circuit fault
Vdd
Vdd
SAMELAB OUT EOPEN 49
IN1
OUT1
MULTILAB OUT ESHORT 49
•Connectivity definitions are established.Based on these definitions,each node is assigned an interal node# and stored in a table.
•Text on a node will overwrite the internal node#.•If open or short is detected, the text(s) wll be discarded and retain the internal node#.
72CIC National Science CouncilCh ip Implem entation Center
ERC Commands
ELCOUNT MOS ALL LE 1 OUT EG 49
ECONNECT : Check if an element with electrical connectivity to a label
ECONNECT MOS[n] GPOLY CONN VSS OUT EF 49
VSS[DISC]
ELCOUNT : Check the number of elements connecting to a node
Err
73CIC National Science CouncilCh ip Implem entation Center
ERC Commands
NDCOUNT MOS[N] NDIFF EQ 1 OUT EL 49NDCOUNT MOS ALL EQ 1 OUT EM 49
NDCOUNT : Check the number of nodes connected for an element
G D GEL49
LCONNECT : Check if the specified layer connect to a node
LCONNECT PWELL CONN Vdd OUT EN 49[DISC]
Vdd
EM49
74CIC National Science CouncilCh ip Implem entation Center
ERC CommandsPATHCHK : Check the existence of path to power/ground
for each node
PATHCHK LEVEL 1 OUT EH 49 ; no path to VDDPATHCHK LEVEL 2 OUT EI 49 ; no path to VSSPATHCHK LEVEL 3 OUT EJ 49 ; no path to VSS & VDDPATHCHK LEVEL 4 OUT EK 49 ; no path to VSS & VDD,exclude nodes
with path to PAD(the labeled nodes)
SOFTCHK : Check if multiple nodes from the upper layer are passed to lower layer with SCONNECT statement
SOFTCHK PWELL OUTPUT errVSS 49
75CIC National Science CouncilCh ip Implem entation Center
ERC Check•Improperly Connected WellsAnd pdifpwl cont pwlcntsconnect mt1 pwl by pwlcntsoftchk pwl output[u] err 60 lconnect pwl disc vss? output hotpwl 50
•Improper Device ConnectionsAnd ndifnwl cont nwlcntsconnect mt1 nwl by nwlcntelement mos[p] pgate gpoly pdiff nnwelleconnect mos[p] nnwell disc vdd? output errpmos 50
•Probing a specified texted nodetext2 = 63connect metal1 gpoly by contconnect metal1 metal2 by via1probe vdd output nodevdd 50 ;output the node that carries label”vdd”
76CIC National Science CouncilCh ip Implem entation Center
Procedure for ERC
TextedLayout
DatabaseDeviceExtract ERC
Text(.erc)and
GraphicError
Reports
CommandFile
The layout must be labeled for ERC
77CIC National Science CouncilCh ip Implem entation Center
Reading ERC Output
Soft Check ListingSoft Connection Check on Layer PWELL
input X 10.25 Y 9.75 NODE 2 ATTACH METAL1gnd X 168.00 Y 9.75 NODE 3 ATTACH METAL1
*/W* WARNING ** TTEXT : ina SHORT DISCARDED
ERC ERROR Summary for cell : ESHORT49...
*.erc
Text Summary
*.sum : Similar to DRC
78CIC National Science CouncilCh ip Implem entation Center
Debug ERC Error• Debug ERC Error is very similar to debug DRC Error
• DRC/ERC could be packed in the same command file, thus DRC / ERC are checked simultaneously.
• Check the text summary for label information, ERC error may caused from wrong label.
• Use the DRC session for debugging ERC error in INQUERY environment.
• OPEN / SHORT should be corrected at first
79CIC National Science CouncilCh ip Implem entation Center
Hierarchical ConceptDracula only handle two levels of hierarchy
TOP
CELL1 CELL2
TOP
CELL1 CELL2
Selection of HCELL1. By specification2. By constraint
80CIC National Science CouncilCh ip Implem entation Center
Hierarchical DRC/ERCDracula check modes :
FLAT MODE : Default
CELL MODE : Check the contents of each HCELL
COMP MODE : Check Hcell to Hcell, COMP to Hcell and composite plane
HIER MODE : Check HCELLs, HCELL to HCELL, COMP
MULTI MODE : Check with hierarchical HCELL, cells are selected automatically
CHECK-MODE =
81CIC National Science CouncilCh ip Implem entation Center
Hierarchical DRC/ERC
• HDRC/HERC check are similar to flatten modePDRACULA:/get command_file n:/finjxrun.com > run_log &
• HCELL-FILE and CHECK-MODE should be provided in the DESCRIPTION BLOCK• HDRC/HERC outputs can be either in one file or to
different HCELL error filesCELL-ERROR-REP = ALL/ONCE/HIER
CIC National Science CouncilCh ip Implem entation Center
82
1. Introduction2. Structure of Command File3. Basic Operation4. Design Rule Check5. Device Extraction6. Electrical Rule Check
7. Layout vs. Schematic Check8. Layout Parameter Extraction9. Parasitic Resistance Extraction
10. Extraction Interface and Reduction
CIC National Science CouncilCh ip Implem entation Center
83
Layout vs. Schematic Check
• 檢查佈局與電路設計的一致性• 執行LVS比對前應先完成 DRC/ERC• Tape-out之前LVS結果應為Error-free• LVS的正確性需依賴TEXT label的正確對應• 更正LVS的錯誤需有耐心
CIC National Science CouncilCh ip Implem entation Center
84
LVS Overview
CommandFile
Device Extraction
LVSLOGLVS
Layout
Netlist
Graphic output
Text output
PDRACULA
CIC National Science CouncilCh ip Implem entation Center
85
Schematic CDL Out Netlist File
LOGLVS
Netlisting Flow
OtherNetlist Types
LVSLOGIC.DATFile
SPICE,EDIF,Verilog… .
CIC National Science CouncilCh ip Implem entation Center
86
Preparing Netlist• 進行LVS之前需先準備 netlist 檔,netlist 檔經LOGLVS轉換成LVSLOGIC.DAT檔以便Dracula讀取
• 原始netlist檔可為SPICE檔,CDL檔或Verilog格式• SPICE/CDL Netlist中整個電路需包含在SUBCKT定義裡• 使用DFII之Schematic CDL OUT時,若要轉出analog
device,需設定環境變數– setenv CDS_Netlisting_Mode Analog
CIC National Science CouncilCh ip Implem entation Center
87
Control statement of Netlist file
以‘* ’開頭的statement表此列為給Dracula讀取以‘$ ’開頭的statement表此列為comment,Dracula不讀取
*.GLOBAL (宣告global node) (ex)*.GLOBAL VDD,VSS*.BIPOLAR (有此statement LOGLVS 將保留netlist中的 R,C,diode以作比對用,當然此時配合用的command file須有相對的元件定義)搭配*.BIPOLAR 可加
*.RESVAL *.RESSIZE (perform R value or size check)*.CAPVAL *.CAPAREA (perform C value or area check)*.DIOAREA *.DIOPERI (perform diode area or perimeter check)
*.UNSPEC_MOS (有此statement,則當netlist中無指定W,L時,將show message於‘PRINT.OUT’中*.REVERSE(LOGLVS讀取MOS順序為W,L,若MOS順序為L,W時可用此statement)
Preparing Netlist
CIC National Science CouncilCh ip Implem entation Center
88
LOGLVS Procedure
:htv:genpad
:case:cir topcell.cdl:ver verilog.v:link:con topcell:exit
generate information for inquerygenerate a 6gpads.dat file for LVS
device reductionspecify case sensitivityread the spice/cdl netlistread Verilog fileexpand the logic network for Verilogconvert from the top cell name
%LOGLVS
Error file: PRINT.OUT(log file)Translation table:IMAGE.LIS(all of the net-names)
CIC National Science CouncilCh ip Implem entation Center
89
LVS Command FileINDISK = amp1.db ; GDSII Layout Database FileNamePRIMARY = amp1 ; Chip Top Cell NameOUTDISK = amp1.out ; GDSII Output Filename of ErrorPRINTFILE = amp1 ; Root Name of Text Output FilenameSYSTEM = GDS2 ; Layout Database FormatLISTERROR = YES ; print the X, Y coordinate of the error flagsKEEPDATA = SMART ; Delete intermediate data files during the runTEXT-PRI-ONLY = YES ; Use top level text for node name; TEXT-LEVEL = 1 ; Specify the level of text for extractionFLAG-SELFINTERS = YES ; report polygons with edges self-intersectERROR-PATH-WIDTH = 5.0 MIC ; Width of Error FlagSCHEMATIC = LVSLOGIC ; Compiles netlist generated by LOGLVSABORT-P-G-SHORT = YES *OPERATIONEDTEXT=TEXT.FILEELEMENT CAP[CP] CAPT CPOLYC GPOLYCPARAMETER CAP[CP] 6.495E-16ELEMENT MOS[NM] NGATE GPOLYC NDIFFC PSUB;****** LVS CHECKING **********LVSCHK[SCRA] WPERCENT=1 LPERCENT=1 CAPVAL=5*END
CIC National Science CouncilCh ip Implem entation Center
90
LVS Internal Flow
Read DatabaseTop cell name
Expand datafrom top
Extract deviceand parameters
Filter unused device
Reduce deviceas specified
Built map ofcorrespondence
Trace from pads
Build Deviceand node maps
Comparisonand Output
CIC National Science CouncilCh ip Implem entation Center
91
LVS Device Reduction
• Dracula is capable of performing LVS up to gate level•Gate information is extracted from layout by device
reduction• Gate information is extracted stage-by-stage.
• Primitive structures by device extraction include : MOS,BJT, Resistor, Diode and Capacitor
PUP
SDW
CIC National Science CouncilCh ip Implem entation Center
92
Second Level Structure
Power
Out
PUP Out,IN1,IN2,...
Power
IN1
IN1
Out
SUP Out,IN1,IN2,...
CIC National Science CouncilCh ip Implem entation Center
93
Second Level Structure(cont’d)
Ground
Out
PDW Out,IN1,IN2,...
Ground
IN1
IN1
SDW Out,IN1,IN2,...
Out
CIC National Science CouncilCh ip Implem entation Center
94
Gate Level StructureVdd
Out
PUPI out1,IN1,IN2SUP Out,IN3,out1
SDWI out2,IN1,IN2PDW Out,IN3,out2
IN1IN2
IN3Out
PUPISDWI SUP
PDW
AOI Out IN1 IN2 IN3
CIC National Science CouncilCh ip Implem entation Center
95
LVS Comparison OptionProhibit Input Swapping A
BLVSCHK[x] AB
Reduce Series Resistors
Prohibit parallel Reduction
r r 2r
LVSCHK[r]
r 0.5r
LVSCHK[k]w/l w/l 2w/lweff=w1+w2
Leff=(L1+L2)/2
CIC National Science CouncilCh ip Implem entation Center
96
LVS Comparison Option(cont’d)
Series MOS Reduction LVSCHK[s]
Reduce Series Capacitors
CMOS Gate Reduction
LVSCHK[a]
LVSCHK[c]
C C 0.5C
IO
I O
wsumlavg
lavg= (l1+l2)/2wsumlavg
(default reduce until second-level)
CIC National Science CouncilCh ip Implem entation Center
97
LVS Parameter ComparisonSpecify the parameter comparison toleranceLVSCHK wpercent = 10
lpercent = 10w/l-percent = 5 resval = 10capval = 10
MOS width ratioMOS length ratioMOS aspect ratioresistor value ratiocapacitor value ratio
LVSCHK weffect = 0.6 Corner effect to orthogonally bent gate6u
6u
2u
2u2u
W = Winitial - (Weff*length*bends)W = 14 - (0.6*2*2) = 11.6
L
CIC National Science CouncilCh ip Implem entation Center
98
LVS Output ControlParameter comparison tolerance:
dioareadioperieapercaparearesareamoscap-area
for diode areadiode perimeteremitter areacapacitance arearesistance areaMOS capacitor area
By the ‘Unspec-para = yes’(in *Description block) can print unknownlayout and schematic device parameters in <printf>.lvs file after the LVS comparisn.
CIC National Science CouncilCh ip Implem entation Center
99
LVS Initial Node Pairs• LVS comparison using text extracted from the schematic andlayout as a starting point
• LVS result heavily rely on the matching of input labels.• Use CPOINT-FILE command (in *Description block) to specify
the label matching of layout and schematic
*DESCRIPTION...CPOINT-FILE = INITNAME.TXT
In INITNAME.TXTLayout nametes-ptgnd
Schematic namex101-x30-01vss
CIC National Science CouncilCh ip Implem entation Center
100
Read LVS Reportprintf.lvs
Header and LVSNET information
Layout Reduction andLVS Run options summary
Schematic Reduction Summary
Main Body LVS report
LVS Repeat Summary
List weffect value andtranslate layout to netlist
Parallel smash and form gate
Correspondence node pairs,LVS device matching,Discrepancy Points Listing and summary,and Device matching
CIC National Science CouncilCh ip Implem entation Center
101
Main Body LVS Report•Execution time and run options
•Initial Correspondence Node PairsList the node pairs given by user
•Correspondence Node PairsLists the node mapping by DRACULA
•Device Match Summary -> unmatched device = 0Reports the number of matched/unmatched device
•Discrepancy Points Listing -> No DiscrepancyList detailed examination of 15 error types
•Detailed Device Matching SummaryList all unmatched devices by device type
CIC National Science CouncilCh ip Implem entation Center
102
Header and LVSNET Information
*********************************************************************/N* DRACULA3 ( REV. 4.51 / SUN-4 S5R4 /GENDATE: 19-MAR-98/14 )
*** ( Copyright 1995, Cadence ) ****/N* EXEC TIME =17:03:05 DATE =21-JAN-01 HOSTNAME = cicsun09********************************************************************INDISK PRIMARY CELL : MULTIPLIER
*********** LVSNET SUMMARY REPORT ***********
WEFFECT VALUE= 0.0000000
Reports the execution time, version, host and top cell nameLVSNET Summary Report tells netlist processing information
CIC National Science CouncilCh ip Implem entation Center
103
Layout Reduction Information******* REDUCE (LAYOUT) SUMMARY REPORT *******
******* STATISTICS BEFORE REDUCE ****MOS BJT RES DIODE CAP UND BOX CELL LDD432 0 0 0 0 0 0 0 0
OPTION TO SMASH PARALLEL DEVICES IS -- ONOPTION TO CONSTRUCT MOS PARALLEL/SERIES STRUCTURES IS -- ONOPTION TO SMASH PSEUDO PARALLEL DEVICES IS -- ONOPTION TO FORM CMOS GATES IS -- ON
******* STATISTICS AFTER REDUCE ****MOS BJT RES INV DIODE CAP SDWI PDWI SUPI320 0 0 0 0 0 0 0 0PUPI SDW PDW SUP PUP AND OR AOI NAND
0 12 0 12 0 0 0 0 16NOR OAI UND BOX CELL LDD SMID PMID MOSCAP0 0 0 0 0 0 0 0 0
CIC National Science CouncilCh ip Implem entation Center
104
Schematic Reduction Information******* REDUCE (SCHEMATIC) SUMMARY REPORT *******
******* STATISTICS BEFORE REDUCE ****
MOS BJT RES DIODE CAP UND BOX CELL LDD432 0 0 0 0 0 0 0 0
******* STATISTICS AFTER REDUCE ****MOS BJT RES INV DIODE CAP SDWI PDWI SUPI320 0 0 0 0 0 0 0 0PUPI SDW PDW SUP PUP AND OR AOI NAND
0 12 0 12 0 0 0 0 16NOR OAI UND BOX CELL LDD SMID PMID MOSCAP0 0 0 0 0 0 0 0 0
CIC National Science CouncilCh ip Implem entation Center
105
Main Body LVS Report***************** LVS REPORT *****************
DATE : 21-MAY-97TIME : 17:04:29PRINTLINE = 1000MOS DEVICE WIDTH NOT CHECKEDMOS DEVICE LENGTH NOT CHECKEDUNSPECIFIED SCHEMATICAL PARAMETERS ARE CONSIDERED AS MISMATCHUNSPECIFIED SCHEMATICAL SUBSTRATES ARE CONSIDERED AS MISMATCHUNSPECIFIED LAYOUT PARAMETERS ARE CONSIDERED AS MISMATCHUNSPECIFIED LAYOUT SUBSTRATES ARE CONSIDERED AS MISMATCH
READING CPOINT-FILE FOR INITIAL CORRESPONDENCE POINTS
/*W : SCH. PAD VDD! MATCHED TO LAY. PAD VDD BY PADTYPE/*W : SCH. PAD GND! MATCHED TO LAY. PAD VSS BY PADTYPE
CIC National Science CouncilCh ip Implem entation Center
106
Main Body LVS Report1 ***************************************************
********* CORRESPONDENCE NODE PAIRS **************************************************************
SCHEMATICS LAYOUT PAD TYPEVCC 3 VCC 14 PGND! 2 gnd 3 GVDD! 1 vdd 1 P***TOTAL = 3***
/*W WARNING : LIST OF SCHEMATIC PADS HAVE NO LAYOUT CORRESPONDENCE
I_INJECT 4 IINPUT 5 IOUT 6 I
***TOTAL = 3***/*W WARNING : LIST OF LAYOUT PADS HAVE NO SCHEMATIC CORRESPONDENCE
i_inject 18input 2out 9
***TOTAL = 3***NUMBER OF VALID CORRESPONDENCE NODE PAIRS = 0
CIC National Science CouncilCh ip Implem entation Center
107
Main Body LVS Report1 ***************************************************
******** LVS DEVICE MATCH SUMMARY ************************************************************
NUMBER OF UN-MATCHED SCHEMATICS DEVICES = 0NUMBER OF UN-MATCHED LAYOUT DEVICES = 0NUMBER OF MATCHED SCHEMATICS DEVICES = 30NUMBER OF MATCHED LAYOUT DEVICES = 30
CIC National Science CouncilCh ip Implem entation Center
108
Main Body LVS Report1 ***************************************************
******** DISCREPANCY POINTS LISTING *************************************************************
**************** DISCREPANCY 1 ***********************-- NODE N1023-- WTH UN-MATCHED DEVICEOCCURRENCE NAME N1023?DEVICE2190 NAND : **** UNMATCHED ****N1023, N2137, N1488
**** UNMATCHED **** : ?DEVICE1855 NAND: X=15661.00 Y=2413.50: N1023,?N2137,N1488
********TOTAL 24 DISCREPANCY POINTS REPORTED 1 ***************************************************
******** DISCREPANCY POINTS SUMMARY **********************************************************
2 MATCHED NODE TO NO DEVICE
CIC National Science CouncilCh ip Implem entation Center
109
LVS Repeat Summary1 **************************************************
********** LVS SUMMARY (REPEATED) ************************************************************************************************************************** LVS DEVICE MATCH SUMMARY **********************************************************
NUMBER OF UN-MATCHED SCHEMATICS DEVICES = 0NUMBER OF UN-MATCHED LAYOUT DEVICES = 0NUMBER OF MATCHED SCHEMATICS DEVICES = 30NUMBER OF MATCHED LAYOUT DEVICES = 30
****************************************************** DISCREPANCY POINTS SUMMARY *************************************************2 MATCHED NODE TO NO DEVICE ...*********************************************************** DEVICE MATCHING SUMMARY BY TYPE ******************************************************
TYPE SUB-TYPE TOTAL DEVICE UN-MATCHED DEVICE
CIC National Science CouncilCh ip Implem entation Center
110
Debug LVS Error• LVS Error usually can not be easily located• Do not verify at block-level until all cells within the block pass LVS• Always Clean ERC error before LVS• LVS Errors are usually closely related, that is one physical error may
introduce several LVS error,so rerun LVS after fixing an error.• LVS results are heavily relied on the correctness of initial
correspondence nodes. That is, the mapping of nodes between schematic and layout must be consistent.
• When LVS mismatch occurs, always check the specification of input text and map of correspondence nodes.
CIC National Science CouncilCh ip Implem entation Center
111
Debug LVS Error(cont’d)•Check the log file to know the texts of layout that have been got
by Dracula•Check if text is added on the top hierarchy•Check if text origin is added on shapes•Check the case sensitivity of text
If Text is not a problem, then•Check device number between schematic and layout•Check if schematic includes analog device•Check the LVS filter option•Check the circuit reduction option•Check device in the reduction group UND•Check the PRINT.OUT file from LOGLVS for schematic processing error
CIC National Science CouncilCh ip Implem entation Center
112
Debug LVS Error(cont’d)Discrepancy point analysis
•Scan the report for repetition of problem nodes or device•Look for coincidence with devices or nodes
unmatched devicesproblem nodes with same number of connections
•Associate multiple discrepancy points•Start with a matched device as a reference point•Use the X:Y location of unmatched layout devices•Rerun LVS after fixing a major error
Propagation of errors is reduced
CIC National Science CouncilCh ip Implem entation Center
113
Finding LVS Errors with InQuery
Overlay Error Flagson Layout Database
Run LVS andCreate Error Files .lvs File
Graphic Output
Search For andFix Errors
CIC National Science CouncilCh ip Implem entation Center
114
There are 15 error typesAll errors are found in the Discrepancy Points ListingEach Error type found indicates one errorEach error may be represented by several error typesEach discrepancy point represents one errorEach error may be represented by many discrepancy points
Error Type Overview
CIC National Science CouncilCh ip Implem entation Center
115
LVS Error Types
Type 1: MATCHED NODE TO NO DEVICE
PAD A PAD A
Type 2: MATCHED DEVICE TO UNMATCHED NODE
2137 2137
2410 ?24001826 1826
CIC National Science CouncilCh ip Implem entation Center
116
LVS Error Types(cont’d)
Type 3: INCONSISTENTLY MATCHED DEVICE
N N
A1
A2
A3
A1
A2
A4
Type 4: Matched Node to Extra Layout Devices
A7 A7
A1 A2 A3 A1 A2 A3 Am
Layout
CIC National Science CouncilCh ip Implem entation Center
117
Type 5: Matched Node to Extra Schematic DevicesA7 A7
A1 A2 A3 A1 A2 A3Am
Layout
Type 6: Matched Node to Unmatched Layout and Schematic Devices
A7
A1 A2 A3 Am
A7
A1 A2 A3 Bm
Layout
LVS Error Types(cont’d)
CIC National Science CouncilCh ip Implem entation Center
118
LVS Error Types(cont’d)
Type 7: Other Unmatched Layout Devices
This type of error indicate those layout devices which are either separated from rest of circuit or cannot be reached from initialcorrespondence points or blocked by discrepancy points
Type 8: Other Unmatched Schematic Devices
This type of error indicate those schematic devices which are either separated from rest of circuit or cannot be reached from initial correspondence points or blocked by discrepancy points
CIC National Science CouncilCh ip Implem entation Center
119
LVS Error Types(cont’d)
Type 9: Device Sup-type Mismatch
A1 A1A2 A2
A3 A3
Layout
Type 10: Device Size MismatchA1 A1
A2 A2A3 A3
Layoutw/l=12/2w/l=14/2
CIC National Science CouncilCh ip Implem entation Center
120
LVS Error Types(cont’d)
Type 12: Device Substrate Connection MismatchA1 A1
A2 A2A3 A3
Vsub1 Vsub2
Type 13: Device Power Connection MismatchVcc1:P
A2 A2A3 A3
Vsub1 Vsub2Vcc2:P
Type 11: MOS Reversibility Error
2137
21372400
24001826 1826
CIC National Science CouncilCh ip Implem entation Center
121
LVS Error Types(cont’d)
Type 14: Reduced Layout Parallel Devices
A1
This type is for reference only
Type 15: Filtered-out Layout MOS DevicesThis type is for reference only
VddVdd
CIC National Science CouncilCh ip Implem entation Center
122
InQuery for LVS
Setup LVSenvironment
CIC National Science CouncilCh ip Implem entation Center
123
Select Error
CIC National Science CouncilCh ip Implem entation Center
124
DisplayNet orDevice
CIC National Science CouncilCh ip Implem entation Center
125
Hierarchical LVS
Specification in *Description block CHECK-MODE = COMP ; composition mode hlvsHCELL-FILE = HP_IO.hcell ; specify the hcell file name
;HCELL-FILE = HD_IO.hcell ; specify the hcell file nameBLACKBOX-FILE = HP_IO.blackbox ; specify the blackbox file name
;BLACKBOX-FILE = HD_IO.blackbox ; specify the blackbox file nameSCHEMATIC = LVSLOGIC.DAT ; specify the schematic
•For cell-based design, run Dracula in hierarchical mode.•Select the HCELL-FILE and BLACKBOX-FILE definition
based on your cell library type.• The netlist must be consistent with your cell• Executing HLVS is the same as typical LVS.
P.S. Cell mode + Composite mode is a complete check
CIC National Science CouncilCh ip Implem entation Center
126
Black-box LVS relative files
Hcell file: HP_IO.hcell (assignment of hierarchical cell)(e.g.) ad01d1(netlist cell name) ad01d1(layout cell name)
ad01d2 ad01d2. … … ...
Pseudo spice file: pseudo.spi (use for LOGLVS)(e.g.) *.GLOBAL vdd gnd
.SUBCKT ad01d1 S CO A B CI
.ENDS ad01d1 .SUBCKT ad01d2 S CO A B CI.ENDS ad01d2 … … ..
black-box file: HP_IO.blackbox(pin information of black-box)(e.g.) vdd x=10.5 y=11.8 ATTACH=METAL1 ad01d0 W=20.4 H=1.8
gnd x=18 y=0.8 ATTACH=METAL1 ad01d0 W=4.75 H=1.8 co x=20.3 y=7 ATTACH=METAL1 ad01d0 W=0.5 H=0.5
(pin_name, location of middle point, pin_layer,cell_name,width&height of pin_layer)
CIC National Science CouncilCh ip Implem entation Center
127
LOGLVS and Verilog In using VAN
•VER command in LOGLVS converts the verilog netlist into TEGAS format internally before flattening and results in several limitations. NVER is used to solve the problem.•The running procedure: 1. %mkdir <libname> (create design library directory)2. Add the library to ‘library manager’3. %van -lib <libname> <verilog_netlist>4. Run LOGLVS, use a simple script:
LOGLVS << EOFtrans 200000htvcasecell/box HP_IO.hcellFPINcir/nodrop pseudo.spinver mylib top_cellconvert top_cell
exit
EOF
CIC National Science CouncilCh ip Implem entation Center
128
1. Introduction2. Structure of Command File3. Basic Operation4. Design Rule Check5. Device Extraction6. Electrical Rule Check7. Layout vs. Schematic Check
8. Layout Parasitic Extraction9. Parasitic Resistance Extraction
10. Extraction Interface and Reduction
CIC National Science CouncilCh ip Implem entation Center
129
Layout Parasitic Extraction(LPE) Overview
LVS Comparisonand Device Checking
Create and ExtractParasitic Devices
Netlist Formattingand Generation
CIC National Science CouncilCh ip Implem entation Center
130
Layout Parasitic Extraction(LPE)
Vdd Vg
Vs
Vr
Vg
Vdd
Vs
Vr
Ca
Cb
Cpoly-metal = 62.1e-18 F/um2
PARASITIC CAP[PI] CIM1P1 MT1 GPOLYCATTRIBUTE CAP[PI] 62.1E-18 108.12E-18
CIC National Science CouncilCh ip Implem entation Center
131
Importance of Parasitic
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 ns
1.0u
0.8u
0.5u
0.35u
Gate delay: short net Gate delay: long netWire delay: short net Wire delay: long net
40-75%
35-60%
25-45%
15-30%
Ref : Cadence DSM Seminar
CIC National Science CouncilCh ip Implem entation Center
132
Parasitic Extraction
Metal3Metal2Metal1
Precise Parasitic Capacitance includes 3D field effect.
Raphel (TMA) is a widely used 3D field solver for capacitance evaluation
CIC National Science CouncilCh ip Implem entation Center
133
Layout Parasitic Extraction• 佈局資料之元件與電路萃取,以便進行post-layout 電路模擬• 包含雜散電容及電阻等寄生元件之萃取• LPE 之輸出為SPICE或DSPF(Detailed Standard Parasitic Format)或RSPF(Reduced Standard Parasitic Format)(for HPRE only)格式檔
• 可由Command file 控制Extraction的複雜度
CIC National Science CouncilCh ip Implem entation Center
134
LPE Command FileMODEL = MOS[NM],N,MOS[PM],P,DIO[N],NDIO,DIO[P],PDIO; equate the elements and sub-types used in the Dracula to the SPICE model nameUNIT = CAPACITANCE,F AREA,P PERIMETER,UPREFIX-PARASITIC = CAP,CCPARSET MOSS AREA PERI ANG AS PS W L AD PDPARSET ICHI AREA PERI*ENDAND M1NPD NNWELLC CMM1WELPARASITIC CAP[PM] CMM1WEL MT1 NNWELLCATTRIBUTE CAP[PM] 42.1E-18 92.34E-18PARASITIC CAP[M1] MT1 MT1 MT1ATTRIBUTE CAP[M1] 4 67.32E-18LEXTRACT ICHI PDIFFC BY NODE PDIFFPCATTACH MOS[PM] PDIFFPCLPESELECT[N] MOS &LPESELECT[N] RES GT 0 &LPESELECT[N] CAP GT 0 OUTPUT SPICE 01*END
Old syntax
CIC National Science CouncilCh ip Implem entation Center
135
Parasitic Overlap Capacitor Extraction
Overlap Capacitance
C2C1Node1
C1 = Area * Attribute1 +Perimeter * Attribute2(default equation)
AND MT2 MT1 CM12PARASITIC CAP[PA] CM12 MT2 MT1ATTRIBUTE CAP[PA] 40.1E-18 95.60E-18
The unit is F/um2 for Attribute1,and the unit is F/um for Attribute2
CIC National Science CouncilCh ip Implem entation Center
136
Parasitic Overlap Capacitor
Lumped Capacitor(default mode)
Coupled Capacitor output if LPESELECT[C] CAP
C2C1
Node t with relative to ground= C1+C2
Node to node
Ct t 0 2.24E-02 pF
2 3
t
C1 t 2 1.2E-02 PFC2 t 3 1.04E-02 PF
CIC National Science CouncilCh ip Implem entation Center
137
Parasitic Fringe Capacitor Extraction
Fringe Capacitance(for single-layer or different-layer)
d1 L C1 = L * Attribute * 1 / d1
d2
Fringe CAP[M2] MT2 MT2 MT2attribute CAP[M2] 4 100.96E-18
attribute CAP[type] max_distance Attribute(F/um)
(default equation)
CIC National Science CouncilCh ip Implem entation Center
138
Note of (Flexible) LPE
•To extract values from specified layers, use LEXTRACT and PARSETGeometric PrimitivesANG: total internal angleAREA: areaPERI: perimeterW1: overlapped perimeter to node 1 of second layerW2: overlapped perimeter to node 1 of second layerOVAR: overlapped area to second layerOVPR: overlapped perimeter to second layerWIDT: distance that the layer runs parallelDEPT: distance between the parallel geometriesTPR: perimeter of geometries that cause fringe effect
Reserved Parameter KeywordsW: MOS channel widthL:MOS channel lengthA1:DIO areaP1:DIO perimeterA2:DIO areaP2:DIO perimeterA3:DIO areaP3:DIO perimeterC:CAP valueR:RES valuesCA:BJT collector areaCP:BJT collector perimeterK:fringe cap. Attribute for piece-wise fringe cap.CLL:sum of fringe effect related to TPR
CIC National Science CouncilCh ip Implem entation Center
139
MOS Source/Drain Parameters
nrx-extract = mos[n] nmPARSET ICHI AREA PERI
LEXTRACT ICHI nsd by node xnsd
ATTACH MOS[n] xnsd &
LEXTRACT ICHI psd by node xpsd
ATTACH MOS[p] xpsd
: in *DESCRIPTION: extract mos source/drain resistance : declare variables AREA and PERI
: in *OPERATION,LEXTRACTextracts these values from layout(nsd or psd) then ATTACH appends them to MOS
****** CORNER ADJUSTMENT FACTOR = 0.5600000MM16-XI23 XI23-net320 net24 vdd! vdd! P L=1.00U W=16.00U+ AD =40.00P PD=37.00U AS=24.00P PS=19.00UMM0-XI2 net24 XI2-net320 gnd! gnd! N L=1.00U W=11.00U+ AD=27.50P PD=27.00U AS=16.50P PS=14.00U
CIC National Science CouncilCh ip Implem entation Center
140
Specifying User-Defined Equations(e.g.)R=coef *[(L-0.2)/(W+0.4)], coef:Ohm/sq
PARSET PR AREA PERI W1 W2 W L R
element res[p] pres termresLEXTRACT PR pres termres BY res[p] &equation W = (w1+w2)/2 &equation L = AREA/W &equation R = 50* ((L-0.2)/(W+0.4))
:in *DESCRIPTION
: in *OPERATION
CIC National Science CouncilCh ip Implem entation Center
141
LPE Commands
MODEL declarationDefine the model name for MOS, Diode, BJTMODEL = MOS[NM],NCH,MOS[PM],PCH,DIO[N],NDIO,DIO[P],PDIO
UNIT declarationDefine the output unit for devicesUNIT = CAPACITANCE, F AREA,p PERIMETER,u
PREFIX-PARASITIC = CAP,CCParasitic device prefix declaration
The following commands are defined in the *DESCRIPTION BLOCK
Circuit name definitionSUBCKT-NAME = TOP1
CIC National Science CouncilCh ip Implem entation Center
142
LPE Commands(cont’d)
PARASITIC device-type[subtype] reg-layer layer1 layer2 .
Define the structure of parasitic device for extractionThe recognition layer is the unique structure for identifyingthe parasitic device
ATTRIBUTE device-type[subtype] value1 value2
Define device parameter of a parasitic capacitor, must be defined after a PARASITIC definitionThe meaning of value1, value2 depends on the type of capacitor
CIC National Science CouncilCh ip Implem entation Center
143
LPE Commands(cont’d)LPECHK[options] SUBCOMMAND
Invoke LVS checks before parasitic extraction, used for back-annotation
Options :F: filter unused transistorsK: keep parallel devicesS : merge paralleled series-structureX: no input swappingC: form CMOS logic gate
SUBCOMMANDS : Specify LVS tolerance
WPERCENT, LPERCENT...
CIC National Science CouncilCh ip Implem entation Center
144
LPE Commands(cont’d)LPESELECT[options] MOS[subtype] OUTPUT netlist
Specify the device type for outputoptions
Y : Report X,Y location of the deviceK : Keep parallel structureS : Keep schematic names when output, must include
SCHEMATIC=LVSLOGIC command in *DESCRIPTIONN : Use SPICE output format
The output file name will be netlist.DAT
LPESELECT[SY] MOS &LPESELECT[SY] CAP GT 0 OUTPUT netlist
CIC National Science CouncilCh ip Implem entation Center
145
LPE Commands(cont’d)LPESELECT[options] CAP[subtype] conditions
Specify the device type for outputoptions A :Report all nodes including power node
Y :Report X,Y location of the deviceC :Report in coupled capacitance modeS :Keep schematic names when output, must include
SCHEMATIC command in *DESCRIPTIONN :Use SPICE output format
GE value
conditions :
GT valueRANGE value
CIC National Science CouncilCh ip Implem entation Center
146
Running LPE
LayoutDatabase
DeviceExtract LPE/PRE Netlist
Output
NetlistDatabase LOGLVS
Dracula
Command File
CIC National Science CouncilCh ip Implem entation Center
147
LPE Outputs*.GLOBAL vdd! gnd! VCC*.SUBCKT ARTCHIP i_inject input out******* CORNER ADJUSTMENT FACTOR = 0.5600000******MM16-XI23 XI23-net320 net24 vdd! vdd! P L=1.00U W=16.00UMM1-XI23 out XI23-net320 vdd! vdd! P L=1.00U W=16.00UMM17-XI23 XI23-net320 net24 gnd! gnd! N L=1.00U W=11.00UMM0-XI23 out XI23-net320 gnd! gnd! N L=1.00U W=11.00U*CC17-XI12 gnd! XI12-net10637 N 6.31350E-12PFCC10 gnd! out N 2.76975E-12PF*.ENDS
Note:Elements will be add ‘*’(become a comment line) in the case of un-match of LVScomparison and unavailableness of model names.
CIC National Science CouncilCh ip Implem entation Center
148
Selective LPE
• Full chip LPE may generate a large netlist that make simulation take too much time
• For most circuit, only critical nets are interested for timing verification, such as clock, global wires
• Selective LPE is used to extract RC parasitics for a specified net. It will be useful for large circuit that is timing critical on some nets or paths.
• Simulation time can be reduced as the number of parasiticsreduced
CIC National Science CouncilCh ip Implem entation Center
149
Selective LPE CommandCommand syntax:In Description block :
:in *Description, use either oneto assign selected-node
LPE-QUERY = CORE / EXPANDSELECT-MODE = SCH / LAY;assign where to select net
NODE-FILE = filenameNODE-SELECT = net1 net2 net3 ...
CORE mode select :1. Specified nodes, 2. devices connected to them3. adjacent nodes connected to the selected devices
EXPAND mode select: nets and devices on the path of selected net
CIC National Science CouncilCh ip Implem entation Center
150
Extracting a Single Net
N2
A1
VDD
VDD
VSSVSS
N1
A2A3
M1 M2
M3
M4
M5M6
M7
CORE modeNODE-SELECT = N2
Adjacent nodes = {VDD, N1, A1, A2, A3,}Devices = {M1,M2, M3,M5}
N3
EXPAND modeAdjacent nodes = {A1, A2, A3, VDD,VSS,OUT}Devices = {M1,M2, M3,M4,M5,M6,M7}
OUT
Nodes on path = {N1,N2,N3}
CIC National Science CouncilCh ip Implem entation Center
152
1. Introduction2. Structure of Command File3. Basic Operation4. Design Rule Check5. Device Extraction6. Electrical Rule Check7. Layout vs. Schematic Check8. Layout Parameter Extraction
9. Parasitic Resistance Extraction10. Extraction Interface and Reduction
CIC National Science CouncilCh ip Implem entation Center
153
Parasitic Resistance Effect
2
4
CIC National Science CouncilCh ip Implem entation Center
154
Parasitic Resistance Extraction(PRE)
•Extraction of Resistive/Capacitive Networks•Create new nodes with resistance extraction•Π model of Coupling and Fringe Capacitances•User defined threshold to short insignificant Parasitic Resistances
In1
In1_t1 In1_t2
CIC National Science CouncilCh ip Implem entation Center
155
Internal Flow of PRE
Device Extraction
Node Connection
LVS
Cross Reference Mapfor back-annotation
Resistor and Terminal Creation
Node Re-connection
Device Re-extraction
Parasitic Extraction
Netlist Creation
First Phase Second Phase
CIC National Science CouncilCh ip Implem entation Center
156
Define Cut-terminal(old syntax)
1. Parasitic Resistor and Resistor Terminal Creation
cut-term metal1 contact mres mtrmcut-term poly1 contact pres ptrm gate
ptrm
prescontactdiff
cut-term cond-layer cont-layer res-layer term-layer {term-dev}
CIC National Science CouncilCh ip Implem entation Center
157
Commands for 2nd phase PRE
2. Pad Layer Terminal Creation - defined in input layerpad-layer = pass
3. Redefine Connectivity with New Terminal Layers
rconnect-layer pwell psd nsd ptrm mtrm
stamp mtrm by metal1rconnect metal1 mtrm by contact
define in the *Input-layer block
CIC National Science CouncilCh ip Implem entation Center
158
Commands for 2nd phase PRE
4. Extract Designed Devices and Parasitic Devices with new terminal layers
5. Generate Netlist
lpeselect[s] mos &lpeselect[s] res gt 0.1 output lpeckt
element mos[n] ngate ptrm nsd pwellparasitic res[m] mres mtrmattribute res[m] 0.05
CIC National Science CouncilCh ip Implem entation Center
159
PRE Outputs
CIC National Science CouncilCh ip Implem entation Center
160
CIC National Science CouncilCh ip Implem entation Center
161
1. Introduction2. Structure of Command File3. Basic Operation4. Design Rule Check5. Device Extraction6. Electrical Rule Check7. Layout vs. Schematic Check8. Layout Parameter Extraction9. Parasitic Resistance Extraction
10. Extraction Interface and Reduction
CIC National Science CouncilCh ip Implem entation Center
162
Extraction User InterfaceAfter Dracula version 4.5.1, a user interface for automatic command file generation is provided for specifying extraction rules. PDRACULA will generate command sets
extractParasitic ( ( layers(LayerList)cap(layer1 layer2 coefficientList)fringe(layer1 layer2 piecewiseList))(resistor(resLayer sheetResValue
contact(contactLayer layer1 layer2 contcoefficient)
))
)
CIC National Science CouncilCh ip Implem entation Center
163
2D3B Parasitic Effect
d
s
2 Dimensional 3 Body Capacitance Structure
Fringe Capacitance value is closely related with nearby object
C
C is dependent on (s , d)
cap(GPOLY MET1 0.2 0.3 lateral(GPOLY (1.0 0.03)(1.5 0.02)))
CIC National Science CouncilCh ip Implem entation Center
164
Sidewall CapacitanceColinear Sidewall Down Sidewall UP
cap(MT2 MT1 0.06 0.05 0.03 0.055)
cap(layer1 layer2 valuea valueb valuec valued)valuea : overlap capacitancevalueb : colinear edge capacitancevaluec : sidewall up capacitancevalued : sidewall down capacitance
CIC National Science CouncilCh ip Implem entation Center
165
Piecewise Fringe Capacitance
d1 d2
In earily version of Dracula, the unit capacitance is C/dHowever, the capacitance is not linear with distance
PARASITIC CAP[M2] MT2 MT2 MT2ATTRIBUTE CAP[M2] 4 100.96E-18
fringe(layer1 layer1(sep1 coef1)(sep2 coef2)...)
fringe(MET1 MET1 (1.0 0.02)(1.5 0.015)(2.0 0.012))
CIC National Science CouncilCh ip Implem entation Center
166
Resistance Extraction
Resistance extraction is based on CUT-TERM concept in PRE
Resistance cut is occurred on the following cases: Bending, Contact and Max length
Command syntax:
resistor( resLayer SheetResVal [contact(contactLayerList)][device(deviceLayerList)] maxlength(length)])
contact(contactLayer layer1 layer2 contactCoefficent)
(e.g.) resistor(MET1 0.1 cont(CONT VIA))contact(VIA1 MET1 MET2 0.1 )
CIC National Science CouncilCh ip Implem entation Center
167
extractParasitic(( layers ( (NNWELLC PSUB) (NDIFFC PDIFFC) GPOLYC MT1 MT2 MT3)fringe(GPOLYC GPOLYC (0.55 0.0367E-15)(0.65 0.0313E-15)(1.0 0.0199E-15))fringe(MT1 MT1 (0.6 0.0643E-15)(0.8 0.0506E-15)(1.0 0.0417E-15))fringe(MT2 MT2 (0.6 0.0704E-15)(0.8 0.0563E-15)(1.0 0.0469E-15))fringe(MT3 MT3 (0.6 0.0963E-15)(0.8 0.0769E-15)(1.0 0.0641E-15))cap (GPOLYC NNWELLC 0.0869E-15 0.0455E-15)cap (GPOLYC PSUB 0.0869E-15 0.0455E-15)cap (MT1 NNWELLC 0.0348E-15 0.0316E-15)cap (MT1 PSUB 0.0348E-15 0.0316E-15)cap (MT1 NDIFFC 0.0554E-15 0.0394E-15)
lateral (GPOLYC (1.0 0.03)(1.5 0.02))
Extraction Rule Example
( resistor(MT3 0.032 cont(VI2) )resistor(MT2 0.063 cont(VI2 VI1) )resistor(MT1 0.069 cont(VI2 VI1 CONT) )contact(VI2 MT3 MT2 0.5)contact(VI1 MT1 MT2 0.6)
))
R of VI1
CIC National Science CouncilCh ip Implem entation Center
168
Device Reduction
Accuracylevel = 5
Accuracylevel = 2
Original segment
Use RC time constant as the approximation
CIC National Science CouncilCh ip Implem entation Center
169
Specify Device ReductionReducer is invoked by specifying REDUCER in *Description Block
Command syntax
REDUCER = YES {filename} / NO
In filename, ACCURACY_LEVEL = 4COUPLING_FACTOR = 1.5 ;A
accuracy_level : number of capacitance left between two end points1 < coupling_factor < 2 , factor for coupling capacitance convert to lumped capacitance
CIC National Science CouncilCh ip Implem entation Center
170
How Coupled Capacitance is Lumped to Ground
Couplingcapacitance
Lumped to ground
C
C = CG + A * CC
total C = CG(C to gnd) + A(coupling factor) * CC (coupling C)
A= 2 for different signal level
A= 1 for grounded line
A= 0 for same signal level
CC
CIC National Science CouncilCh ip Implem entation Center
171
References1. Dracula on-line user manual2. Dracula standalone verification training manual3. New Dracula enhancements & RCX flow