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Basic MOS Device Physics
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Topics
MOS Structure
MOS IV Characteristics
Second Order Effects MOS Device Models
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NMOS Structure
LD is caused by side diffusion
Source: the terminal that provides charge carriers.(electrons in NMOS)
Drain: the terminal that collects charge carriers.
Substrate contact--toreverse bias the pn junctionConnect to most negative supply voltagein most circuits.
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CMOS Structure
PMOSNMOS
Reverse bias the pnjunction
Reverse bias the pnjunction
Connect to most positive
supply voltage in most circuits.
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Symbols
In Digital CircuitsThis textbook
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MOS IV Characteristics
Threshold Voltage
Derivation of I/V Characteristics I-V curve
Transconductance
Resistance in the linear region
Second Order Effect
Body Effect Channel Length Modulation
Subthreshold conduction
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Threshold Voltage
1. Holes are expelled from the gate area2. Depletion region (negative ions) is
created underneath the gate.
3. No current flows because no chargecarriers are available.
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Threshold (2)
Two capacitors in series:Cox: capacitance between the gate and oxide/silicon interface
Cdep: capacitance of the depletion region
As VG increases, the potential at the oxide/silicon increases.
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Threshold Voltage (3)
When the surface potential increases to acritical value, inversion occurs.1. No further change in the width of the
depletion region is observed.2. A thin layer of electrons in the depletion
region appear underneath the oxide.3. A continuous n-type (hence the name
inversion) region is formed between thesource and the drain. Electrons can nobe sourced from S and be collected atthe drain terminal. (Current, however,
flows from drain to source)4. Further increase in VG will fruther incrase
the charge density.
The voltage VG required to provide an
inversion layer is called the threshold voltage.
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Body Effect
The n-type inversion layer connects the source to the drain.The source terminal is connected to channel. Therefore,
A nonzero VSB introduces charges to the Cdep.The math is shown in the next slide.
A nonzero VSB for NFET or VBS for PFET has the net effectOf increasing the |VTH|
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Math for Body Effect
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Experimental Data of Body
Effect
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W/L=12 um/0.12umCMOS: 0.13 um processVDS=50 mVSimulator: 433 mVAlternative method: 376 m
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Subthreshold current
Subtresholdregion
As VG increases, the surfacepotential will increase.
There is very little majority carriersunderneath the gate.
There are two pn junctions. (B-S and B-D)The density of the minority carrierdepends on the difference in thevoltage across the two pn junction diode.
A diffusion current will result the electron densities
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Threshold Voltage
VG=0.6 V
VD=1.2 V
CMOS: 0.13 um W/L=12um/0.12 um
NFET
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Implantation of p+ dopants to
alter the threshold
Threshold voltage can be adjusted by implantingDopants into the channel area during fabrication.
E.g. Implant p+ material to increase threshold voltage.
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Formation of Inversion Layer in a
PFET
The VGS must be sufficientnegative to produce an inversionlayer underneath the gate.
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I-V Characteristics
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Channel Charge
A channel is formed when VG is increased to the point
that the voltage difference between the gate andthe channel exceeds VTH.
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MOSFET as a variable resistor
The conductive channel between S and D can be viewed
as resistor, which is voltage dependent.
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Application of VDS
What happens when you introduce a voltage at the drain terminal?
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Channel Potential Variation
VX the voltage along the channel
VX increases as you move from S to D.
VG-VX is reduced as youmove from S to D.
E.g. VS=0, VG=0.6, VD=0.6At x=0, VG-VX=0.6 (more than VTH)At x=L, VG-VX=0 (less than VTH)
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Pinch Off
Small VDS
Large VDS
No channel
Electrons reaches the D
via the electric field in thedepletion region
SaturationRegion
LinearRegion
Conceptual Visualization of
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Conceptual Visualization of
Saturation and Triode(Linear)
Region
NMOS
PMOS
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I-V Characteristic Equations for
NMOS transistor
(Triode Region:VDSVGS-VTH
To produce a channel (VGS>VTH)
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I-V characteristic Equation for
PMOS transistor
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MOSFTE as a controlled linear
resistor
1. Take derivative of ID
with respect to VDS
2. For small VDS, the drain resistance is
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Example
Ron=233.625 Ohms
VS=100/(100+233.625)*100 mV=29.97 mV
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Sweep VGS to change MOS
resistance and VS
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Transistor in Saturation Region
I-V characteristics
Transconductance
Output resistance Body transconductance
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Saturation of Drain Current
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Transconductance
Analog applications:How does ids respond to changes in VGS?
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IDS vs VGS
0.13 um NMOSVDS=0.6 VW/L=12um/0.12 umVB=VS=0
Y axis: idsX axis: Vgs
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Different Expressions of
Transconductance
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Transconductance in the triode
region
(Triode region)
For amplifier applications, MOSFETs are biased in saturation
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gm as function of region
saturation
0.13 um NMOSVGS=0.6 VW/L=12um/0.12 um
VB=VS=0Y axis: gmX axis: vds
linear
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Channel Length Modulation
As VDS increases, L1 will move towards the source, sincea larger VDS will increase VX .
L is really L1
ID will increase as VDS increases.The modulation of L due to VDS is called channel length modulation.
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Controlling channel modulation
For a longer channel length, the relative change in L andHence ID for a given change in VDS is smaller.
Therefore, to minimize channel length modulation, minimum
length transistors should be avoided.
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gds
saturation
0.13 um NMOSVGS=0.6 VW/L=12um/0.12 um
VB=VS=0Y axis: gmX axis: vds
linear
Slope due tochannel lengthmodulation
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Output resistance due to gds
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More on Body Effect
Example
Analysis
gmbs
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Variable S-B Voltage
constant
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VTH as a function of VSB
(VTH0: with out body effect)
Body effect coefficient
VSB dependent
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Sensitivity of IDS to VSB
(chain rule)
gm
=1/3 to 1/4, bias dependent
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Small Signal Model
If the bias current and voltages of aMOSFET are only disturbed slightly bysignals, the nonlinearamd large signal
model an be reduced to linearandsmall signal representation.
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Small signal model of an NMOS
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MOS Device Layout
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MOS Capacitances
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Bias dependent CGS and CGD
C l t NMOS S ll Si l
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Complete NMOS Small Signal
Model
C l t PMOS S ll Si l
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Complete PMOS Small Signal
Model