Module 11
Bus Interface Design
Module 11
Bus Interface Design
이론 3시간
이혁재
서울대학교
학습목표
• AMBA AHB bus protocol을 이해한다.
• Bus specification에서 protocol이 기술되는 방식을 익힌다.
• 여러가지 bus protocol과 AHB의 차이점을 이해하고, 이를통하여 AHB 버스의 특징을 파악한다.
• Off-chip bus protocol과 on-chip bus 프로토콜의 차이점을이해하고, 이를 통하여 on-chip bus의 특징을 파악한다.
모듈구성
선택필수
SoC 구조
Embedded Processor I, II
Embedded Memory
Typical Logic Blocks
External Interface
On-Chip Bus Architecture
Bus Interface Design
실습
Processor 설계실습I, II
간단한 SoC 설계실습 I, II
Reconfigurable Processor
Architecture
Low Power SoC Design I, II
Network-on-Chip
Introduction
Introduction to SoC Architecture
Review of Processor
Architecture
강의자료활용 Guideline
• "1. AMBA AHB Protocol"에서는 SoC on-chip bus를 널리사용되는 AHB protocol을 자세하게 설명을 한다.
• "2. Other On-chip Bus Protocols "에서는 다른 on-chip bus protocol과 AHB의 차이점을 비교 설명한다.
• "3. Comparison with Off-chip Bus Protocols"에서는 Off-chip bus에 대해서 간단히 설명을 하고, 이를 AHB와 비교한다. 강의진행 시간에 따라서, 이 부분은 생략할 수 있다.
Contents
1. AMBA AHB Protocols
2. Other On-chip Bus Protocols
3. Comparison with Off-chip Bus Protocols
4. Summary
5. Exercises
6. References
AMBA
• Advanced Microprocessor Bus Architecture
• On-chip bus protocol proposed by ARM
• Very simple protocol
• A design guideline for correct communication between multiple IPs
• High bandwidth bus
– AHB (Advanced High-performance Bus)
– ASB (Advanced System Bus)
• Low bandwidth bus
– APB (Advanced Peripheral Bus)
On-Chip Bus (OCB)
• Interconnect components inside a single chip
CPU On-chipRAM
DMABus
Master
BRIDGE
UARTExternalMemoryInterface
Timer
PIOKeypad
High bandwidthbus
Low bandwidthbus
AMBA AHB Components
slave #1 slave #3
AMBA AHB
master #1 master #2
slave #2
arbiter
Basic Signals for Read Txn
master slave
HADDR[31:0]HRDATA[31:0]HRESP[1:0]
master slave
HCLK
master
Operation for a Read Txn
AHADDR[31:0]
HRESP[1:0]
HCLK
Data (A)HRDATA[31:0]
OK (A)
Address Phase Data Phase
Pipelined Operation
HADDR
HRESP
HCLK
A1
Data (A1)HRDATA
OK (A1)
Address Phase (A1) Data Phase (A1)
Data (A2)
OK (A2)
A2
Address Phase (A2) Data Phase (A2)
HREADY for a Slow Slave
master slave
HADDR[31:0]HRDATA[31:0]HRESP[1:0]HREADY
master slave
HCLK
master
Wait State Insertion
HADDR
HRESP
HCLK
A
Data (A)HRDATA
OK (A)
Slave Not Ready Slave Giving Data
Wait StateHREADY
Operation for Write Txn
HADDR[31:0]HRDATA[31:0]HRESP[1:0]HREADYHWRITEHWDATA[31:0]
master slave
HCLK
master
Operation for a Write Txn
AHADDR[31:0]
HRESP[1:0]
HCLK
Data (A)HWDATA[31:0]
OK (A)
HWRITE
Address Phase Data Phase
Response Type
HRESP[1:0] Response Description00 OKAY Transaction Completed
01 ERROR Error Occurs
10 RETRY Transaction Not Completed
Master Must Retry
11 SPLIT Transaction Not Completed
Master Must Retry
Slave Informs Completion
ERROR/RETRY/SPLIT: two cycle response
Two Cycle Response
HADDR
HRESP
HCLK
A
HRDATA
RETRY (A)RETRY (A)
HREADY
Timing Diagram Practice
HCLK
HADDR
HRESP
HRDATA
HREADY
A1 A2 A3 A4
A1 A2
OK OK RETRY RETRY
A5 A4
A4A3
OK OK OK
Timing Diagram Practice
HCLK
HADDR
HRESP
HRDATA
HREADY
A1 A2 A3 A4
A1 A2
OK OK OK
A5
RETRY RETRY
A4A5
A3
OK
Burst Operation Signals
slave
HADDR[31:0]HRDATA[31:0]HRESP[1:0]
master
HREADYHWRITEHWDATA[31:0]HTRANS[1:0]HBURST[2:0]HSIZE[2:0]
Burst Mode
HBURST[2:0] Type Description000 SINGLE Single transfer
001 INCR Incrementing burst of unspecified length
010 WRAP4 4-beat wrapping burst
100 WRAP8 8-beat wrapping burst
011 INCR4 4-beat incrementing burst
101 INCR8 8-beat incrementing burst
110 WRAP16 16-beat wrapping burst
111 INCR16 16-beat incrementing burst
Transfer Type
HTRANS[1:0] Type Description00 IDLE No data transfer required
Requires zero wait state OKAY response
01 BUSY Same as IDLE between burst transfers
Address/Control unrelated previous
10 NONSEQ Single transfer or the first of a burst
to the previous transfer
11 SEQ Remaining transfers in a burst
Address/control related
to the previous transfer
Transfer Size
HSIZE[2:0] Size Description000 8 bits Byte
001 16 bits Halfword
010 32 bits Word
100 128 bits 4-word line
011 64 bits -
101 256 bits 8-word line
110 512 bits -
111 1024 bits -
Transfer Type Examples
HCLK
NONHTRANS BUSY SEQSEQ SEQ
0x20
HBURST
HADDR 0x24 0x2C0x24 0x28
INCR
Word
0x20 0x2C
HSIZE
HREADY
0x24 0x28HRDATA
Four-beat Wrapping Burst
HCLK
NON SEQ SEQHTRANS SEQ
0x38
HBURST
HADDR 0x3C 0x340x30
HSIZE
HREADY
0x38 0x30 0x34HRDATA 0x3C
WRAP4
Word
Four-beat Incrementing Burst
HCLK
NON SEQ SEQHTRANS SEQ
0x38
HBURST
HADDR 0x3C 0x440x40
INCR4
WordHSIZE
HREADY
HRDATA 0x38 0x40 0x440x3C
Undefined-length Bursts
HCLK
NON SEQ NON SEQHTRANS SEQ
0x20 0x22
HBURST
HADDR 0x5C 0x640x60
INCR
Word
0x20
HSIZE
HREADY
0x22 0x60 0x64
INCR
Halfword
0x5CHRDATA
Arbitration
Which master uses the bus ?
Master#1
Slave#1 Slave#2
Master#2 Master#3
Slave#3
Arbitermux
Decoder mux
Arbitration Signals
slave
HADDR[31:0]HRDATA[31:0]HRESP[1:0]
master
HREADYHWRITEHWDATA[31:0]HTRANS[1:0]HBURST[2:0]HSIZE[2:0]
HBUSREQxHGRANTx
Arbiter
Arbitration Phase
• A bus master uses the HBUSREQx signal to request access to the bus.
• The arbiter will sample the request on the rising edge of the clock and then … decide which master will be the next to gain access to the bus
• A master gains ownership of the address bus when HGRANTx is HIGH and HREADY is HIGH at the rising edge of HCLK.
Arbitration Phases
HCLK
HBUSREQx
HGRANTx
HTRANS NONSEQ
DATAHRDATA
OKHRESP
Request Grant Address Data
Undefined Length Burst
• For undefined length bursts the master should continue to assert the request until it has started the last transfer.
• The arbiter cannot predict when to change the arbitration at the end of an undefined length burst.
Undefined Length Burst
HBUSREQx
HTRANS
HCLK
HGRANTx
HBURST
HRESP OK
NON SEQ SEQ SEQ
INCR
OK OK OK
Fixed Length Burst
• When a master is granted the bus and is performing a fixed length burst it is not necessary to continue to request the bus in order to complete the burst.
• The arbiter observes the progress of the burst and uses the HBURST[2:0] signals to determine how many transfers are required by the master.
• Normally the arbiter will only grant a different bus master when a burst is completing. However, if required, the arbiter can terminate a burst early to allow a higher priority master access to the bus.
Fixed Length Burst
HBUSREQx
HTRANS
HCLK
HGRANTx
HBURST
HRESP OK
NON SEQ SEQ SEQ
WRAP4
OK OK OK
Arbitration Example: Slow Grant
HBUSREQx
HADDR
HCLK
HGRANTx
HRDATA
HRESP
A
A
A
DATA(A)
OK (A)
Arbitration Example: Two Masters
HBUSREQ1
HTRANS
HCLK
HBUSREQ2
HBURST
HRESP
HGRANT1
HGRANT2
NON SEQ SEQ NONSEQ
WRAP4INCR4
OK OK OK OK
Arbitration Example: Two Masters
HBUSREQ1
HTRANS
HCLK
HBUSREQ2
HBURST
HRESP OKOK
HGRANT1
HGRANT2
INCR
SEQ
OK
SEQNON SEQ IDLE
OK
AMBA AHB Summary
• Pipelined transfer
• Burst transfers
• Split Txns (Transactions)
• Single cycle bus master handover
• Single clock edge operation
• Non-tristate implementation
• Wider data bus configurations (64/128 bits)
Contents
1. AMBA AHB Protocols
2. Other On-chip Bus Protocols
3. Comparison with Off-chip Bus Protocols
4. Summary
5. Exercises
6. References
IBM PLB (Processor Local Bus)
IBM PLB (Processor Local Bus)
• The example in the previous slide
– Both address, write-data and read-data bus are utilized at same time.
– Higher bus utilization than AHB
• To support high bus utilization
– Address and data phases are not aligned
– Maintain multiple outstanding transactions
– Acknowledge the second address cycle even though the data cycle of the first address cycle is incomplete
• fast acknowledgement of address cycle
• reduce address cycle pressure
AMBA APB
• APB: Advanced Peripheral Bus
• Low power
• Latched address and control
• Simple interface
• Suitable for many peripherals
• No wait state allowed
• No burst transfers
• No arbitration (bridge the only master)
• No pipelined transfer
• No response signal
Operation for a Read Txn
PADDR
PSELx
PCLK
A
PWRITE
Setup Phase Enable Phase
PRDATA
PENABLE
DATA (A)
Operation for a Write Txn
PADDR
PSELx
PCLK
A
PWRITE
Setup Phase Enable Phase
PWDATA
PENABLE
DATA (A)
APB Operation Example
A1 A2 A3
A1
PCLK
PADDR
PSELx
PWRITE
PRDATA
PENABLE
A4
A4
A2
A3
PSELy
PWDATA
WISHBONE
• Opencore standard interconnect architecture
• Single cycle data transfer
WISHBONE
• Single READ transaction Single WRITE transaction
AMBA AXI
• Separate address/control and data phases
• Support for unaligned data transfers using byte strobes
• Burst-based transactions with only start address issued
• Separate read and write data channels
• Multiple outstanding addresses
• Out-of-order transaction completion
• Easy addition of register stages
AMBA 3.0 AXI
• Channel architecture
– Four groups of signals
• Address “A” signal name prefix
• Read “R” signal name prefix
• Write “W” signal name prefix
• Write Response “B” signal name prefix
ADDRESS WRITE DATA
READ DATA RESPONSE
AMBA 3.0 AXI
• To read ..
ADDRESS WRITE DATA
1. Master issues address
READ DATA RESPONSE
2. Slave returns data
AMBA 3.0 AXI
• To write ..
ADDRESS WRITE DATA
1. Master issues address
2. Master gives data
READ DATA RESPONSE
3. Slave acknowledges
AMBA 3.0 AXI
• Channels - One way flow
– Each channel has information flowing in one direction only
– READY is the only return signal
AVALID RVALID BVALIDWVALIDADDR WLAST RLAST BRESP
WDATAAWRITE RDATA BIDWSTRBALEN RRESP BREADYWIDASIZE RIDWREADYABURST RREADY
ALOCKACACHEAPROTAIDAREADY
AMBA 3.0 AXI
• Register slices for max frequency
– Register slices canbe applied across any channel
– Allows maximum frequency of operation by matching channel latency to channel delay
– Allows system topology to be matched to performance requirements
WREADY
WIDWDATAWSTRBWLAST
WVALID
AMBA 3.0 AXI
• Write burst
AMBA 3.0 AXI
• Example Register Slices
Master#1
Master#2
Slave#1
Slave#2
Slave#3
Slave#4
A
A
A
A
A
A
Master#1
Master#2
Slave#1
Slave#2
Slave#3
Slave#4
A
A
A
A
A
A
Master#1
Master#2
Slave#1
Slave#2
Slave#3
Slave#4
A
A
A
A
A
A
Isolate addresstiming
R
R
R
R
R
R
R
R
R
R
R
RIsolate poor
read data setupBreak long
interconnect path
AMBA 3.0 AXI
• AMBA 2.0 AHB Burst
– AHB Burst
• Address and Data are locked together
• Single pipeline stage
• HREADY controls intervals of address and data
A21 A22 A23A11 A12 A13 A14
D21 D22 D23D11 D12 D13 D14
A31
D31
ADDRESS
DATA
AMBA 3.0 AXI
• AXI - One Address for Burst
– AXI Burst
• One Address for entire burst
A21A11
D21 D22 D23D11 D12 D13 D14
A31
D31
ADDRESS
DATA
AMBA 3.0 AXI
• AXI - Outstanding Transactions
– AXI Burst
• One Address for entire burst
• Allows multiple outstanding addresses
A21A11
D21 D22 D23D11 D12 D13 D14
A31
D31
ADDRESS
DATA
AMBA 3.0 AXI
• Out of Order Interface
– Each transaction has an ID attached
• Channels have ID signals - AID, RID, etc.
– Transactions with the same ID must be ordered
– Requires bus-level monitoring to ensure correct ordering on each ID
• Masters can issue multiple ordered addresses
AMBA 3.0 AXI
• AMBA 2.0 AHB Burst - Slow slave
– With AHB
• If one slave is very slow, all data is held up.
A21 A22 A23A11 A12 A13 A14
D11 D12
A31ADDRESS
DATA
AMBA 3.0 AXI
• AXI - Out of Order Completion
– Out of order completion allowed
– Fast slaves may return data ahead of slow slaves
– Complex slaves may return data out of order
A21A11
D21 D22 D23 D11 D12 D13 D14
A31
D31
ADDRESS
DATA
AMBA 3.0 AXI
• AXI - Data Interleaving
– Returned data can even be interleaved
– Gives maximum use of data bus
– Note - Data within a burst is always in order
A21A11
D21 D22 D23D11 D12 D13 D14
A31
D31
ADDRESS
DATA
AMBA 3.0 AXI
• AXI Multi-layer
– Parallel paths between masters and slaves
– Key Advantages
• Increased bandwidth
• Design flexibility
– Uses the same interface protocol
Master#1
Master#1
Slave#4
Slave#4
BusMatrixBus
Matrix
Master#2
Master#2
Master#3
Master#3
Slave#3
Slave#3
Slave#2
Slave#2
Slave#1
Slave#1
Open Core Protocol
• Main goal: to achieve IP-reuse
• Reconfigurable back-bone bus optimize die area
• Basic signals and extended signals
• Inclusion of sideband signals
Sonics’ MicroNetwork
• Auto generation of bus architecture• Use of OCP • IP-wrapper-OCP-Agent-Network
Sonics’ MicroNetwork
• Sonics StudioTM
– Difficult to register an IP and generate its wrappers
SNP: A Phase-based Communication Protocol
control
address
data
on-chip bus
control
data
addr addr
WA
control
CO
single channel
phase selection
time
SNPphase-basedcommunication
time
3 cyclessmall numberof wires
1 cyclelarge numberof wires trade-off
time wire
data
WD
SNP: A Phase-based Communication Protocol
numbers of wireslarge small
hardwaresimple complex
latencysmall large
addr
WA
control
CO
data
WD
time
SNPphase-basedcommunication
on-chip bus
control
address
data
• Goal of the new protocol:
– small wires, simple hardware, small latency
Contents
1. AMBA AHB Protocols
2. Other On-chip Bus Protocols
3. Comparison with Off-chip Bus Protocols
4. Summary
5. Exercises
6. References
PC Architecture
CPU CPU
FSB (Front Side Bus)
North Bridge(Host/PCI Bridge)
MainMemory
AGPAccelerator
Monitor
South BridgeSCSIHBA
EthernetNCA
PCI SlotsPCI Bus
Hard Drive, CD-ROM
Ethernet HD USBISA Bus
Keyboard, Floppy Diskette,Mouse, Printer, Speaker,,,
FSB: Two Cycle Response
• Large propagation delay
• Flopping of input/output signals
• Two cycle response
ADDR
TRDY#
DATA
slave master
FF
FF
FF
FF
FF
FF
FSB: Two Cycle Response
• TRDY#: Target ready to accept data – Symbol ‘#’ represents an active low signal
• Cycle 2: Decode ADDR and Drive TRDY internally
• Cycle 3: Drive TRDY# on the bus
ADDR
CLK
TRDY#
A
DATA(A)
1 2 3 4 5 6 7 8
DATA
Out-of-order Execution Signals
• RESP: defer response
– Transaction not completed, but not retried
– The next transaction can be initiated without the completion of the deferred Txn.
• IDS#: completion of a deferred Txn.
• DID: deferred Txn. ID
– Indicates which deferred transaction is completed
– Supports multiple deferred transactions
PCI Signals
• AD: Address or Data
• C/BE#: Command or byte enable
• FRAME#: the start and duration of a Txn.
• TRDY#: Target ready to complete data phase
• IRDY#:
– Write: the initiator is driving valid data
– Read: the initiator is ready to accept data
• DEVSEL#: Target has decoded its address
PCI: Write Txn.
Sharing of address and data buses
AD[31:0]
IRDY#
CLK
A Data (A)
C/BE#[3:0] Byte EnablesWRITE
FRAME#
TRDY#
DEVSEL#
PCI: Read Txn.
• The use of AD bus for both address and data causes one turnaround cycle for Read Transaction
AD[31:0]
IRDY#
A Data (A)
C/BE#[3:0] Byte EnablesREAD
FRAME#
TRDY#
Turnaround cycleDEVSEL#
PCI: Non-pipelined Back-to-back Operation
AD[31:0]
IRDY#
CLK
C/BE#[3:0]
FRAME#
TRDY#
DEVSEL#
BA
WR WR
D(A) D(B)
PCI: Non-pipelined Operation/Turnaround Cycle
AD[31:0]
IRDY#
CLK
C/BE#[3:0]
FRAME#
TRDY#
DEVSEL#
BA
RD
D(A) D(B)
WR
turnaround
On-Chip Bus Characteristics
HADDR[31:0]
HRESP[1:0]
HCLK
A
Data (A)HRDATA[31:0]
OK (A)
Address Phase Data Phase
• Short propagation delay
• Fast response possible
On-Chip Bus Characteristics
• Non-tristate implementation
Sender#1
Receiver#1 Receiver#2
Sender#2 Sender#3
Receiver#3
Arbitermux
On-Chip Bus Characteristics
• Less limitation in the number of wires
• Separate address, read data, and write data bus
• Wider data bus configurations (64/128 bits)
Master#1
Slave#1 Slave#2
Master#2 Master#3
Slave#3
Arbitermux
HWDATAHRDATA
Decoder mux
On-Chip Bus Characteristics:
• Non-efficient bus utilization
• In-order transaction: the next transaction cannot proceed till the completion of the previous transaction
• Broadcasting architecture (not point-to-point)
• No (or minimal) transaction command: just for simple data transfer
• No parity error
• Very simple protocol
• Users design bus components by themselves
Contents
1. AMBA AHB Protocols
2. Other On-chip Bus Protocols
3. Comparison with Off-chip Bus Protocols
4. Summary
5. Exercises
6. References
4. Summary
• AMBA AHB의 특징
– Very simple protocol
– Pipelined transfer
– Burst transfers
– Split Txns (Transactions)
– Single cycle bus master handover
– Single clock edge operation
– Wider data bus configurations (64/128 bits)
– Non-efficient bus utilization allowed
– In-order transaction: the next transaction cannot proceed till the completion of the previous transaction
– Broadcasting architecture (not point-to-point)
– just for simple data transfer
– No parity error
– Users design bus components by themselves
Contents
1. AMBA AHB Protocols
2. Other On-chip Bus Protocols
3. Comparison with Off-chip Bus Protocols
4. Summary
5. Exercises
6. References
5. Exercises
1. AMBA AHB에서 어떠한 transaction type 있는지 나열하고, 그차이점을 설명하시오.
2. AMBA AHB에서 어떠한 response type 있는지 나열하고, 그차이점을 설명하시오.
3. AMBA AHB에서 버스를 사용하는 master가 single cycle에바뀌기 위한 조건은 무엇인가?
4. PLB와 AHB의 차이점을 설명하시오
5. Wishbone과 AHB의 차이점을 설명하시오.
6. AXI와 AHB의 차이점을 설명하시오.
7. AHB와 APB의 차이점을 설명하시오.
8. On-chip bus와 off-chip bus의 차이점을 설명하시오.
Contents
1. AMBA AHB Protocols
2. Other On-chip Bus Protocols
3. Comparison with Off-chip Bus Protocols
4. Summary
5. Exercises
6. References
6. References
• [1] ARM, AMBA Specification, http://www.arm.com, 1999.
• [2] IBM, Coreconnect Bus Architecture, http://www.chips/ibm/products/coreconnect, 1999
• [3] WISHBONE Specification, http://www.opencores.org/wishbone
• [4] OCP International Partnership, Open Core Protocol Specification, http://www.ocpip.org, 2001
• [5] ARM, AMBA AXI protocol specification, 2003.
• [6] SNP Specification, http://capp.snu.ac.kr, 2002