Boolean Algebra
Application to electric switches (open - 0, closed - 1):
a
b
c220V~
L
L = (a + b)c = ac + bc
b c220V~
L
L = ac + bc
ca
Variables: only 2 values (0,1)Huntington’s (1804) axioms:1 1 = 1 0 + 0 = 0a 0 = 0 a + 1 = 1a a’ = 0 a + a’ = 1a b = b a a + b = b + aa(b+c)=ab+ac a+bc=(a+b)(a+c)
Verification by truth table:abc (a+b)c ac+bc000 0 0001 0 0010 0 0011 1 1100 0 0101 1 1110 0 0111 1 1
Every logical function can be specified by truth table and implemented as sum of product form,e.g. L = a’bc + ab’c + abc.
a+b
Combinational Circuits
a a’ NOT
OR
a
ba+b
Switch light L implemented by gatesL = a’bc + ab’c + abc sum of products.
Function presentation by Karnough mapevery product term has a field, and neighboringfields differ by only one variable. Example (three input variables):
L = abc + ab’c + a’bc = abc + ab’c + abc + a’bc = ac(b + b’) + bc(a + a’) = ac + bc = (a + b)c
Output is direct function of inputs
b
a
c
L
1 1
1
a
bab
a b c
L
a
bc
L
2
Decoders and Multiplexers
Decoder has n inputs and 2n outputs:
AB
BA 00 01 10 11
Mux determines which input will connect to output:
S[1:0]
A B C D
1 1 1 1
A B C D
1
OUT
OUT
S
Binary Adder Designa0a3 a2 a1b3 b2 b1 b0
c3 c2 c1 c0c4
s3 s2 s1 s0
ab
s
co ci
Truth Tablea b ci s co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Karnough maps
a
b
ci
a
b
ci
s = ab ci +ab ci’+a’b’ ci +a’b’ ci’=(ab + a’b’)ci +(ab + a’b’)ci’ =(a + b’) + ci =a + b’ + ci
co = ab + aci + bci
1 1
1
1
1
1
1
1
a b ci
s
co
Programmable Logic Arrays PLA
X
ABC
Y
Any logical function can be implemented by two levels circuits: ANDs and ORs.
c
a
b pCC
a b p
0 0 stable
0 1 0
1 0 1
1 1 x
a
p
b
time
c
b
a
p
x
x
1
0
0
1
0
1
a: 1 0
a: 0 1
b: 1 0
b: 0 1
c
b
ax
x
1
0
0
1
0
1
p = a + b’c
b’
p
c
a
p’a
b p
Design of the RS flip-flop
RegistersOne bit register = memory cell
WE = Clock pulse in bit
gate
RS
out bit
WE
b5 b4 b3b2 b1b7 b6
b0
Eight bit register
The Concept of Memory
address decoder
N addresslines (bus)
address space = 2N
M data lines (bus)
WEmemory 0
memory 1
memory 2
memory 3
memory 4
memory 5
memory 6
memory 7
Memory as array of registers: address space and addressability
Memory details
word select word WEaddress
writeenable
input bits
output bits
Q’
Q
K
J
CL
A opensmaster accepts
B opensslave accepts
B closes
A
A
B
B
A closes
master slave
At no time the path between inputs JK and outputs QQ’ is closed.
Design of the JK flip-flop
CC
clock
A
B
Input Output
Present state
Nextstate
* Output is a function of Input and Present state.* Next state is a function of Input and Present state.* Present state is delayed Next state.
Synchronous Sequential Circuit
StateSW current next outputSW E1 E2 E1+ E2+ 1,2 3,4 5
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 00 1 0 0 0 0 0 00 1 1 0 0 0 0 01 0 0 0 1 0 0 01 0 1 1 0 1 0 01 1 0 1 1 1 1 01 1 1 0 0 1 1 1
Combinational Circuit
Traffic warning sign
1
2
3
45
SW
All off
1,2 on
1,2,3,4 on
All on
00 01
1011
0,1 0
00
1
1
1
SW 1,23,45
Cl
E1
E2
E1 E2
SW
E1+ = SW E1’ E2 + SW E1 E2’E2+ = SW E1’ E2’ + SW E1 E2’
1,2 = E1+ + SW E1 E23,4 = E1+ + SW E1 E2 5 = SW E1 E2
E1+
E2+
1,2
3,4
5
E1+
E2+
E1
E2
SW
Combinational Circuit
000
110
010011
001
0
0
0
1 1
1
110
0
a b c Next State
Reversible counter modulo 5
a+ = a’bc’I’ + b’c’I
b+ = (c + a’b) I’ + c’I
c+ = ab’ + b’I’ + a’b I
a+
b+
c+
a
b
c
I
CL
0
0
0
01
000 0
1 0
0 0
x x
x
x x
xa
b
c
I
01
101 0
1 1
0 1
x x
x
x x
1a
b
c
I
10
100 1
0 1
0 0
x x
x
x x
1a
b
c
I
a+ = a’bc’I’ + b’c’I b+ = (c + a’b) I’ + c’I c+ = ab’ + b’I’ + a’b I