Download - BBIC 12 FFT Circuit Design
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FFT Circuit Design
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Applications of FFT in Communications
Fundamental FFT Algorithms
FFT Circuit Design Architectures
Conclusions
Outline
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DAB Receiver
256/ 512/
1024/ 2048
point FFT
Tuner OFDMDemodulator
ChannelDecoder
Mpeg2
AudioDecoder
PacketDemux
Controller
Control Panel
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WLAN OFDM System
RECEI VER
FEC
CoderS/P
IFFT
64-pt
GuardInterval
Insertion
D/ALPF
UpConverter
TRANSMI TTER
MAC
Layer6Mbps
~54Mbps
FEC
DecoderP/S
FFT
64-pt
GuardInterval
Removal
A/D
LPF
Down
Converter
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ADSL (Discrete Multi-tune) System
receivefilter
+A/D
P/SQAM
decoders FEQ
S/PQAM
encoders
IFFT
512-pt
addcyclic
prefix
P/SD/A +
transmit
filter
FFT
512-pt S/P
remove
cyclicprefix
TRANSMI TTER
RECEI VER
TEQ
channel
Data
In
Data
Out
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Applications of FFT in Communications
Comm.
System
WLAN DAB DVB ADSL VDSL
FFT Size 64 256/512/
1024/2048
2048/
8192
512 512/1024/
2048/4096
OFDM DMT
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Applications of FFT in Communications
Fundamental FFT Algorithms
FFT Circuit Design Architectures
Conclusions
Outline
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Fundamental FFT Algorithms
Discrete Fourier Transfer Pair
Radix-2FFT (N= 2)
Decimation-in-time (DIT) Decimation-in-frequency (DIF)
FFT for composite N (N = N1 N2)
Cooley-Tukey Algorithms
Radix-r FFT
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Discrete Fourier Transform Pair
][][ kXnxDFT
.)/2( NjN eW =
,1...,,1,0,][][1
0
==
=
NkWnxkXkn
N
N
n
,1...,,1,0,][N
1][
1
0
==
= NnWkXnx knNN
n
Let
denote a DFP pair.
Where,
We have
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Observations
WNk
is N-periodic.
WNkis conjugate symmetric.
Both x[n]and X[k]are N-periodic.
Ifx[n]is real, then X[k]is conjugate symmetric
and vice versa.
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Observations
A direct calculation requires approximately N2
complex multiplications and additions.
FFT algorithms reduce the computation
complexity to the order ofN log N.
Algorithms developed for FFT also works forIFFT with only minor modifications.
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Example: Zero-Padding (WLAN)
WLAN 52 sub-carriers: use 64-point FFT.Null#1#2..#26NullNull
Null#-26..
#-2#-1
IFFT
012
2627
3738
6263
012
2627
3738
6263
TimeDomainOutputs
Sub-carriers
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Decimation-in-Time Radix-2FFT
1,,0
]12[]2[
][][
2/
12/
0
2/
12/
0
1
0
=
+=
++=
=
=
=
=
Nk
H[k]WG[k]
WrxWWrx
WnxkX
k
N
kr
N
N
r
k
N
kr
N
N
r
kn
N
N
n
K
Assume N is an even number.
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Observations
G[k]is DFT of even samples ofx[n].
H[k]is DFT of odd samples ofx[n].
G[k]and H[k]are N/2-periodic.
WNk+N/2 = - WN
k.
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DIT Radix-2 FFT
.2/0
,-
,]2/[
,][)2/(
Nr
H[r]WG[r]
H[r]WG[r]NrX
H[r]WG[r]rX
rN
Nr
N
rN
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Decimation-in-Time Radix-2FFT
Butterfly for Radix-2 DIT FFT
(M-1)th stage Mth stageWN
r
-WNr
(M-1)th stage Mth stage
WNr -1
In-place Computation
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Decimation-in-Time Radix-2FFT First layer decimation
N/2-point
DFT
x[0]
x[2]
x[4]
x[6]
N/2-pointDFT
x[1]
x[3]
x[5]
x[7]
G[3]
H[3]
H[2]
H[0]
G[2]
G[0]
G[1]
X[0]
X[1]
X[7]
X[6]
X[5]
X[4]
X[3]
X[2]
H[1] WN0
WN3
WN
2
WN1
-1
-1
-1
-1
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Decimation-in-Time Radix-2FFTx[0]
x[4]-1WN0
x[6]
x[2]
-1WN0
x[5]
x[1]
-1WN0
x[7]
x[3]
-1WN0
-1
-1
WN0
WN2
-1
-1WN
0
WN2
X[0]
X[7]
X[6]
X[5]
X[4]
X[3]
X[2]
X[1]
-1
-1
-1
-1
WN
0
WN2
WN1
WN3
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Bit Reversal
x[n2 n1 n0] x[1 1 0]
x[1 0 0]
x[0 1 0]
x[0 0 0]
x[0 0 1]
x[1 0 1]
x[0 1 1]
x[1 1 1]
0
1
0
1
0
1
0
1
n0
0
1
n2
0
n1
1
1
0
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Decimation-in-frequency Radix-2FFT
12,,0
])2/[][(]12[
])2/[][(]2[
1,,0,][][
2/
1)2/(
0
2/
1)2/(
0
1
0
-N/r
WWNnxnxrX
WNnxnxrX
NkWnxkX
rn
N
n
N
N
n
rn
N
N
n
kn
N
N
n
K
K
=
+=+
++=
==
=
=
=
Assume N is an even number.
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Decimation-in-frequency Radix-2FFT
12,,0
22where,
,][]12[
,][]2[
2/
1)2/(
0
2/
1)2/(
0
-N/r
])N/x[n(x[n]h[n]
])N/x[n(x[n]g[n]
WWnhrX
WngrX
rn
N
n
N
N
n
rnN
N
n
K=
+=++=
=+
=
=
=
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Decimation-in-frequency Radix-2FFT
Butterfly for Radix-2 DIF FFT
(M-1)th stage Mth stage
WNn
-1
In-place Computation
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Decimation-in-frequency Radix-2FFT First layer decimation
x[7]
x[0]
x[1]
x[6]
x[5]
x[4]
x[3]
x[2]
-1
-1
-1
-1
h[2]
h[3]
h[1]
h[0]
g[3]
g[2]
g[0]
g[1]
N/2-point
DFT
N/2-pointDFT
X[0]
X[2]
X[4]
X[6]
X[1]
X[3]
X[5]
X[7]
WN0
WN2
WN1
WN3
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Decimation-in-frequency Radix-2FFTX[0]
X7]
X3]
X[5]
X[1]
X[6]
X[2]
X[4]-1
-1
-1
-1
WN0
WN0
WN0
WN0
-1
-1
-1
-1
WN0
WN0
WN2
WN2
-1
x[0]
x7]
x[6]
x5]
x[4]
x[3]
x[2]
x[1]
-1
-1
-1
WN0
WN2
WN1
WN3
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Butterfly Comparison Butterfly (decimation-in-frequency)
(M-1)th stage Mth stage
WNn-1
Butterfly (decimation-in-time)
(M-1)th stage Mth stage
WNr -1
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Cooley-Tukey Algorithm
].kX[][
],x[][
:tarrangemen-repoint2D
,10
,10,
,10
,10,
211
212
22
11
211
22
11
212
NkkX
nnNnx
Nk
NknNkk
Nn
NnnnNn
+=
+=
+=
+=
21
NNN =
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Cooley-Tukey Algorithms
,][][ 222
2
2
21
1
1
11
1
1
0
1
0
212
nk
N
N
n
nk
N
N
n
nk
N WWWnnNxkX
=
=
+=
],[ 12 knG
Twiddle factor
],[~
12 knG
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N1 = 2, N2 = N/2 ->1st stage of thedecimation in frequency radix-2FFT.
N1 = N/2, N2 = 2 ->1st stage of thedecimation in time radix-2FFT.
In general, N = N1 N2 Nn.
IfN = r n ->Radix-r.
Observations
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Radix-3FFT (DIF)
rn
N
n
N
N
r
jj
rn
N
n
N
N
r
jj
rn
N
N
n
kn
N
N
n
WWeNnxeNnxnxrX
WWeNnxeNnxnxrX
WNnxNnxnxrX
WnxkX
3/
21)3/(
0
32
32
3/
1)3/(
0
32
32
3/
1)3/(
0
1
0
)]3/2[]3/[][(]23[
)]3/2[]3/[][(]13[
])3/2[]3/[][(]3[
][][
=
=
=
=
++++=+
++++=+
++++=
=
Assume N is a multiple of 3.
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Radix-3FFT (DIF)
Butterfly for Radix-3DIF FFT
32j
e
32j
e
(M-1)th stage Mth stage
32j
e
32j
e
WNn
WN2n
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Radix-4FFT (DIF)
rn
N
n
N
N
r
rnN
nN
N
r
rn
N
n
N
N
r
rn
N
N
n
WWNnxjNnxNnjxnxrX
WWNnxNnxNnxnxrX
WWNnjxNnxNnxjnxrX
WNnxNnxNnxnxrX
4/
31)4/(
0
4/2
1)4/(
0
4/
1)4/(
0
4/
1)4/(
0
])4/3[)(]4/2[)1(]4/[][(]34[
])4/3[)1(]4/2[]4/[)1(][(]24[
])4/[]4/2[)1(]4/[)(][(]14[
])4/3[]4/2[]4/[][(]4[
=
=
=
=
++++++=+
++++++=+
++++++=+
++++++=
Assume N is a multiple of 4.
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Radix-4FFT (DIF)
Butterfly for Radix-4DIF FFT
(M-1)th stage Mth stage
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Split Radix FFT
Mix Radix-2and Radix-4architecture.
Compute even transform coefficientsbased on Radix-2strategy and oddcoefficients based on Radix-4strategy.
Can perform FFT for N= 2.
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Simplify Butterfly Representations
Radix-2
Radix-4
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Split-Radix FFT
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Computational Complexity
Method# of Complex
Multiplications
# of Complex
Additions
DFT N2 N(N-1)
Radix-2 (N/2) log2N N log 2N
Radix-4 (3N/8) log2N (3N/2) log2N
The above numbers do not tell the whole story!
Architecture is the key issue to trade of among
performance, cost, hardware complexity, etc.
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Outline Applications of FFT in Communications
Fundamental FFT Algorithms
FFT Circuit Design Architectures
Conclusions
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FFT Architecture Design Considerations
Trade-off among accuracy, speed, hardwarecomplexity, and power consumptionbest fitarchitecture should be application dependent.
Main architecture differences in:
Degrees of parallelismnumber and complexity of
processing elements,
Control schemes - hardware utilization and data flowcontrol.
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Degree of Parallelism One simple processing unit or multiple simple processing units
x[0]
x[7]
x[3]
x[5]
x[1]
x[6]
x[2]
x[4]
X[0]
X[7]
X[6]
X[5]
X[4]
X[3]
X[2]
X[1]-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
WN0
WN0
WN0
WN0
WN0
WN0
WN0
WN2
WN2
WN2
WN1
WN3
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Degree of Parallelism
Simple processing units versus complicate processing units
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Memory-based FFT architecture
Single butterfly or processing element. Required memory size = N.
A control unit ensures the right dataflows to compute FFT.
Firmware Like.
Low complexity.
Low speed.
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Memory-based FFT Block Diagram
Butterflyor
Processing Element
Input Buffer
CoefficientsROM or
Generator
RAM
Control Unit
DataIn
DataOut
Control
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Pipeline Architectures
FFT Signal Flow Graph
Multiple path delay commutator
Single path delay commutator
Single path delay feedback
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Radix-2Signal Flow Graph (DIT)
BF2
Buffer
ROM
BF2
Buffer
ROM ROM
BF2
x[0]
x[4] -1WN0
x[6]
x[2]
-1WN0
x[5]x[1]
-1WN0
x[7]
x[3]
-1WN0
-1
-1
WN0
WN2
-1
-1WN0
WN2
X[0]
X[7]
X[6]
X[5]X[4]
X[3]
X[2]X[1]
-1
-1
-1
-1
WN0
WN2
WN1
WN3
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Radix-2Signal Flow Graph (DIF)
ROM
BF2
Buffer
ROM
BF2
Buffer
ROM
BF2
X[0]
X7]
X3]
X[5]
X[1]
X[6]
X[2]
X[4]-1
-1
-1
-1
WN0
WN0
WN0
WN0
-1
-1
-1
-1
WN0
WN0
WN2
WN2
-1
x[0]
x7]
x[6]
x5]
x[4]
x[3]
x[2]x[1]
-1
-1
-1
WN
0
WN2
WN1
WN3
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Multi-Path Delay Commutator
Commutator(switch)
Delay
Delay
Butterfly
Delay
Delay
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Radix-2Multi-Path Delay CommutatorX[0]
X7]
X3]X[5]X[1]X[6]X[2]
X[4]-1
-1
-1
-1
WN0
WN0
WN0
WN0-1
-1-1
-1
WN0
WN0
WN2
WN2
-1
x[0]
x7]
x[6]x5]x[4]x[3]x[2]
x[1]
-1-1
-1
WN0
WN2
WN1
WN3
7 6 5 4 3 2 1 03 2 1 0
4 5 6 73 2 1 04 5 6 7
3 2 1 04 5 6 7
3 2 1 04 5 6 7
5 4 1 07 6 3 2
5 4 1 07 6 3 2
5 4 1 07 6 3 2
5 4 1 07 6 3 2
6 4 2 07 5 3 1
6 4 2 07 5 3 1
6 4 2 07 5 3 1
switch
switch
switch
delay butterfly
butterfly
butterfly
delay
delay
delay
delay
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Radix-2Multi-Path Delay Commutator
C2
4
BF2
2
C2
2
BF2
1
C2
1
BF2C2
8
BF2
4
N=16
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Radix-4Multi-Path Delay Commutator
C4 BF4
3
2
1
C4
12
BF4
3
2
18
4
C4
48
BF4
12
8
432
16
C4
192
BF4
48
32
16128
64
N=256
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Single Path Delay Commutator
Delay
Commutator Butterfly
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Radix-2Single Path Delay Commutator
DC2 BF2 DC2 BF2 DC2 BF2 DC2 BF2
N=16
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Radix-4Single Path Delay Commutator
DC4 BF4 DC4 BF4 DC4 BF4 DC4 BF4
N=256
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Single Path Delay Feedback
Butterfly
Delay
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Radix-2Single Path Delay Feedback
BF2
4
BF2
2
BF2
1
BF2
8
N=16
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Radix-4 Single Path Delay Feedback
BF4
4x3
BF4
1x3
BF4
16x3
BF4
64x3
N=256
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R22SDF
BF2II
4
BF2I
2
BF2I
8
BF2II
1
N=256
BF2II
64
BF2I
32
BF2I
128
BF2II
16
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Hardware ComparisonMultiplier # Adder # Memory Size ControlArchitecture
R2MDCR2SDFR4MDC
R4SDFR4SDCR22SDF
2(log4N-1)2(log4N-1)3(log4N-1)
log4N-1log4N-1log4N-1
4 log4N4 log4N8 log4N
8 log4N3 log4N4 log4N
3N/2-2N-1
5N/2-4
N-12N-2N-1
simplesimplesimple
mediumcomplexsimple
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Conclusions Effect FFT computation is essential to many
communication applications utilizing OFDM or DMTtechnique.
A pipelined FFT architecture is applied where a highreal-time performance is required. A memory-basedFFT architecture can be adopted when cost is more
concerned than speed.
A best fit FFT architecture depends on applicationspecific requirements to tradeoff among accuracy,
speed, chip size, power consumption, etc.