Download - Architecture and instruction set
![Page 1: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/1.jpg)
Architecture and instruction setArchitecture and instruction set
![Page 2: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/2.jpg)
![Page 3: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/3.jpg)
Microcontroller Core Features: Operating speed: DC - 20 MHz clock input DC - 200 ns instruction
cycle Up to 8K x 14 words of FLASH Program Memory, Up to 368 x 8 bytes of Data Memory (RAM) Up to 256 x 8 bytes of EEPROM Data Memory
Pinout compatible to the PIC16C73B/74B/76/77 Interrupt capability (up to 14 sources) Eight level deep hardware stack Direct, indirect and relative addressing modes Power-on Reset (POR) Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) Watchdog Timer (WDT) with its own on-chip RC oscillator for
reliable operation Programmable code protection Power saving SLEEP mode Selectable oscillator options
![Page 4: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/4.jpg)
Peripheral Features Timer0: 8-bit timer/counter with 8-bit prescaler Timer1: 16-bit timer/counter with prescaler, can be incremented
during SLEEP via external crystal/clock Timer2: 8-bit timer/counter with 8-bit period register, prescaler and
postscaler Two Capture, Compare, PWM modules
Capture is 16-bit, max. resolution is 12.5 ns Compare is 16-bit, max. resolution is 200 ns PWM max. resolution is 10-bit
10-bit multi-channel Analog-to-Digital converter Synchronous Serial Port (SSP) with SPI (Master mode) and I2C
(Master/Slave) Universal Synchronous Asynchronous Receiver Transmitter
(USART/SCI) with 9-bit address detection Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS
controls (40/44-pin only) Brown-out detection circuitry for Brown-out Reset (BOR)
![Page 5: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/5.jpg)
![Page 6: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/6.jpg)
Program Memory Program Memory OrganizationOrganization
The PIC16F87X devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space.
The PIC16F877/876 devices have 8K x 14 words of FLASH program memory.
Accessing a location above the physically implemented address will cause a wraparound.
The RESET vector is at 0000h and the interrupt vector is at 0004h.
![Page 7: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/7.jpg)
Data Memory OrganizationData Memory Organization The data memory is partitioned into multiple banks which contain the The data memory is partitioned into multiple banks which contain the
General Purpose Registers and the Special Function Registers. Bits General Purpose Registers and the Special Function Registers. Bits RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank select bits.RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank select bits.
Each bank extends up to 7Fh (128 bytes). Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function The lower locations of each bank are reserved for the Special Function
Registers. Registers. Above the Special Function Registers are General Purpose Registers, Above the Special Function Registers are General Purpose Registers,
implemented as static RAM. implemented as static RAM. All implemented banks contain Special Function Registers. All implemented banks contain Special Function Registers. Some frequently used Special Function Registers from one bank may Some frequently used Special Function Registers from one bank may
be mirrored in another bank for code reduction and quicker access.be mirrored in another bank for code reduction and quicker access.
![Page 8: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/8.jpg)
![Page 9: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/9.jpg)
What are the two/four banksfor?
Memory space is organized in 128Byte banks. PIC 16F684 has two banks - Bank 0 and Bank 1. Bank 1 is used to control the actual operation of
the PIC for example to tell the PIC which bits of Port A are input and which are output.
Bank 0 is used to manipulate the data. An example is as follows:
Let us say we want to make one bit on Port A high. First we need to go to Bank 1 to set the particular bit,
or pin, on Port A as an output. We then come back to Bank 0 and send a logic 1 (bit
1) to that pin.
![Page 10: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/10.jpg)
Special Function Registers W, the working register. To move values from
one register to another register, the value must pass through the W register.
FSR (04h,84h,104h,184h), File Select Register Indirect data memory addressing pointer
INDF (00h,80h,100h,180h) accessing INDF accesses the location pointed by IRP+FSR
PC, the Program Counter, PCL (02h, 82h, 102h, 182h) and PCLATH (0Ah, 8Ah, 10Ah, 18Ah)
![Page 11: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/11.jpg)
![Page 12: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/12.jpg)
Direct/Indirect Addressing
![Page 13: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/13.jpg)
Direct Addressing Use only 7 bits of instruction to identify a register file
address. The other two bits of register address come from RP0 and
RP1 bits in the STATUS register Example: Bank switching (Note: case of 4 banks)
CLRF STATUS ; Clear STATUS register (Bank0) : ; BSF STATUS, RP0 ; Bank1 : ; BCF STATUS, RP0 ; Bank0 : ; MOVLW 0x60 ; Set RP0 and RP1 in STATUS register, other XORWF STATUS, F ; bits unchanged (Bank3) : ; BCF STATUS, RP0 ; Bank2 : ; BCF STATUS, RP1 ; Bank0
![Page 14: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/14.jpg)
Indirect Addressing The INDF register is not a physical register. Addressing the
INDF register will cause indirect addressing. Any instruction using the INDF register actually access the
register pointed to by the File Select Register (FSR). The effective 9-bit address is obtained by concatenating the
8-bit FSR register and the IRP bit in STATUS register. Example
MOVLW 0x20 ;initialize pointer MOVWF FSR ;to RAM NEXT: CLRF INDF ;clear INDF register INCF FSR,F ;inc pointer BTFSS FSR,4 ;all done? (to 0x2F) GOTO NEXT ;no clear next CONTINUE:
;yes continue
![Page 15: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/15.jpg)
I/O Ports General I/O pins are the simplest of peripherals
used to monitor and control other devices. For most ports, the I/O pin’s direction (input or
output) is controlled by the data direction register TRISx (x=A,B,C,D,E).
A ‘1’ in the TRIS bit corresponds to that pin being an input, while a ‘0’ corresponds to that pin being an output
The PORTx register is the latch for the data to be output. Reading PORTx register read the status of the pins, whereas writing to it will write to the port latch.
![Page 16: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/16.jpg)
Example: Initializing PORTD bcf STATUS, RP0 ; bank0 bcf STATUS, RP1 clrf PORTD ; initializing PORTD by clearing output
data latches bsf STATUS, RP0 ; select bank1 movlw 0xCF ; value used to initialize data direction
(1100 1111) movwf TRISD ;
PORTD<7:6>=inputs, ;PORTD<5:4>=outputs, PORTD<3:0>=inputs
![Page 17: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/17.jpg)
Instruction FormatsInstruction Formats
![Page 18: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/18.jpg)
INSTRUCTION 1INSTRUCTION 1
![Page 19: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/19.jpg)
INSTRUCTION 2INSTRUCTION 2
![Page 20: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/20.jpg)
INSTRUCTION 3INSTRUCTION 3
![Page 21: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/21.jpg)
INSTRUCTION 4INSTRUCTION 4
![Page 22: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/22.jpg)
INSTRUCTION 5INSTRUCTION 5
![Page 23: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/23.jpg)
INSTRUCTION 6INSTRUCTION 6
![Page 24: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/24.jpg)
INSTRUCTION 7INSTRUCTION 7
![Page 25: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/25.jpg)
INSTRUCTION 8INSTRUCTION 8
![Page 26: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/26.jpg)
INSTRUCTION 9INSTRUCTION 9
![Page 27: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/27.jpg)
INSTRUCTION 10INSTRUCTION 10
![Page 28: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/28.jpg)
INSTRUCTION 11INSTRUCTION 11
![Page 29: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/29.jpg)
INSTRUCTION 12INSTRUCTION 12
![Page 30: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/30.jpg)
INSTRUCTION 13INSTRUCTION 13
![Page 31: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/31.jpg)
INSTRUCTION 14INSTRUCTION 14
![Page 32: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/32.jpg)
INSTRUCTION 15INSTRUCTION 15
![Page 33: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/33.jpg)
INSTRUCTION 16INSTRUCTION 16
![Page 34: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/34.jpg)
INSTRUCTION 17INSTRUCTION 17
![Page 35: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/35.jpg)
INSTRUCTION 18INSTRUCTION 18
![Page 36: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/36.jpg)
INSTRUCTION 19INSTRUCTION 19
![Page 37: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/37.jpg)
INSTRUCTION 20INSTRUCTION 20
![Page 38: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/38.jpg)
INSTRUCTION 21INSTRUCTION 21
![Page 39: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/39.jpg)
INSTRUCTION 22INSTRUCTION 22
![Page 40: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/40.jpg)
INSTRUCTION 23INSTRUCTION 23
![Page 41: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/41.jpg)
INSTRUCTION 24INSTRUCTION 24
![Page 42: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/42.jpg)
INSTRUCTION 25INSTRUCTION 25
![Page 43: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/43.jpg)
INSTRUCTION 26INSTRUCTION 26
![Page 44: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/44.jpg)
INSTRUCTION 27INSTRUCTION 27
![Page 45: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/45.jpg)
INSTRUCTION 28INSTRUCTION 28
![Page 46: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/46.jpg)
INSTRUCTION 29INSTRUCTION 29
![Page 47: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/47.jpg)
INSTRUCTION 30INSTRUCTION 30
![Page 48: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/48.jpg)
INSTRUCTION 31INSTRUCTION 31
![Page 49: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/49.jpg)
INSTRUCTION 32INSTRUCTION 32
![Page 50: Architecture and instruction set](https://reader035.vdocuments.site/reader035/viewer/2022081502/56816092550346895dcfb7c1/html5/thumbnails/50.jpg)
INSTRUCTIONS 33-35INSTRUCTIONS 33-35
SLEEPSLEEP CLRWDTCLRWDT NOPNOP