Download - An Introduction to VHDL Using Altera’s Quartus II IDE Dr. William M. Jones Coastal Carolina University Numbers and Bytes Meeting 20 OCT 2008

An Introduction to VHDL Using Altera’s Quartus II IDE

Dr. William M. Jones

Coastal Carolina University

Numbers and Bytes Meeting

20 OCT 2008

© 2007, William M. Jones, et. al.

VHDL Quick Start 2

Pre-Intro

• VHDL– Very Hard Difficult Language

– Jk

– VHSIC Hardware Description Language

• VHSIC– Very High Speed Integrated Circuits

• Intended uses– Circuit simulation

– Circuit synthesis (realization)

• FPGA’s, (C)PLDs, ASICs


VHDL Quick Start 3

Some Background

• VHDL vice Verilog

• Altera and Xilinx

• VHDL is a language– But, is very different from traditional languages– In general, all statements are CONCURRENT (parallel)– Traditional is SEQUENTIAL – Typically referred to as code as opposed to a program– VHDL is not case sensitive

• PROCESS, FUNCTION, PROCEDURE – Only places were sequential behavior is seen


VHDL Quick Start 4

Basic VHDL Code Parts

• LIBRARY– Like #include <stdio.h> in C or import in JAVA

– Commonly used pieces of code

– 2 are generally included by default

• ENTITY– List of specifications for input and output PORTS

– Kinda like function prototypes in C (provides interface)

• ARCHITECTURE– Provides a description of how the circuit should behave


VHDL Quick Start 5

LIBRARY

LIBRARY library_name;USE library_name.package_name.package_parts;

LIBRARY ieee;USE ieee.std_logic_1164.all;

LIBRARY std; -- included by defaultUSE std.standard.all;

LIBRARY work; -- included by defaultUSE work.all;


VHDL Quick Start 6

ENTITY (Modeling Interfaces) (VHDL-93)

• Entity declaration– describes the input/output ports of a module

entity reg4 isport ( d0, d1, d2, d3, en, clk : in bit;

q0, q1, q2, q3 : out bit );end entity reg4;

entity name port names port mode (direction)

port typereserved words

punctuation


VHDL Quick Start 7

PORTS – Signal Modes

• IN– Unidirectional

• OUT– Unidirectional

• INOUT– Bidirectional

• BUFFER– Used when output signal needs to be used internally


VHDL Quick Start 8

Putting Them Together


VHDL Quick Start 9

A Simple Multiplexer


VHDL Quick Start 10

MUX Implementation with Pure Logic


VHDL Quick Start 11

Synthesized Hardware (Pure Logic)

But what do you do now?


VHDL Quick Start 12

Altera DE 2 Board


VHDL Quick Start 13


VHDL Quick Start 14


VHDL Quick Start 15


VHDL Quick Start 16


VHDL Quick Start 17


VHDL Quick Start 18


VHDL Quick Start 19

MUX Implementation with WHEN/ELSE


VHDL Quick Start 20

Synthesized Hardware (WHEN/ELSE)


VHDL Quick Start 21

A Simple ALU


VHDL Quick Start 22

ALU Specifications


VHDL Quick Start 23

ALU Part 1


VHDL Quick Start 24

ALU Part 2


VHDL Quick Start 25

ALU Part 3


VHDL Quick Start 26


VHDL Quick Start 27


VHDL Quick Start 28


VHDL Quick Start 29

Kickin’ It Up A Notch

Combinational v. Sequential LOGIC


VHDL Quick Start 30

Concurrent v. Sequential Code

• Code placed inside a PROCESS, FUNCTION, or PROCEDURE is executed sequentially

• Otherwise the does is executed concurrently– In parallel

– Order of statements would not matter

– Often called ‘dataflow’ code

• With only a few exceptions purely concurrent code will only produce ‘combinational’ circuits

• Sequential code must be employed to produce sequential logic circuits (this code can produce both in fact)


VHDL Quick Start 31

A Simple Counter (Sequential Code Intro)


VHDL Quick Start 32

Simple Counter Code


VHDL Quick Start 33

Synthesized Hardware (Counter)


VHDL Quick Start 34

Counter (Zoom 1)


VHDL Quick Start 35

Counter (Zoom 2)


VHDL Quick Start 36

A Counter With A Display


VHDL Quick Start 37

Counter With Display VHDL (Part 1)


VHDL Quick Start 38

Counter With Display (Part 2)


VHDL Quick Start 39



VHDL Quick Start 40



VHDL Quick Start 41

Synthesized HW (Partial)


VHDL Quick Start 42

Creating A Symbol File (Schematic)


VHDL Quick Start 43

End of N&B Presentation

Have a nice day!

Download - An Introduction to VHDL Using Altera’s Quartus II IDE Dr. William M. Jones Coastal Carolina University Numbers and Bytes Meeting 20 OCT 2008

Top Related