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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Topics
Modeling with hardware description
languages (HDLs).
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Hardware description languages
Textual languages for describing hardware:
structure;
function.
Most people today use textual languages
rather than schematics for most digital
design.Schematics make poor use of screen space.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Major HDLs
Two major HDLs designed for simulation:
VHDL;
Verilog.
Similar capabilities but somewhat different
language philosophies.
EDIF is a standard netlist format.
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Simulation vs. programming
Simulation tags computations with times.
Must know when signals change to properly
simulate hardware.
Simulation is parallel.
Many statements can execute at the same
(simulation) time.Just like hardware.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Types of simulation
Compiled code simulation.
Generate program that evaluates a hardware
block.
Operational details within the hardware block
are lost.
Event-driven simulation.Propagate events through simulation.
Dont simulate a block until its inputs change.
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Event-driven simulation
An event is a change
in a nets value.
An event has twocomponents:
value;
time.
timet=35 ns
net1=0 @ 35 ns
net
event
ne
t1
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Propagate events
only when nets
change value. If an input change
doesnt cause an
output change, no
event is propagated.
0
1
1
0
no
event
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Timewheel
The timewheel is a data structure in the
simulator that efficiently determines the
order of events processed.
Events are placed on the timewheel in time
order.
Events are taken out of the head of thetimewheel to process them in order.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Timewheel operation
a
b
c1
0
1
a=1 @ 0 ns
netlist timewheel
b=1 @ 1 ns
1
c=0 @ 2 ns
0 time
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Order of evaluation
Order of evaluation is important.
Causality must be obeyed.
Evaluating events in the wrong order can
cause inaccurate results.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Order of evaluation example
a
b
c0
0
0
netlist timewheel
b=1 @ 1 ns
1 d=1 @ 2 ns
1
d
e1
e=0 @ 4 ns
0
1
time
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Modeling
Structural modeling describes the
connections between components.
Netlists are structural models.
Behavioral models describes the functional
relationship between inputs and outputs.
Similar to programming but values are events.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
HDLs language constructs
Must be able to define component types.
A model may be behavioral or structural.
May be able to define abstract data types.
A wire may carry an enumerated value.
Multi-valued simulation may be defined using
abstract data types.
May be able to define modules to control
the scope of names.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Testbenches
A testbench is a model used to exercise a
simulation.
Provides stimulus.Checks outputs.
Testbenches help automate design
verification.Rerun edited module against testbench.
Run models at behavioral, RTL levels against
the same testbench.
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Synthesis subsets
VHDL and Verilog were designed for
simulation.
A synthesis subset is:
synthesizable;
produces consistent simulation results.
Different tools may use different synthesis
subsets.
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Register-transfer synthesis
Most common type of synthesis.
Synthesizes gates from abstract RT model.
Registers are explicit.
Some tools will infer storage elements---be
careful.
Optimized for performance, area, power.