TM
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
Charlie WuSenior System & Application Engineer
Advanced Digital Power Solutions Digital Signal Controller-Based Digital Power Supply
November 2007
PZ307
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Abstract
Learn about the emerging technology of digital power conversion as it applies to the markets of Switched-mode Power Supplies (SMPS),)and Renewable Energy Converter. This class provides a technical overview of applications as well as hardware and software implementation based on Freescale 56800E Digital Signal Controller.
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Emerging Technology in Digital Power Converters
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Where Is Digital Power Conversion Applied ?
►“Digital power Conversion” is a power system that is controlled by digital circuits, in much the same way as as would be with analog circuits, to monitor, supervise, communicate and control looping. A fully digitally controlled power system includes bothdigital control and digital power management.► Digital Control
• The control feedback or feed-forward loop, which is controlled by the digital circuit or programmable controller, regulates the output of the power system by driving the power switch duty cycle using pulse width modulation techniques.
• The control circuits combine A/D conversion, Pulse Width Modulation, and Communication interfaces, operating entirely or mostly in digital mode.
► Digital Power Management• A Digital circuit or programmable controller provides the functions
of configuration, tracking, monitoring , protection, supply sequencing, and communication with the environment.
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Comparison of Analog and Digital Power Control System
R
C
REF
SCALE
AnalogCompensator
Network
AnalogCompensator
Network
Current
Voltage
PowerSwitch
LCFilter
PWMGenerator
CLKC
VoltageRamp
Network
DC InputDC Output
Analog Control System With Digital Management
Fan
A to D Converter
VoltageCurrent
Temperature
Serial Interface
GPIO
ShutDown
Microcontroller
To Other Controllers
DC Input
Voltage
SCALE
PowerSwitch
LCFilter
DC Output
SCALE
DigitalPWM
Generator
A to D ConverterCurrent
Serial Interface
DSP Controller
Tempe-rature
Fan
GPIO
Full Digital Control System
To Other Controllers
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Compare Digital Control To Analog Control
Analog Control Digital Control
Control Circuit
ComplexComplex��BulkyBulky
Simple, Programmable,Simple, Programmable,IntegratedIntegrated
Flexibility BadBad GoodGood
Sample Mode
ContinuousContinuous Digitalization ErrorDigitalization Error
Design Continuity
BadBad GoodGood
Processing Course
ContinuousContinuous Control DelayControl Delay
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Analog Control vs. Digital Control - Transient Response Comparison
Vout
Iout
Constant Voltage
Constant Power
Constant Current
• No OV and no OC during transient because of the smooth loop transition
• Output profile is programmable
Advanced Digital control
Power Fold Down
Iout
Vout Constant Voltage
Constant PowerOver current during load step-up
Over voltage during load step-down
Traditional Analog control Constant Current
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Digital vs. Analog Control Loop
Vref VoutLinear compensation Power stage
+-
44
33
22
110
44
33
2210
SBSBSBSBBSASASASAA
K++++++++
211)1(SS
Sβα
γκ+++
A typical control loop implemented by an analog circuit
A digital control loop implemented by Digtal Signal Controller (DSC)
Vref VoutAdaptive compensation Power stage
+-
Nonlinear compensation
Operation condition
44
33
2210
44
33
2210
SSSSSSSS
βββββααααακ++++++++
Software Implementation
211)1(SS
Sβα
γκ+++
Benefit of digital control: 1)Optimize feedback loop to meet application requirements2) Runtime changes to compensation parameters according to operating conditions
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Real-time Digital System Model
A/Dconvert
Analog signal
Analog signal
D/Aconvert
Signal processing
quickHigh
precision
quickreal time
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Quantization Effects - PWM resolution
PWM resolution = PWM clock ÷ PWM Switching FrequencyAssume 1:
PWM clock = 32Mhz; PWM Switching Frequency = 250KHzPWM Resolution = 32,000,000 ÷ 250,000
= 128 ( 2 7 or 7 bit)Assume 2:
PWM clock = 96Mhz; PWM Switching Frequency = 250KHzPWM Resolution = 96,000,000 ÷ 250,000
= 384 (1.5x2 8 or 8.5 bit)
If DC bus voltage is 300VDC, each bit represents:7 bit PWM resolution: 48VDC ÷ 128 = 0.375V ( 0.78% accuracy)8.5 bit PWM resolution: 48VDC ÷ 348 = 0.138V ( 0.29% accuracy)
The second Assumption yields higher PWM resolution, less Voltage variation per bit change. So the voltage ripple on output will be smaller.
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Quantization Effects- ADC Resolution and Speed
A/Dconvert
Analog signal Input
Analog signal Output
D/Aconvert
Signal processing
Slow SpeedLess ResolutionAnd Speed
Low ADCResolution
High SpeedHigh Resolution
Signal Reconstruction
High ADCResolutionAnd Speed
Higher SignalDistortion
Lower SignalDistortion
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Increase PWM resolution: Digital Dithering Technique
49.5
With Dithering:PWM dithersBetween 49 & 50 50
Dither is a form of noise, or erroneous signal or data which is deliberately added to sample data for the purpose of minimizing quantization error.
The quantization error is a repeatable error as the value repeat. Digital dithering is a system wherein the error does not repeat as the value repeat.In digital power system, digital dithering technique will reduce the PWM quantization error.If a digital PWM module can not output a value that matches the Control Loop’s calculated value, the control loop will dither between the two closest values to obtain the desired result.
Calculated PWM Duty Value = 49.5
Without Dithering
Modulo = 100
49 49 50 50
49 49 50
Voltage At Point A
A B
C
+
Current At Point B
ModuloValueDutyPWMCycleDutyPWM =
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Transfer Function Of Control Loop
V*o is the reference;V0is the output; Kvs is the feedback gain.Control loop includes a PID controller and a power stage model.PID controller is a dynamic error regulator
PID transfer function
Power Stage transfer function
S S)(GVEA )(Gvh
vsK
ov*
oV
*fV
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Control Law Processor - PID Controller(Proportional-Integral-Derivative)
• Continuous ( Analog) Expression
-
+
Feedback Xf(t)
M(t) = Kp*e(t) + Ki*∫e(t)dt + Kd * ---- e(t)ddt
e(t) = Xi(t) – Xf(t) ----- (1)
----- (2)
• Difference ( digital ) Expressionn
m(n) = Kp × e(n) + Ki × ∑ e(i) × Δt + Kd × ----------------Δt
e(n) – e(n-1)i=0
Command Xi(t)
Output M(t)
m(n)= m(n-1) + Kp × [e(n)-e(n-1)] + Ki × e(n) × Δt + Kd × [---------------- - ------------------- ]e(n) – e(n-1)Δt Δt
e(n-1) – e(n-2)
- (3)
- (4)
Where -- e(t): Error signal; Kp: Proportional Gain; Ki: Integral Gain; Derivative Gain
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Design Of Control Feedback Loop In Digital DomainPID Regulating Loop
11
1
)(
1)]([&)()]1([
tionTransformaZToConversion
−−
−∑=
==−
−
z
zEn
inezzEznez
tKKtKivKKK didippv Δ÷=Δ×== ;;:Where *
)5()1(1)(
)()(
(4)EquationFrom
1*1
** −−+
−+== −
−zK
z
KK
zEzMzVEAG idpv
iv
Digital PID Controller*pvK
)1( 1* −− zKiv
)1( 1* −− zKid
++
+
)(zEe(n)
)(zMm(n)
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Design Of Control Feedback Loop In Digital Domain Model Of Power Stage Transfer Function
Power stage Z-transformation function
)(SGvSe SST−−1
)(SGvh
( ) ov
vo o
v KG Sv SCV
= =%
%
)1(])([)1())(()( 1
−⋅
=−== −
zCVTK
SSGZzSGZzG
o
Svvhvh
Vo and Vvo are values of output and loop output~ ~
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PID Parameter Design For Feedback Loop Control
vsvhVEAopenv KzGzGzG )()()( =−ssTez =
vssT
vhsT
VEAsT
openv KeGeGeG sss )()()( =−
Measurement criteria for a stable closed loop system- Phase margin should be greater than 45°at open loop cross frequency
- Gain margin should be greater than one at the frequency where the phase shift is -180°
1)(45180)( =+−>∠ −− scsc Tjopenv
Tjopenv eGwhereateG ϖϖ oo
)(ZGVEA )(ZGvh
vsK
ov*oV
ΔT
o180)(1)(1 −=∠> −− scsc Tjopenv
Tjopenv eGwhereateG ϖϖ
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Benefits of Digital PowerFree from the effects of component tolerance, parametric drift, aging, etcConfigurable feedback loop structure for specific application requirementsAdaptive control to meet changing operating conditions Flexible Pulse Width Waveform-generation module Programmable relationships among PWM outputsUpgradeable with new features without hardware changes Retainable operational data for diagnostic and record keepingDiverse communications capabilities Reduced component count - and costHigher power density due to over all integrationShorter R&D cycle, fewer turns of board prototyping Portable Projects for faster reuseDefendable firmware - protects IP and differentiating technology
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Typical DSP-based AC/DC Converter
Primary DSP
Secondary DSP
SPI or SCI
RS485 / I2C (communication)
PFCIsolatedDC/DC
PWMA/D PWMA/D
LEDs
reset reset
Thermal ThermalFan Fan
AC
AC sensing
OV/OC detection
OV/OC detection
Current sharing
Discrete status report
System info / control
Vout
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Production Overview
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Controller Continuum
LowHCS08 LVLP 8-bit familyHC08 8-bit familyRS08 8-bit family
Mid56F800 hybrid family56F801x hybrid familyHCS12 16-bit family
Upper Mid
ColdFire® MCF5xxx family56F83xx/81xx hybrid family568xx hybrid family
HighMobileGT™ MPC5200ColdFire® MCF5xxx familyMPC5xx family based on Power Architecture technoloygi.MX family based on ARM® technology
Wireless
SMAC802.15.4Zigbee
Software, Tools, &
Services
Flash Technology
Analog
Motion controlPower mgmt
QUICCsupplyI/O expansion
Sensors
AccelerometersPressure
Proximity
760 MIPS 2 M
IPS
In Addition, Freescale also offers……
Host & Communications Processors based upon the Power Architecture™Technology
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What is Digital Signal Controller
• Specialized microprocessor whose architecture contains a core engine capable of competitively performing both microcontroller and digital signal processor functionalities
• Core processing capability applicable to many types of system solutions• Common basic features:
> MAC, single instruction cycle allowing several memory accesses, address generation units, algorithms for efficient looping
• Specialized cost effective, high performance on-board interfaces utilized in implementing embedded control applications :
> PWM; multifunction timer; high speed ADCs; DACs; Comparators; SCIs (UART); SPIs; CANs and I2Cs, etc.
• Embedded nonvolatile memory:> Flash memory, ROM or EEPROM
• Easy to use development tools
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TraditionalMicrocontroller
• Designed for Controller Code• Compact Code Size• Easy to Program• Inefficient Signal Processing Traditional DSP
Engine
• Designed for DSP Processing • Designed for Matrix Operations• Complex Programming• Less Suitable for Control
56800/E Family Combining Signal Processing and Controller Functionality
• Instructions Optimized for Controller Code, DSP, Matrix Operations • Compact Assembly and “C” Compiled Code Size• Easy to Program• Additional MIPS Headroom and extended addressing space
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DSP56800E Core Features
CPU MIPS # InterruptPriorities Registers Data Types
ProgramMemory
Adr Space
DataMemory
Adr SpaceTechnology
DSP56800E120 from RAM
60 from Flash5 7 Data
8 Address8-bit, 16-bit
32-bit 4 MB 32 MBFully
Synthesizable and Scanable
True SoftwareStack and Pointer
General Purpose Register Files and Orthogonal Instructions to Data and Address Register Files
20 Addressing Modes and Atomic Read-Modify-Write Instructions
Full Set of Bit and Bitfield Manipulation Instructions and 16- and 32-bit Shifting
16-bit Program Word
Multiplier - Accumulator (MAC)Single And Dual Parallel Move
Instructions
No Overhead Hardware LoopingNested Looping Capability
Nested Interrupt with HW priority Fast Interrupt Support
Modulo arithmetic (For Circular Buffers) Integer and Fractional Arithmetic Support
56800/E DSP Functionality56800/E MCU Functionality
Superfast Interrupt
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DATA ARITHMETIC LOGIC UNIT
A2 A1 A0B2 B1 B0C2 C1 C0D2 D1 D0
Y1Y0X0
DATA REGISTERS
Y
ABCD
35 32 31 16 15 0
DSP56800E General Purpose Registers
ADDRESS GENERATION UNITR0R1R2R3R4R5
N
SPPOINTER REGISTERS
23 0
PROGRAM CONTROL UNITPC
OMRSR
PROGRAM COUNTER
OPERATING MODE and STATUS
15 0
20 0
=> 7 DataRegisters
=> 8 AddressRegisters
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Registers with Dedicated Functionality
SECONDARY OFFSET REGISTER
N315 0
PROGRAM CONTROL UNITLALA2
LOOP ADDRESS
HARDWARE STACK
LOOP COUNTER
15 0
23 0
23 0
HWS0HWS1
LCLC2
=> HW LoopingNested 2 Deep
FISRFAST INTRPT STATUS REG
FAST INTRPT RETURN ADDR12 0
20 0
FIRA=> Fast Interrupt
M01
N
R0R1
ADDRESS GENERATION UNIT
POINTER REGISTERS
MODIFIER REGISTERS
M01
23 0
15 0
=> Shadows
23 0
=> Modulo Addressing
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==> R0, R1, N, and M01registers are shadowed
A2 A1 A0B2 B1 B0C2 C1 C0D2 D1 D0
Y1Y0X0
DATA REGISTERSDATA ARITHMETIC LOGIC UNIT
Y
ABCD
35 32 31 16 15 0
DSP56800E Programming Model
M01
N
R0R1
R0R1R2R3R4R5
N
SP
ADDRESS GENERATION UNIT
POINTER REGISTERS
SECONDARY OFFSET REGISTER
MODIFIER REGISTERS
M01
N3
23 0
15 0
15 0
PC
PROGRAM CONTROL UNIT
OMRSR
LALA2
FISRFAST INTERRUPT STATUS REGISTER
PROGRAM COUNTER
OPERATING MODE and STATUS
LOOP ADDRESS
HARDWARE STACK
LOOP COUNTER
FAST INTERRUPT RETURN ADDRESS12 0
15 0
15 0
23 0
23 0
20 0
20 0
HWS0HWS1
LCLC2
FIRA
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Mapping the Architecture to DSP Algorithms
DATAALU
ABCD
Y0Y1X0
MAC and ALU
Multi-bitShifter
R 0R 1R 2R 3R 4R 5N
S P
R 0R 1R 2R 3R 4R 5N
S P
AGU ALU1 ALU2ALU1 ALU2
M 01M 01
BITMANIPULATION
UNIT
EOnCE / JTAG TAP
XAB1XAB1XAB2XAB2PABPAB
PDBPDBCDBWCDBWCDBRCDBRXDB2XDB2
ProgramMemory
ProgramMemory
DataMemory
DataMemory
IP-BusInterfaceIP-Bus
Interface
ExternalBus
Interface
ExternalBus
Interface
N 3N 3
Operations Performed:• Multiply-Accumulate• 3 Memory Accesses• 2 Address Additions
Common Operation in DSP
MAC X0, Y0, A X:( R4)+, Y1 X:( R3)+, C
Arithmetic Op 1st Read 2nd Read
PROGRAMCONTROLLER
INSTRUCTIONDECODER
INSTRUCTIONDECODER
LOOPINGUNIT
LOOPINGUNIT
INTERRUPTUNIT
INTERRUPTUNIT
PCPCLALA
LA2LA2
HWSHWSFIRAFIRAFISRFISR
SRSR
LCLCLC2LC2
OMROMR
2nd Data Access:XAB2 - 24 bitsXDB2 - 16 bits
1st Data Access:XAB1 - 24 bitsCDBR - 32 bits
Instruction Fetch:PAB - 21 bitsPDB - 16 bits
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Data ALU - General Purpose Register File
A1B1C1D1Y1Y0X0
A0B0C0D0
A2B2C2D2
DSP56800E
DATA ALU
Conventional DSP
DATA ALU
SRC1 SRC2
A1B1
A0B0
“Accumulator Based”
INC,DECASL,ASR
ADD, etc. SRC1 , A or B
A or B
“GP Register File”
INC.W, DEC.WASL, ASR
ADD, etc. FFF , FFF
FFF
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Supports 8, 16, 32-bitsSupports Modulo Arithmetic
Powerful Set of Addressing Modes
• Indirect• X:(Rn) No Update• X:(Rn)+ Post Increment• X:(Rn)- Post Decrement• X:(Rn)+N Post Update by Register
• Indexed• X:(Rn+x) Indexed:3-bit Offset• X:(SP-xx) Indexed:6-bit Offset• X:(Rn+xxxx) Indexed:16-bit Offset• X:(Rn+xxxxxx) Indexed:24-bit Offset • X:(Rn+N) Indexed: By a Register
• Immediate• #x 5-bit “Long” Constant• #xx 6-bit Loop Ct • #xx 7-bit Short• #xxxx 16-bit • #xxxxxxxx 32-bit
•Absolute• X:aa 6-bit Absolute Short• X:<<pp 6-bit Peripheral Direct• X:xxxx 16-bit Absolute• X:xxxxxx 24-bit Absolute
•Other• DDDDD Register Direct• * Inherent
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2005
56F8300 Series 60 MMACS32-512KB Program Flash48-160 Pins-40°C to +125°C
56850 Series120 MMACS20-128KB RAM81–144 Pins-40°C to +85°C
56F800 Series30/40 MMACS16-128KB Program Flash32-160 Pins-40°C to +85°C56F8000 Series 32MMACS12-64KB Program Flash32 - 64 Pins-40°C to +125°C
56F8100 Series 40 MMACS32-512KB Program Flash48-160 Pins-40°C to +105°C
56F8400 Series60 - 120 MMACSUp to 1MB Program Flash-40°C to +125°C
56F80556F80356F80156F802
56F80756F82656F827
56F803756F803656F802556F8023
56F836x56F836x56F836x
56F836x56F836x56F835x
56F836x56F836x56F834x
56F836x56F832x56F836x56F836x56F816x
56F836x56F836x56F815x
56F836x56F836x56F814x
56F836x56F812x
56F8335
56F8135
568585685756855568545685356852
56F84xx
Freescale Digital Signal Controller Roadmap
56F8100/830056F8100/8300
56F800056F8000
56F800x
20082006
56F8013
56F8011
56F8014
32Mhz
2010
60MHz
120Mhz
40Mhz
60MHz-120MhzExpected Products
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Embedded System Trend
0.35u 0.25u 0.18u 0.90nm
•Feature Integration•Operating Frequency
Total System
Cost
2000’s 2010’s
•Component Usage•Manufacturing cost
•Technology Geometry•Power Consumption
0.65nm
Controller C
ost
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SIMSIM
High Performance 56F8300 Solutions 56F836x/56F835x/56F834x/56F832x 60MHz/60MIPS
60 MIPS PerformanceProgram Memory
Up to 512Kbytes FLASHUp to 4Kbytes RAMUp to 32Kbytes BootFLASH ™
Data MemoryUp to 32Kbytes FLASHUp to 32Kbytes RAM
Serial Ports: SCIs and SPIs, CANsQuad, 4 channel, 12-bit ADCDual 6-Output PWM ModulesSynchronization between PWM and ADCUp to Sixteen multifunction 16-bit TimersExternal Memory InterfaceCOP/Watchdog TimerUp to 76 GPIO – Versatile pin usageSystem Clock GeneratorOn-chip temperature sensorOn-chip Voltage Regulator and Power SupervisorVectored Interrupt ControllerJTAG/OnCE™ Debug Port
GPIOGPIO2x4 Input2x4 Input
ADCADC2x4 Input2x4 Input
ADC ADC
56800E56800ECoreCore
60 MIPS60 MIPS60 MHz60 MHz
SCISCI
FlexCANFlexCAN
Voltage Voltage RegulatorsRegulators
COPCOP
JTAG/JTAG/EOnCEEOnCE
System ClockSystem ClockGeneratorGenerator
InterruptInterruptControllerController
PowerPowerSupervisorSupervisor
66--OutputOutputPWMPWM
66--OutputOutputPWMPWM
16 1616 16--bitbitTimersTimers
QuadratureQuadratureDecoderDecoder
SPISPI
Data FlashData Flash
Program Program FlashFlash
ProgramProgramRAMRAM
BootBootFlashFlash
External External Memory Memory InterfaceInterface
Data RAMData RAM
Temp SensorTemp Sensor
►Packages: 48/64/128/144/160LQFP and 160 MBGA►Derivatives: 23 devices Key Control Peripherals
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56F8300 Series (1 of 2)56F8322 56F8323 56F8335
Performance 60MHz/MIPS 60MHz/MIPS 60MHz/MIPSTemp. Range (-40, +125)°C (-40, +125)°C (-40, +125)°CVoltage (Core / I/O) 2.5/3.3V 2.5/3.3V 2.5/3.3VOn-Chip Flash 48KB 48KB 80KBProgram Flash 32KB 32KB 64KBData Flash 8KB 8KB 8KBBoot Flash 8KB 8KB 8KBOn-Chip RAM 12KB 12KB 12KBProgram RAM 4KB 4KB 4KBData RAM 8KB 8KB 8KBFlash Security Yes Yes YesExt. Memory Interface - - -Internal Voltage Regulator On-Chip On/Off-Chip On/Off-ChipOn-Chip Relaxation Osc. Yes Yes Yes16-bit Timers 8 8 16Quadrature Decoder 1 x 4ch 1 x 4ch 2 x 4chPWM 1 x 6ch 1 x 6ch 2 x 6chPWM Fault Input 1 3 4 + 4PWM Current Sense Pins 0 3 3 + 312-bit ADC 2 x 3ch 2 x 4ch 4 x 4chTemperature Sensor YES Optional OptionalCAN FlexCAN FlexCAN FlexCANSCI (UART) 2 2 2SPI (Synchronous) 2 2 2GPIO (Ded./Shrd/Tot) 0 / 21 / 21 0 / 27 / 27 21 / 28 / 49JTAG/EOnCE Yes Yes YesPackage 48LQFP 64LQFP 128LQFP
56F8322 56F8323 56F8335Performance 60MHz/MIPS 60MHz/MIPS 60MHz/MIPSTemp. Range (-40, +125)°C (-40, +125)°C (-40, +125)°CVoltage (Core / I/O) 2.5/3.3V 2.5/3.3V 2.5/3.3VOn-Chip Flash 48KB 48KB 80KBProgram Flash 32KB 32KB 64KBData Flash 8KB 8KB 8KBBoot Flash 8KB 8KB 8KBOn-Chip RAM 12KB 12KB 12KBProgram RAM 4KB 4KB 4KBData RAM 8KB 8KB 8KBFlash Security Yes Yes YesExt. Memory Interface - - -Internal Voltage Regulator On-Chip On/Off-Chip On/Off-ChipOn-Chip Relaxation Osc. Yes Yes Yes16-bit Timers 8 8 16Quadrature Decoder 1 x 4ch 1 x 4ch 2 x 4chPWM 1 x 6ch 1 x 6ch 2 x 6chPWM Fault Input 1 3 4 + 4PWM Current Sense Pins 0 3 3 + 312-bit ADC 2 x 3ch 2 x 4ch 4 x 4chTemperature Sensor YES Optional OptionalCAN FlexCAN FlexCAN FlexCANSCI (UART) 2 2 2SPI (Synchronous) 2 2 2GPIO (Ded./Shrd/Tot) 0 / 21 / 21 0 / 27 / 27 21 / 28 / 49JTAG/EOnCE Yes Yes YesPackage 48LQFP 64LQFP 128LQFP
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56F8300 Series (2 of 2)56F8345 56F8346 56F8347 56F8355 56F8356 56F8357 56F8365 56F8366 56F8367
Performance 60MHz/MIPS 60MHz/MIPS 60MHz/MIPS 60MHz/MIPS 60MHz/MIPS 60MHz/MIPS 60MHz/MIPS 60MHz/MIPS 60MHz/MIPSTemp. Range (-40, +125)°C (-40, +125)°C (-40, +125)°C (-40, +125)°C (-40, +125)°C (-40, +125)°C (-40, +125)°C (-40, +125)°C (-40, +125)°CVoltage (Core / I/O) 2.5/3.3V 2.5/3.3V 2.5/3.3V 2.5/3.3V 2.5/3.3V 2.5/3.3V 2.5/3.3V 2.5/3.3V 2.5/3.3VOn-Chip Flash 144KB 144KB 144KB 280KB 280KB 280KB 560KB 560KB 560KB Program Flash 128KB 128KB 128KB 256KB 256KB 256KB 512KB 512KB 512KB Data Flash 8KB 8KB 8KB 8KB 8KB 8KB 32KB 32KB 32KB Boot Flash 8KB 8KB 8KB 16KB 16KB 16KB 16KB 16KB 16KBOn-Chip RAM 12KB 12KB 12KB 20KB 20KB 20KB 36KB 36KB 36KB Program RAM 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB Data RAM 8KB 8KB 8KB 16KB 16KB 16KB 32KB 32KB 32KBFlash Security Yes Yes Yes Yes Yes Yes Yes Yes YesExt. Memory Interface - Yes Yes - Yes Yes - Yes YesInternal Voltage Regulator On/Off-Chip On/Off-Chip On/Off-Chip On/Off-Chip On/Off-Chip On/Off-Chip On/Off-Chip On/Off-Chip On/Off-ChipOn-Chip Relaxation Osc. No No No No No No No No No16-bit Timers 16 16 16 16 16 16 16 16 16Quadrature Decoder 2 x 4ch 2 x 4ch 2 x 4ch 2 x 4ch 2 x 4ch 2 x 4ch 2 x 4ch 2 x 4ch 2 x 4chPWM 2 x 6ch 2 x 6ch 2 x 6ch 2 x 6ch 2 x 6ch 2 x 6ch 2 x 6ch 2 x 6ch 2 x 6chPWM Fault Input 4 + 4 3 + 4 3 + 4 4 + 4 3 + 4 3 + 4 4 + 4 3 + 4 4 + 4PWM Current Sense Pins 3 + 3 3 + 3 3 + 3 3 + 3 3 + 3 3 + 3 3 + 3 3 + 3 3 + 312-bit ADC 4 x 4 ch 4 x 4 ch 4 x 4 ch 4 x 4ch 4 x 4ch 4 x 4ch 4 x 4 ch 4 x 4ch 4 x 4chTemperature Sensor Optional Optional Optional Optional Optional Optional Optional Optional OptionalCAN FlexCAN FlexCAN FlexCAN FlexCAN FlexCAN FlexCAN FlexCAN (2) FlexCAN (2) FlexCAN (2)SCI (UART) 2 2 2 2 2 2 2 2 2SPI (Synchronous) 2 2 2 2 2 2 2 2 2
GPIO (Ded./Shrd/Tot) 21/ 28 / 49 0 / 62 / 62 0 / 76 / 76 21 / 28 / 49 0 / 62 / 62 0 / 76 / 76 21 / 28 / 49 0 / 62 / 62 0 / 76 / 76JTAG/EOnCE Yes Yes Yes Yes Yes Yes Yes Yes YesPackage 128LQFP 144LQFP 160LQFP 128LQFP 144LQFP 160LQFP 128LQFP 144LQFP 160LQFP
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56F8000 Series
New platform to address the needs of cost sensitive applicationsrequiring a high performance 16-bit solution
Extended Temperature• -40°C to +105°C• -40°C to +125°C
Low pin count, easy to manufacture with packages
Aggressive price points
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Cost Effective 56F8000 Solutions 56F8011/56F8013/56F8014
32 MIPS Performance 12K -16 K Bytes Program FLASH 4 K Bytes Program/Data RAM Tunable Internal Relaxation OscillatorSoftware Programmable Phase Locked LoopUp to 96 MHz Peripherals – Timers and PWMsUp to 6-Output PWM Module with up to 4
Programmable Fault Inputs•Selectable PWM frequency for each complementary PWM signal pairTwo 12-bit ADCs with up to 8 Inputs , 1.125us
conversion rateSynchronization between PWM and ADCFour 16-bit General Purpose Programmable TimersComputer Operating Properly TimerSerial Ports: SCI, SPI, I2CUp to 26 GPIOs – Versatile pin usageLow Power Consumption – 59mA Max and .026mA
MinJTAG/EOnCE™ Debug PortIndustrial & Automotive tempCost Effective
Package: 32LQFP
56800E Core32MHz
Power-On-Reset
Power Supervisor
COP
12K - 16KB Program Flash
6-ch PWM Output
System Integration Module (SIM) 1 x SCI
1 x SPI1x IIC
JTAG/EOnCE
4kB Program/Data RAM
Voltage Regulator
PLL
Interrupt Controller
Relaxation OSC3-4ch 12bit ADC3-4ch 12bit ADC
56F8011/56F8013/56F8014Up to 26 GPIOs
4Ch 16bit Timer
Synch
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56F8000 Family Expansion56F8023/56F8025/56F8036/56F8037 Features
32 MHz/32 MIPS 56800E Core3.0-3.6V Operation32K-64K Bytes Program FLASH4K-8K Bytes Program/Data RAM Flash securityTunable Internal Relaxation OscillatorSoftware Programmable Phase Locked LoopUp to 96 MHz Peripherals – Timers and PWMs6 Output PWM Module with 4 Programmable Fault InputsSelectable PWM frequency for each complementary
PWM signal pairTwo 12-bit ADCs with up to 16 Inputs , 1.125us
conversion rateUp to Two 12-bit Digital to Analog ConvertersTwo Analog ComparatorsSynchronization between PWM and ADC4 or 8 16-bit General Purpose Programmable Timers1 or 3 Programmable Interval Timers (PIT)Computer Operating Properly Timer2-Queued Serial Communications Interface 2-Queued Serial Peripheral InterfaceOptional MSCANI2C Communications InterfaceUp to 53 GPIOs – Versatile pin usageJTAG/EOnCE™ Debug PortLead Free “Green” PackagesIndustrial & Automotive tempPackage 32 LQFP, 44LQFP, 48LQFP, 64LQFP
56800E Core32MHz
Power-On-Reset
Power Supervisor
COP
32KB - 64KB Program Flash
6-ch PWM Output
System Integration Module (SIM) 2 x QSCI
2 x QSPI1xIIC
JTAG/EOnCE
4kB-8KB Program/Data RAM
Voltage Regulator
PLL
Interrupt Controller
Relaxation OSC
8ch 12bit ADC8ch 12bit ADC
56F8023/56F8025/56F8036/56F8037Up to 53 GPIOs
8Ch 16bit Timer
Synch
1x MSCAN
Crystal OSC
2 x Comparators2 x 12 bit DAC
3xPIT
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56F8000 Series Feature Summary 56F8011 56F8013 56F8014 56F8023 56F8025 56F8036 56F8037
Performance 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs 32MHz/MIPsTemperature Range (V) -40C to 105C -40C to 105C -40C to 105C -40C to 105C -40C to 105C -40C to 105C -40C to 105CVoltage Range 3.0V - 3.6V 3.0V - 3.6V 3.0V - 3.6V 3.0V - 3.6V 3.0V - 3.6V 3.0V - 3.6V 3.0V - 3.6V
Program/Data Flash 12KB 16KB 16KB 32KB 32KB 64KB 64KBProgram/Data RAM 2KB 4KB 4KB 4KB 4KB 8KB 8KB
On Chip Relaxation Osc. Yes Yes Yes Yes Yes Yes YesPLL Yes Yes Yes Yes Yes Yes YesCOP Yes Yes Yes Yes Yes Yes YesPWM 1 x 6ch 1 x 6ch 1 x 5ch 1 x 6ch 1 x 6ch 1 x 6ch 1 x 6chPWM Fault Inputs 4 4 3 4 4 4 412-bit ADCs 2 x 3ch 2 x 3ch 2 x 4ch 2 x 3ch 2 x 4ch 2 x 5ch 2 x 8ch12-bit DACs 2 2 2 2 (Pinned out)Analog Comparator 2 2 2 216-bit Timers 4 4 4 4 4 4 8Prog. Interval Timers 1 3 3 3GPIO (max) 26 26 26 26 35 39 53IIC 1 1 1 1 1 1 1SCI (UART) / LIN Slave 1 - SCI 1 - SCI 1 - SCI 1 - QSCI 1 - QSCI 1 - QSCI 2 - QSCISPI (Synchronous) 1 - SPI 1 - SPI 1 - SPI 1 - QSPI 1 - QSPI 1 - QSPI 2 - QSPICAN MSCAN MSCANJTAG/EOnCE JTAG/EOnCE JTAG/EOnCE JTAG/EOnCE JTAG/EOnCE JTAG/EOnCE JTAG/EOnCE JTAG/EOnCE
Package (V) - Industrial 32LQFP (.8p) 32LQFP (.8p) 32LQFP (.8p) 32LQFP (.8p) 44LQFP (.8p) 48LQFP (.5p) 64LQFP (.5p)
Voltage Regulator On-Chip On-Chip On-Chip On-Chip On-Chip
Program Security Yes Yes Yes Yes Yes Yes Yes
On-Chip On-Chip
NoNo
NoNo
NoNo
No No No
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• Up to 16K Bytes Flash memory• Up to 4K Bytes Unified RAM• On Chip Dual Harvard Architecture• Programmable “Code Protection”
feature• Programmable “Code Security” feature• Flash with 256 word page size enabling
EEPROM emulation (HW & SW Support)
• Can program one word at a time• Flash memory programmable via
JTAG/OnCE interface or user defined programming (such as SPI, SCI)
• Flash Signature Calculator• 32MHz operation for 56F80xx and
60Mhz operation for 56F83xx at 125oC
56F8000 Feature Highlights - Memory
56800E Core32MHz
Power-On-Reset
Power Supervisor
COP
12K - 16KB Program Flash
6-ch PWM Output
System Integration Module (SIM) 1 x SCI
1 x SPI1x IIC
JTAG/EOnCE
4kB Program/Data RAM
Voltage Regulator
PLL
Interrupt Controller
Relaxation OSC3-4ch 12bit ADC3-4ch 12bit ADC
56F80xxUp to 26 GPIOs
4Ch 16bit Timer
Synch
Memory
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• Clock PWM up to 96Mhz• Three complementary signal pairs or six
independent signals or combinations• Complementary channel operation
Separate Deadtime insertions for rising and falling edgeSeparate top and bottom polarity control
• Edge-aligned or center-aligned signals• 15-bits of resolution• Half-cycle reload capability• Asymmetric mode of operation (for phase shifting)• Programmable integral reload rates (half to 16)• Individually software-controlled PWM outputs• ADC synchronization• Up to 4 Programmable fault inputs• PWM compare output polarity control• 8 or 4 mA current source/sink• Output Polarity Control• Write protected registers• Double-buffered PWM registers• Wait/Debug mode operation• Selectable PWM supply source for each
complementary PWM signal pair (F8000family only)PWM GeneratorExternal GPIOInternal timer channelADC conversion result, taking into account values set ting ADC high and low limit register
Pulse Width Modulator (PWM)
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Pulse Width Modulator (PWM)PWM Function Block1) Timer Output
2) ADC Conversion Result3) GPIO Input
Dead Tim
e Generation
Prescaler PWMCounter
Comparator#1
PWM ValueRegister #1
Comparator#0
PWM ValueRegister #0
OUT1
OUT0
OUT CTR0(Software Ctr)
ChannelSwap
IndependentMode
Clock
Fault Decoder& Fault
AND
AND
XOR
XOR
Fault0Fault1Fault2Fault3
MASK0
MASK1
XOR
XOR
PolarityControl
PolarityControl
PWM0
PWM1
OutputPad
Enable
Q D
CLK
PWM ValueRegister Select
PWM Cycle Start
XOR
XOR
PolarityControl
PolarityControl
ExternalReset
Window
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FilterCapacitor
Converter
AC Input
Inverter
56F80xx/83xx
Fault 1
Fault 2
Fault 3
Fault 4
• Fault inputs can independently monitor critical system parameters, andgenerate an interrupt when asserted.
• Each input is mappable to immediately disable any or all PWMs• Each input is programmable to allow Automatic or Manual PWM restart
PWM - Multiple Fault Inputs
Load
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AND
AND
AND
ANDOR
DISMAP3 DISMAP2 DISMAP1 DISMAP0
Digital Filter
Digital Filter
Digital Filter
Digital Filter
Fault 0
Fault 1
Fault 2
Fault 3
DisablePWM 0
PWM Enable PWM Disable PWM Enable PWM Disable PWM Enable
PWM Output
PWM Modulo
PWM Value
Fault Input
*When Fault logic returns to logic 0, the PWM restart at beginning of the next half cycle.
PWM Fault Decode and Automatic Clearing
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56F8000 Feature Highlights - Quad Timers
• Up to 96 MHz operation• Four 16-bit general purpose up/down
timers• Individually programmable
Input capture triggerOutput compare captureSelectable input clock sourceQuadrature DecodePulse Generation
• Input pins are shareable within a timer module
• Each timer has separate prescalar• Counters are pre-loadable• Counters in module can be daisy-chained
to yield longer counter lengths, up to 64-bits
• Up to 12 operating modes• Timer outputs can generate PWM
complementary pair output signals
PRESCALER
MUX
CONTROL
COUNTER
TMRLOAD
TMRHOLD
CAPTURE
TMRCMP1
TMRCMP2
CMPLD1
CMPLD2
COMPARATOR
COMPARATOR
MUX OFLAG
OUTPUT
INPUTS
OTHER INPUTS
STATUS &
CONTROL
DATA BUS
QTimer ChannelQTimer ChannelPRESCA
LER
MUX
CONTROL
COUNTER
TMRLOAD
TMRHOLD
CAPTURE
TMRCMP1
TMRCMP2
CMPLD1
CMPLD2
COMPARATOR
COMPARATOR
MUX OFLAG
OUTPUT
INPUTS
OTHER INPUTS
STATUS &
CONTROL
DATA BUS
QTimer ChannelQTimer ChannelPRESCA
LER
MUX
CONTROL
COUNTER
TMRLOAD
TMRHOLD
CAPTURE
TMRCMP1
TMRCMP2
CMPLD1
CMPLD2
COMPARATOR
COMPARATOR
MUX OFLAG
OUTPUT
INPUTS
OTHER INPUTS
STATUS &
CONTROL
DATA BUS
QTimer ChannelQTimer ChannelPrimary Input
SecondaryInput
PRESCALER
MUX
CONTROL
COUNTER
TMRLOAD
TMRHOLD
CAPTURE
TMRCMP1
TMRCMP2
CMPLD1
CMPLD2
COMPARATOR
COMPARATOR
MUX OFLAG
OUTPUT
INPUTS
OTHER INPUTS
STATUS & CONTROL
DATA BUS
Quad-Timer ChannelQuad-Timer Channel
4 x Timer
Output
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Quad Timer: Simple Operating Modes
Timer0 Timer1 Timer2 Timer3
Signed Count Mode – Counts primary input up or down based on polarity of secondary input
Cascaded Count Mode - Input is connected to the output of another (Great for large counts up to 264)
Stop Mode - Counter is inert. No counting will occurCount Mode – Counts rising or falling edges(generating periodic interrupts, timing purposes)
Edge Count Mode – Counts rising and falling edges(counting of simple encoder wheel)
Gated Count Mode - Counts primary input if secondary input is high (signal width measurement)
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Quad Timer: Triggered Modes
Triggered Count Mode – Start/Stop count of Primary input on rising edge of Secondary input.
One-Shot Mode - Provides timing delays(ADC acquisition of new samples until a specified period of time has passed since the PWM sync signal occurred)
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Quad Timer: Other ModesFixed Frequency PWM - Fixed frequency, variable duty cycle(driving PWM amplifiers)
Variable Frequency PWM - Variable frequency and duty cycle (driving PWM amplifiers)
Pulse Output Mode - Supports stepper motor systems and provides change of signal frequency and number of pulses
Primary
Count 0 1 2 3 4 0
Output
Count Mode Timer is Off Timer is in Count Mode
TimerStopped dueto Compare(COMP1 = 4)
Quadrature Count Mode• Counter will decode the primary and secondary external
inputs as quadrature encoded signals• Compare interrupts will signal commutation
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• 12-bit resolution• Two ADCs per module
6 to 8 Analog Inputs per moduleIndependent sampling frequency per ADC
• Sampling rate up to 1.78 million samples per secondSequential: First 1.59us subsequent 1.125usSimultaneous: 8 conversions in 4.48us
• Can be internally synchronized to a PWM reload event• Simultaneous or sequential sampling• Optional sample correction by subtracting a pre-
programmed offset value• 4 Interrupt types:
End of a scan, zero crossing, High/Low limitHigh/Low Limits can control PWM outputs
• Signed or unsigned result• Single-ended or differential inputs for all input pins with
support for an arbitrary mix of input types• Power savings modes
Explicit power down of all/part of ADCIntelligent power savings mode: Auto wake-up
• Internal or External Voltage Reference
Analog to Digital Converters
Note: 56F83xx conversion time:• Sequential: First 1.7us subsequent 1.2ns
• Simultaneous: 8 conversions in 5.3us
ANA0ANA1ANA2ANA3ANA4ANA5ANA6ANA7ANB0ANB1ANB2ANB3ANB4ANB5ANB6ANB7
MU
X
Sample/Hold
VoltageReference
Circuit
VREFH
VREFLO
SYNCn Controller
Scalling andCyclic Converter A
Scalling andCyclic Converter B
12
12
Digital OutputStorage
Registers
Bus Interface Data
IRQ
16
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Once• The ADC starts to sample just one
time whether you use the START bit or by a sync pulse. This mode must be re-armed by writing to the ADCR1 register again if you want to go capture another scan
Triggered• Sampling begins with every
recognized START command or sync pulse
Loop• The ADC continuously take samples
as long as power is on and the STOP bit has not been set
Sequential Mode• Sequential will sample SampleN one
after another. Channel ANAx are sampled by ADCA and Channel ANBx are sampled by ADCB
Parallel Mode• Simultaneous: Parallel can sample
SampleN from Group1 and SampleN from Group 2 at the same time.
• Independent:: ADCA and ADCB can operate independently. At end of scan of each ADC, they generate separate interrupt request.
56F8000 ADC Channel Scan Modes
SYNCx
Voltage Reference
Circuit
Controller
VREFHI
VREFLO
Scaling and Cyclic Converter A 12Sample/
Hold
ANA0
MUX
ANA1ANA2ANA3ANB0ANB1ANB2ANB3
SequentialMode Result Reg 0
Result Reg 1
Result Reg 2
Result Reg 3
Result Reg 5
Result Reg 7
Result Reg 6
Result Reg 4Scaling and Cyclic Converter B
12
Voltage Reference
Circuit
ControllerSYNCA
VRETHVREFPVREFM
IDVREFN
VREFLO
Scaling and Cyclic Converter A0
Scaling and Cyclic Converter A1 12
12Sample/Hold
ANA0
MUX
ANA1ANA2ANA3ANA4ANA5ANA6ANA7
SimultaneousMode Result Reg 0
Result Reg 1
Result Reg 2
Result Reg 3
Result Reg 5
Result Reg 7
Result Reg 6
Result Reg 4
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ADC Synchronization With The PWM
AD
C s
tart
si
gnal
ControlAlgorithmExecution
PWM
val
ues
Writ
ten
tore
gist
ers
ADCConvert
PWM Synch signal
TimerDelay
PWM
val
ues
Upd
ated
AD
C In
terr
upt
PWM
syn
ch
puls
e
PWM Output
ISRLatency
Traditional Solution
56F801x Solution
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A/D Converters - PWM Synchronization Benefits
ADC Sampling helps to filtering the measured current - antialiasing.Noise free ADC sampling when the power switch is not actingADC sample is taken when Current information is available
PWM Period
PWM topPWM Bottom
Phase Current
Sampled and Average Currents
Shunt ResistorSignals
A/D
calc.
New PWM Parameters Calculation with Half-cycle Reload
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56F8000 Digital to Analog Converters
12 bit ResolutionUp to Two independent voltage mode DACs2us settling time settling time when output swing from rail to rail at 3KΩ/400pf loadOutput glitch filter to eliminate switching glitchesTwo output update modes
Asynchronous – Update On-demandSynchronous – Update based on PIT or Timer Overflow, or PWM synch signal
Automatic waveform generation generates square, triangle and sawtooth waveforms with programmable period, update rate, and rangeSoftware controlled power down mode
56800E Core32MHz
Power-On-Reset
Power Supervisor
COP
32KB - 64KB Program Flash
6-ch PWM Output
System Integration Module (SIM) 2 x QSCI
2 x QSPI1xIIC
JTAG/EOnCE
4kB-8KB Program/Data RAM
Voltage Regulator
PLL
Interrupt Controller
Relaxation OSC
8ch 12bit ADC8ch 12bit ADC
56F8023/56F8025/56F8036/56F8037Up to 53 GPIOs
8Ch 16bit Timer
Synch
1x MSCAN
Crystal OSC
2 x Comparators2 x 12 bit DAC
3xPIT
Digital to Analog
Converters
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56F8000 Analog ComparatorsUp to Two continuous-time differential-input analog comparator modules
Internal switching matrix supports the independent connection of the analog inputs to the positive or negative input of the analog comparator and to the comparator’s export output for another Comparator module.
5 selectable Input sources:
Three GPIO Pins.
One DAC output,
One import input from another comparator module
Programmable comparator output polarity
Comparator output edge indicator
Interrupt can be generated by comparator output rising edge, or falling edge, or both edges
Comparator output can be fed to timer input, PWM faults input, PWM source, external pin output.
Software controlled power down mode
56800E Core32MHz
Power-On-Reset
Power Supervisor
COP
32KB - 64KB Program Flash
6-ch PWM Output
System Integration Module (SIM) 2 x QSCI
2 x QSPI1xIIC
JTAG/EOnCE
4kB-8KB Program/Data RAM
Voltage Regulator
PLL
Interrupt Controller
Relaxation OSC
8ch 12bit ADC8ch 12bit ADC
56F8023/56F8025/56F8036/56F8037Up to 53 GPIOs
8Ch 16bit Timer
Synch
1x MSCAN
Crystal OSC
2 x Comparators2 x 12 bit DAC
3xPIT
AnalogComparators
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INV
Export to CMP_B
ProgrammableGlitch Filter
CIN_A0
CIN_A1
CIN_A2
DAC_A
ESEL [0,1] NSEL [0,2]
PSEL [0,2]
+
-CMP_A 0
1
PDN
MUX
MUX
MUX
Import From CMP_B
COUT
Rising EdgeInterrupt Request
Falling EdgeInterrupt Request
To Timer A1
To PWM
To GPIO
To PWM Fault 1
Analog Comparator Interconnection
Negative inputSource Select
Positive inputSource Select
ExportSource Select
Power Down
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Interrupt Priority Structure
IPL Description Priority Interrupt Sources
LP Maskable Lowest SWILP Instruction
0 Maskable * On-chip peripherals, IRQA and IRQB, SWI #0 Instruction
1 Maskable * On-chip peripherals, IRQA and IRQB, SWI #1 Instruction
2 Maskable * On-chip peripherals, IRQA and IRQB, SWI #2 Instruction
3 Non-maskable Highest Illegal instruction, hardware stack overflow, SWI instruction, EOnCEInterrupts, misaligned data access
I1 I0 CCPL* Exceptions Accepted
Exceptions Masked
Comments
0 0 0 IPL 0,1,2,3, and SWILP
None This interrupt controller accepts any unmasked interrupt, including the SWILP
0 1 1 IPL 1,2,3 IPL 0 and SWILP
This interrupt controller accepts all non-maskable interrupts and any unmasked interrupts that are programmed at level 1 or 2
1 0 2 IPL 2,3 IPL 0 , 1 and SWILP
This interrupt controller accepts all non-maskable interrupts and any unmasked interrupts that are programmed at level 1
1 1 3 IPL 3 IPL 0, 1, 2 and SWILP
This interrupt controller only accepts all non-maskableinterrupts
Interrupt Priority Level Summary
Current Core Interrupt Priority Levels
* CCPL:Current Core Interrupt Priority Level
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Interrupt Arbiter
...
Standard Interrupt Arbitration
MisalignedData Access
HWS Overflow
SWI #3
IllegalInstruction
PriorityLevelSelect Bits
PriorityLevelSelect Bits
... PriorityLevelSelectBits
PriorityLevelSelectBits
PriorityLevelSelectBits
PriorityLevel 3Arbiter
PriorityLevel 2Arbiter
PriorityLevel 0Arbiter
PriorityLevel 1Arbiter
LowestPriority
SWILPInstruction
SWI #2 SWI #1 SWI #0
I1I0
Interrupt Mask Bit
Interrupt Request Vector Table Address New Interrupt Priority Level
BKPT_U0 TPBUF IRQA IRQB SCI1_RCV
Peripheral Interrupt SourcesEOnCE Interrupt Sources
If Priority level selectBits is set to 00, theinterrupt is disabled
•EOnCE Interrupt Sources can be assigned to priority level 3, 2, and 1. •Peripheral Interrupt sources can be assigned to priority level 2, 1, and 0.•Any interrupt sources can interrupt Lowest-Priority Software Interrupt (SWILP interrupt).
InterruptController
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Standard Interrupt Processing
► Vectored Interrupts - Vectors may be located anywhere in Program Memory► 4 Priority Levels - Highest is non-maskable► Software Traps at each priority level► One additional software trap (5th level) at lowest priority for O/S support
ExplicitReturn From
Interrupt(RTI)
MainProgram
n1n2
General Case:
InterruptSubroutine
PC ResumesOperation
InterruptRoutine
ii2ii3ii4
iinRTI
InterruptVector Table
JSRJmp Addr (LBL)
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The “Fast Interrupt”
► Vectors directly to service routine► Operates at Interrupt Level 2 - Highest “maskable” priority► The Frozen PC is copied to FIRA, the status register and NL bit are copied to FISR ► Automatically swaps registers with shadows: R0, R1, N, and M01► Automatically aligns SP and pushes the Y0 and Y1 registers onto the stack► Automatically advances the SP to an empty 32-bit location► Automatically restores above registers on exit, and restores original SP
Fast Interrupt Case (Improved latency and throughput):
ExplicitReturn FromFast Interrupt
(FRTID)
MainProgram
n1n2
InterruptVector Table
Fast InterruptSubroutine
ii0ii1ii2ii3
FRTIDdly0dly1
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Example - Fast Interrupt for A/D
► The A/D’s interrupt request is programmed for Level 2 (highest maskable level)► The shadow registers are initialized:
• M01 <== SIZE - 1• R0 <== A/D’s memory mapped register • R1 <== start address in Output Buffer• Swap R0, R1, M01 with their shadow registers by using instruction” SWAP SHADOWS”
Initializing the Fast Interrupt:
► The first instruction must not be JSR or BSR► FRTID is used to return from interrupt (2 delay slots)
The Fast Interrupt’s Service Routine:
Read value from A/D into a Circular Buffer in Memory:
;Fast Interrupt Service RoutineFRTID ; Return from interrupt - 2 delay slotsMOVE.W X:(R0),Y0 ; Read value from A/D peripheralMOVE.W Y0,X:(R1)+ ; Write value to circular buffer in memory
Total Execution Time:Total Execution Time:7 Cycles7 Cycles
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56F8000 Cost Saving 56800E architecture optimized for C language
• Reduce software development cost• Software can be modular and reused
On-Chip 12bit Digital-to-Analog Converters (DAC) and Comparators • Dynamic reference settings• High speed comparator – Propagation delay: 50ns for internal comparator vs. 1us for external one
On-Chip Power-on reset and Low voltage detection• Eliminate external Reset and power supply monitor chip.
Single 3.3V supply and 5V I/O port.• Reduce power supply cost • Directly interface with 5V system without level shift device
On-Chip regulator improves device EMI acceptability• On-Chip 2.5V linear regulator powers the CPU and peripheral logic circuits
On-Chip Relaxation oscillator• Eliminate external crystal and reduce PCB size.• Greatly improve EMI acceptability
Smaller Flash memory page size• Enable User to designate a page flash as EEPROM ( eliminate external EEPROM devices)
5 Level interrupt priority• Reduce interrupt overhead• improve software efficiency
Enhanced On-Chip Emulator• Enable debug of target system using cost effective, isolated debug tool.
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JTAG /OnCE
Controller
Host System(Windows)
Parallel cableOr
USB cable
On-Chip Emulator
DSP56800/ETargetSystem
1
1325
14
Port IDNT
1A11A21A31A42A12Y22Y32Y4
VCCGND
1Y11Y21Y31Y42Y12A22A32A4
PORT-RESETPORT-TMSPORT-TCKPORT-TDIPORT-TRST
PORT-VCC
PORT-TDO
PORT-CONNECT
51 OHM
51 OHM1G2G
1A11A21A31A42A12Y22Y32Y4
VCCGND
1Y11Y21Y31Y42Y12A22A32A43.3V
1G2G
3.3V
3.3V
/RESET
TMSTCKTDI/TRSTTDO
10k
ohm
1k o
hm DSP56800E
5453
514749
110
74HC244 74HC244
Reset Switch
JTAG Converter
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Applications
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Harm Of Input Harmonics
►Filter capacitance behind the rectifier diodes on in intermission
►Input current aberrance include large number of harmonics
►Sequence: pollute, EMI, interfere etc
DC/DCconverter
LOADui
i i
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Control Method Of PFC Circuit
Peak current control: makes the inductor current follow the reference current: THD distortion is serious;Hysteresis current control: inductor current increases to the upper limit, mosfet off; otherwise, it decreases to the low limit, mosfet on; simple to control, quick dynamic response ,switch frequency changes with duty.Average current control: inductor average current follows the reference current. little current error; little THD and EMI; immune to noise; widely used.
Peak current control Average current controlHysteresis current control
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Average Current PFC Control
One Mosfet BOOST PFC circuit is widely used.two main tasks of PFC mission:
1 control inductor current - to make current sinusoidal2 control output voltage - to insure voltage invariance
AC
LOAD
*ovVEA
Driver
MUL
vov
inv
Li *Li
ovVEA
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Cycle-By-Cycle Controlled PWM
COMP
T T T T T TT: PWM Period
PWM Start
PWM runs at a constant period with pre-set 100% duty cycle. When feedback is greater than reference, the PWM output is truncated (disabled).
Reference
Feedback
PWM ModuleFault
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►Peak current mode control for PFC
Cycle-By-Cycle Controlled PWM
LOAD
RCFilter
COMP
PWM Module
Fault
GateDrive
PWM
ANAT0
ANB
Reference
Feedback
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Power Supply applicationsDigital AC to DC Switch mode Power Supply
AC to DC conversion with Power Factor Correction
DC to DC conversion using Soft Switching Technology
Isolation
Q2
1
3Q
2
1
3
T
1
5
4
8
-+ D
1
2
3
4
Q1A2
1
3
R?1 2
R?
12
R?
12
+C
12
FUSE1 2
1 2
L
1 2
ISO?
12
5
4
L
1 2
R
12
L1A1 2
Q2A2
1
3
FUSE1 2
L2A1 2
Q2
1
3
R
12
+C
12
D2A1 2
D1A1 2
ISO?12
5
4
PWM0
AC
If1
Vsychr
AC
PWM2-5If1
b
b
b
VfVfIf2
PWM3
b b
Vo
b
Q2
1
3
ADC ADC
SPI / SCISPI / SCI
MC56F8036MC56F8014
T11 5
4 8
T
15
48
R
1
R
+C
21
R
Q2
13
Q2
1 3
TMRA0&1
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Interleaving PFC
MC56F8013
1800
I1
I2
PWM0 PWM1
I
1800 1800 1800 1800 1800 1800
I1PWM0
PWM1
I2
ADC
I
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A/D Converters - PWM Synchronization Benefits
ADC Sampling helps to filtering the measured current - antialiasing.Noise free ADC sampling when the power switch is not actingADC sample is taken at middle of PWM pulse which is equal to average Current
PWM Period
PWM 0PWM 1
Inductor Current I1
Sampled and Average Currents
A/D
calc.
New PWM Parameters Calculation with Half-cycle Reload
ADC trigger Signal
Inductor Current I2
Trigger ADCA Trigger ADC
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PWM Module PWMs
ADC Synchronization from the PWM Module
ADC A
Sync pulse
ADC Trigger
PWM Signal
Sync Pulse
Timer Trigger(Rising EdgeTrigger ADC) Convert anywhere
within thePWM cycle
56F80xx/83xx
Time delay
Timer A3One Shot Mode
Time delay
I1
I2
ADC BADC Trigger
PrimaryClock
Source
Timer A2One Shot Mode
Time delay
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PFC Software Bandwidth
PWM ReloadInterrupt
BackgroundLoop
Volta ge
Loo p
Aver age
inpu tvo ltage
c alcula ti on
Curr entLoo p
Dis play
val uecal culat ion
Volta ge
Loo p
Aver age
inpu tcu rrent calculation
Curr entLoo p
Dis play
val uecal culat ion
Volta ge
Loo p
Aver age
inpu tvo ltage
c alcula ti on
Curr entLoo p
Dis play
val uecal culat ion
ADC
Reload period #1 Reload period #2 Reload period #3
PWM ReloadInterrupt occur
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Phase shifting control
PWM Modulus
OddPWM ValueReg
EvenPWM ValueReg
OddPWM ValueReg
EvenPWM ValueReg
OddPWM ValueReg
EvenPWM ValueReg
T1
T2
T4
T3
T1 ON T1 ON T1 ON
T2 ON T2 ON T2 ON
T4 ON T4 ON T4 ON
T3 ON T3 ON
VAB
Soft switching operation
T1
T2
PWM0
PWM1
PWM3
PWM2
T3
T4
+
T5
T6
TA0
TA1
Vout
PWM Module Timer A1One Shot Mode
56F80xx/3xx
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PWM Module PWMs
Synchronous Rectification
Sync pulse
56F80xx/83xx
Timer A2One Shotr Mode
ResetTA0
Output
Timer A0One Shot Mode
Timer A1One Shot Mode
T1
T2
T4
T3
VAB
PWM Sync
Timer A2
Timer A0
Timer A1
StartDelay
StartDelay
StartDelay
PrimaryClock
Source
Reset TA0
Reset TA0
Time Delay
Time Delay
Time Delay
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Digital controlled isolated DC-DC Converter
Q1 D1 C1 DR1Cf LDR
Vin Q3 D3 C3
Q2 D2 C2
Q4 D4 C4
Lr
DR2
Lf
Rio
Tr
TiL
Singal ( I o)Conditioning
Singal ( Uo)Conditioning
Singal ( I L)Conditioning
IsolatedGate Drive
GPIOA 10GPIOA 9
GPIOA 11GPIOA 6GPIOA 5
GPIOA 7
G1 G2 PWM 3PWM 4PWM 5
PWM 2
Vr
FAULT 2
ANA 5ANA 6
ANA 1
HardwareProtect
DSP 56F8323 to primary DSP
LED
DSP56F8323
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DC to DC Software Bandwidth
PWM ReloadInterrupt
BackgroundLoop
Volta ge
Loop
C urr entL oop
Displ ay
val uecalc ula ti on
Volta ge
Loop
C urr entL oop
Displ ay
val uecalc ula ti on
Volta ge
Loop
C urr entL oop
Displ ay
val uecalc ula ti on
ADC
Reload period #1 Reload period #2 Reload period #3
PWM ReloadInterrupt occur
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Hybrid Digital Control
SlopeCompensation
CurrentRegulator
CMPDAC
DigitalPWM Module
VoltageRegulator
Inductor CurrentFeedback
Voltage Feedback
--+ +
Peak CurrentMode Control
Average CurrentMode Control
MC56F802x/3x
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Renewable Energy- Solar Panel
MC56F8013PWM0 PWM1 ADC0 ADC1
PWM0&1 PWM2&3ADC0
ADC1MC56F8037
MC56F8013
DC/DC BoosterIsolated DC/AC Inverter
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56F8000 Demonstration Kit
• Contents:• Demo Board• Complimentary permanent license for
CodeWarrior® Development Studio with Processor Expert™ tool
• Utilizes on-chip oscillator• JTAG-to-Parallel Port command converter
and parallel cable• Power supply• Preprogrammed sample application• Accelerated Development System CD• On-board expansion capabilities for
development activities• Ordering Part Number and SRP:
• DEMO56F8013-EE • DEMO56F8014-EE
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56F8037 Demonstration Kit
• Contents:• Demo Board• Complimentary permanent license for
CodeWarrior® Development Studio with Processor Expert™ tool
• Utilizes on-chip oscillator (optional off Chip Crystal)
• USBTAP™ Host Target Interface• Addition USB cable to power board via USB
port• 9V-12V power supply connector • Preprogrammed sample application• Development System CD• On-board 60pin dual row connector
expansion capabilities for development activities
• Ordering Part Number and SRP:• MC56F8037EVM
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Tools Library• Cycle Count, FIFO, FileIO,
Test
Memory Manager• Dynamic allocation
Application Specific Software LibrariesModem Libraries• V.8bis, V.21, V.22bis,
V.42bis
Telephony Libraries• AEC, AGC, Caller ID,• CAS, CPT, CTG, DTMF• G165, G168, G711• G723, G726, G729
Security Libraries• RSA, DES, 3DES,
Math Libraries• Matrix, Fractional, Vector• Trigonometric
Feature Phone Library• CallerID type 1and2,
CallerID Parser, Generic Echo Cancellor Motor Control
• BLDC, ACIM, SR motor specific algorithms
• General purpose algorithms
DSP Library• FIR, IIR, FFT, Auto
Correlation, Bit Reversal
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Development Tools - Code Warrior™
CodeWarrior™ Release 8.x for 56800/EComprehensive, scalable application development environment allows concurrent approach to hardware, software and system level engineering to minimize time-to-market.• CodeWarrior™ Development Studio incl. C compiler, assembler, linker, debugger• New QEDesign Lite filter design tool• Stand alone Flash programming software• Processor Expert™ rapid application development (RAD) tool•Quick Start ™ Low level Peripheral Driver provide User Flexibility to Access All Hardware Resources. • License Pricing:
<= 32K bytes FREE license for entire 56F801x/2x Series<= 64K bytes Please contact Freescale Representative<= 128K bytes Please contact Freescale RepresentativeUnlimited Please contact Freescale Representative
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Free Filter Design Tool• Launch QED Filter Design Package.
• Select EquirippleFIR Design,
Lowpass.
• Input filter parameters,select Next,get 31 taps, select Next.
This filter has samenormalized trans.bandwidth as priorexample:
450625.0
≈=′Δ
tapsNf
Only need 31 taps because of 1 dB passband ripple
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Equiripple (Parks McClellan) FIRs
►Clearly the most popular approach to FIRs• Supports arbitrary
band shape• Filters have equiripple
in each passband orstopband
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Filter Design - Graphic Results• Here’s what
you shouldsee:
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Filter Design – Coefficients
• Save the coefficients generated.
• Place TestFIRCoefs.h file in Filter Lab project.
• Rebuild filtering project with “new” coefficients. Download and run project.
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Why 56F8000? High performance Nonvolatile Memory – Flash memory
• Fast access speed, small page size enables user to designate a flash page as EEPROM• Longer Data retention and higher program erase cycles• Wide operating temperature range ( -40C to 125C ambient operating temperature)
High speed/flexible PWM module• Improved PWM resolution on both duty cycle and frequency – Resonant converter applications• Arbitrary PWM pulse generation which can be used for any power stage topology
High speed, 12 Analog-to-Digital Converter• High input impedance• Various power operating modes
High performance On-chip Analog Modules - DACs, Comparators,• Allowing analog designer to work in digital control world• Low offset, lifetime drift and gain error• Programmable comparator hysteresis• Adaptive slope compensation for peak current mode control
On-Chip Power-on reset and Low voltage detection• Eliminate external Reset and Power supply monitoring devices.
On-Chip regulator improves device EMI acceptability• On-Chip linear regulator powers the CPU and peripheral logic circuits
Multiple clock sources – multiple On-Chip clocks and external clock source• Clock redundancy• Greatly improve EMI acceptability
Enhanced On-Chip Emulator• Enables debugging of target system using low cost, isolated debug tool.
5V I/ODirectly Interface to drive circuit
Low Cost Development ToolEnhanced On-Chip Emulator - Enables debugging of target system using low cost, isolated debug toolFree 32KB CodeWarrior License
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TM