The aim of the NEMO collaboration is to investigate neutrinoless double-beta decay. This research is one of the principal topics in neutrino physics, which is a subfield of particle physics with cosmological and astrophysical implications.

Double-beta decay experiments can play a particularly interesting role in providing the answers to questions on the nature of the neutrino. Of paramount importance is the identification of the neutrino as a Dirac particle or Majorana particle.

The SuperNemo detector will be composed of about 20 modules. Each module will contain a chamber to measure the particle path and a calorimeter to measure the energy.

The SNATS chip has been designed for the calorimeter.

SNATS SuperNemo Absolute Time Stamper, a high resolution and large dynamic range TDC for SuperNemo experiment

aDominique Breton, bLaurent Leterrier, aVanessa Tocut, bPhilippe Vallerand, aCNRS/IN2P3/LAL-ORSAY, bCNRS/IN2P3/LPC-CAEN/SEM

Introduction: SuperNemo experiment

SNATS

Tests and measurements

Calorimeter Front-End Electronics

Timing characteristics: Bin size (LSB): 195.3ps Reference clock frequency: 160 MHz Dynamic range: ~20 days Single channel mode: Resolution 71ps (RMS) DNL single ( / max): 0.083 / 0.2 LSB INL single ( / max): 0.36 / 1.3 LSB Differential channel mode: Resolution 101ps (RMS) DNL diff ( / max): 0.024 / 0.08 LSB INL diff ( / max): 0.514 / 1.8 LSB Crosstalk: < 1 bin

Functional characteristics: Number of channels: 16 Power consumption: 380mW Reference clock frequency levels: LVDS or CMOS Hit inputs logic levels : LVDS or CMOS Buffer depth (hit register): 1 Output word length: 16 bits Silicon area: 12.7mm2

Package: 100-pin ceramic CQFP

Test board

20,000 PhotoMultipliers

1,250 SNATS chips

INL histogram

1 SuperNemo detector module

For running in double-beta mode in the SuperNEMO experiment, it has been decided to work without a hardware trigger and with absolute time measurements.

To achieve this requirement, a time stamp system is needed for the calorimeter front-end electronics.

The SNATS chip is designed to provide both a high resolution of 70ps RMS and a large dynamic range of 53 bits.

voltage controlled

delay line : 32 cells

Phase

Detector

Master

Clock

Hit Fine Time Memory

32 shifted

phase clocks

@ 160 MHz

Delay Locked Loop

Coarse Time Counter

48 bits

Coarse Time Memory

Fine

Time

Decoder

48 bits

Time

measurement :

53 bits

48 bits

5 bits

SNATS principle

Fine time measurement (high resolution) Delay Locked Loop Coarse time measurement (dynamic range) 48-bit counter

Association of a counter and an interpolator

SNATS architecture 8 DLL’s single ended (1 DLL for 2 channels) and a common counter

Based on the association of a first starved inverter followed by a second standard inverter.

DLL’s delay cell

Voltage controlled delay cell curve

100

150

200

250

300

350

400

450

1 1,5 2 2,5

Voltage charge pump (V)

(ps)

Cell

delay

DLL’s delay cell

Only one counter is used -> synchronizer to avoid any junction error

Synchronizer block diagram

Readout interface

the principle consists in generating a hit coarse delayed

in function of the relative position of the hit arrival

within the clock period. Timing of the specific synchronizer signals

1 hit register of 16 bits 1 data register of 4 x 16 bits : 53 significant bits of data (all gray) Readout clock: 40 MHz Max readout time (1 ch): 400ns

Synchronizer

195ps

slope 0.15 ps/mV

DNL histogram

Conversion error histogram Conversion error histogram

DNL histogram

INL histogram

Single channel measurement Differential channel measurement

Clock

Hit

MSB bits

Time measurement

Counter

DLL

Synchroniser

LSB bits

Latchin

out

L

Registerin

out

C

hit_counter

Latchin

out

L

Register

in out

Chit_dll

status_dll

Clock

Hit

MSB bits

Time measurement

Counter

DLL

Synchroniser

LSB bits

Latchin

out

L

Registerin

out

C

Latchin

out

L

Registerin

out

C

hit_counterhit_counter

Latchin

out

L

Register

in out

C

Latchin

out

L

Register

in out

Chit_dll

status_dll

0 1 2 3

10 1 2 3

10 1 2 3

10 1 2 3

10 1 2 3

10 1 2 3

1

Clock

N N+1N-1Counter N N+1N-1Counter

DLL

Hit

Hit _dll

Hit_counter

Hit

Hit _dll

Hit_counter

Status_dllStatus_dll

Hit+<i>

Data_Select<0:1>

Word_Select<0:1>

Adress_ch<0:3>

Data<0:15> 0 Voie touchée = i LSB MSB

0 i

i 0

0

10 01

00 10 01 11 00

10

Clear

4321

Hit register

15 i 0

0 1 00 1 0

Data register

out

VDD

GND

V_control_P

V_control_N

in

V_control_P

V_control_N

VDD

GND

in out

reg1 reg2phase

detector

DNL (/ max): 0.024 / ± 0.08 LSB

-0,04

-0,02

0

0,02

0,04

0,06

0,08

0,1

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31

bin

DN

L (

LS

B)

DNL ( / max): 0.083 / ± 0.2 LSB

-0,25

-0,2

-0,15

-0,1

-0,05

0

0,05

0,1

0,15

0,2

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31

bin

DN

L (

LS

B)

Resolution : 71ps (RMS)

Time (ps)

IN

L (

LS

B)

Time (ps)

IN

L (

LS

B)

AMS CMOS 0.35m technology chip area ~ 12.7mm2

SNATS layout

INL (/ max): 0.36 / 1.3 LSB

Timing of parallel read-out signals

DNL (/ max): 0.083 / 0.2 LSB DNL (/ max): 0.024 / 0.08 LSB

calorimeter : 1,000 PhotoMultipliers tracking : 3,000 Geiger cells

Characterization of the Differential NonLinearity ( DNL ) was performed using statistical code density tests from a data set of 1,000,000 random hits.

To measure Integral NonLinearity and time resolution, a linear time sweep over complete dynamic range was performed in order to measure errors of random nature such as jitter, electronic noise…..

A high performance generator was used to provide a time sweep of 5ps. The conversion histogram error includes 1,250,000 measurements generated with a time step of 5 ps, accumulating 1,000 measures per time step.

Concerning the performances, a Differential NonLinearity around 0.2 LSB has been measured, as well as an Integral NonLinearity about 1.3 LSB and a time resolution of 70 ps (RMS).

The static power dissipation is of about 380mW.

DLL registers

5-bit gray encoder

Counter registers

48-bit gray counter

Synchronizer

Hit register

Data

selection

+

-

Adress

decoder

Hit[0:15]

Vcom_hit

+

-

Clk_LVDS+

Clk_LVDS-Clk

195ps 195ps 195ps 195ps

VCDL

Phase

detector

Charge

pumpC

Clk

Clear

Configuration register

BypassLVDS

BypassLVDS

Vcp

Vcp

Enable_clear

Clear

Hit16

Vdll0

Vcom_tuning

VcomVdll_tuning[0:7]

Sel_tuning

Sel_tuning

Sel_out_cp[0:7]

Sel_cp

Vcp_ext

Analog_visu

Sel_out_cp[0:7]

BypassLVDS

Enable_clear16

Sel_cp

Sel_out_cp8 / Sel_cp / BypassLVDS

Analog_visu / Vcp _ext / Vcom_hit

Vcom_tuning

Vdll_tuning8

Sel_tuning

Enable_clearEnable_dll

Dll_out[0:7]

Data_visu[0:5]

Hit_phy

Hit_F

Hit_C

Status

Hit_reg

Counter[0:47]

Adr_ch

C[0:4]

Error

Q_reg[0:47]

DLL_reg[0:31]

Data_visu6

Visu_counter[0:25]

Data_visu

[7:15]

Data_out

[0:15]

Enable

Sclk

Sdata_in

Sdata_out

Addr_ch[0:3]

Data_sel[0:1]

Word_sel[0:1]

X8DLL

DLL

1 Channel logic

Channel logic

X2

Test channel

8 blocks16 channels

4x16bits

Hit_reg[0:15]

DLL registers

5-bit gray encoder

Counter registers

48-bit gray counter

Synchronizer

Hit register

Data

selection

+

-

Adress

decoder

Hit[0:15]

Vcom_hit

+

-

Clk_LVDS+

Clk_LVDS-Clk

195ps 195ps 195ps 195ps

VCDL

Phase

detector

Charge

pumpCC

Clk

Clear

Configuration register

BypassLVDS

BypassLVDS

Vcp

Vcp

Enable_clear

Clear

Hit16

Vdll0

Vcom_tuning

VcomVdll_tuning[0:7]

Sel_tuning

Sel_tuning

Sel_out_cp[0:7]

Sel_cp

Vcp_ext

Analog_visu

Sel_out_cp[0:7]

BypassLVDS

Enable_clear16

Sel_cp

Sel_out_cp8 / Sel_cp / BypassLVDS

Analog_visu / Vcp _ext / Vcom_hit

Vcom_tuning

Vdll_tuning8

Sel_tuning

Enable_clearEnable_dll

Dll_out[0:7]

Data_visu[0:5]

Hit_phy

Hit_F

Hit_C

Status

Hit_reg

Counter[0:47]

Adr_ch

C[0:4]

Error

Q_reg[0:47]

DLL_reg[0:31]

Data_visu6

Visu_counter[0:25]

Data_visu

[7:15]

Data_out

[0:15]

Enable

Sclk

Sdata_in

Sdata_out

Addr_ch[0:3]

Data_sel[0:1]

Word_sel[0:1]

X8DLL

DLL

1 Channel logic

Channel logic

X2

Test channel

8 blocks16 channels

4x16bits

Hit_reg[0:15]

16 PMsSlow Shaper

PACTrack & Hold

Fast Shaper CFD

SNIFE (SuperNemo Integrated Front-end)

SNATS

ADC

12bits / 40MHz

FPGA

Cyclone 3

1616

Data

Readout

16 channel front-end board

Clock Multiplier

SI5325CLK

40MHz

160MHz

Control

9

6

Data acquisition

16 PMs16 PMsSlow ShaperSlow Shaper

PACPACTrack & HoldTrack & Hold

Fast ShaperFast Shaper CFDCFD

SNIFE (SuperNemo Integrated Front-end)

SNATS

ADC

12bits / 40MHz

ADC

12bits / 40MHz

FPGA

Cyclone 3

1616

Data

Readout

16 channel front-end board

Clock Multiplier

SI5325CLK

40MHz

160MHz

Control

9

6

Data acquisition

Resolution : 101ps (RMS)

INL (/ max): 0.514 / 1.8 LSB

8 dual channel blocks

16 coarse time registers

48-bit counter

100-pin ceramic CQFP

SNATS package