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Korea Winter Public ConferenceORTC 2011 ITRS
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1) Unchanged for 2010/11 MPU contacted M11) 2-year cycle trend through 2013; then 3-year trend to 20262) 60f2 SRAM 6t cell Design Factor
3) 175f2
Logic Gate 4t Design Factor4) Ongoing - evaluate alignment of nodes with latest M1 industrystatus and also High Performance/Low Power timing needs
2) Unchanged for 2010/11 Tables:MPU Functions/Chip and ChipSize Models
1) Design TWG Model for Chip Size and Density Model trends tied to
technology cycle timing trends and cell design factors2) ORTC line item OverHead (OH) area model, includes non-active area
3) Updated for 2010/11 Tables:MPU GLpr, GLphtrendssmoothed by PIDS modeling; but close to previoustargets
4) Updated for 2010/11 Tables: Vdd Low operating and standbyline items from PIDS model track smoothed gate lengthchanges
5) Added in 2011 Table ORTC-6 Battery Energy Storage(Watt-hours) Line Item from iNEMI Roadmap
2011 Renewal ITRS ORTC Technology Trend Pre-Summary
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6) Updated in ORTC 2011 Tables - DRAM contacted M1:1) 1-year pull-in of M1 and bits/chip trends;2) no Flattening of DRAM M1 as with Flash Poly**
3) 4f2 push out [to 2013];
7) Updated in ORTC 2011 Tables - Flash Un-contacted Poly:1) 2+-year pull-in of Poly; however slower 4-year cycle (0.5x per
8yrs) trend to 2020/10nm; then 3-year trend to 2022/8nm; then FlatPoly after 2022/8nm;
2) and 3bits/cell extended to 2018; 4bits/cell delay to 20228) Updated in ORTC 2011 Tables - DRAM Bits/Chip and Chip Size Model:
1) 3-year generation Moores Law bits/chip doubling cycle target (1-2yrdelay for smaller chip sizes
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10) Updated in ORTC 2011 Tables - ORTC Table 5 - Litho # of Mask CountsMPU, DRAM,
1) Flash Survey inputs Updated2) Also IC Knowledge (ICK) model contribution to extend mask levels range
11) Unchanged for 2011 - IRC 450mm Position:1) Timing Status
1) Consortia work underway2) IDM and Foundry Pilot lines: 2013-14;3) Production: 2015-16
2) SEMATECH/ISMI making good progress on 450mm program activities to meet the ITRS Timing
1) Consortium operations are using 450mm early test wafer process, metrology and patterning capability tosupport Supplier development2) 193 immersion multiple exposure litho tools are under development to support consortium and manufacturers
schedules3) 450mm increasing silicon demand is needed from consortium demonstrations to support development
3) Europe momentum building - EEMI status reviewed with IRC in Potsdam4) FI TWG will extend 300mm wafer generation in parallel line item header with 450mm;
1) Including Technology upgrade assumptions through end of roadmap2) Assuming compatibility of 300mm productivity extensions into the 450mm generation;
5) Utilizing a new ITRS-based ICK Strategic commercial model , SEMATECH has developed300mm and 450mm 2009-2024 Range Scenarios for silicon and equipment demand
12) Updated in 2011 - More than Moore white paper online at www.itrs.net1) New Moores Law and More Graphic update included in 2011 ITRS Executive Summary2) MtM Workshop completed in Potsdam, GE, in April and reviewed at Summer ITRS meeting3) New MEMS TWG and Chapter added to 2011 ITRS
2011 Renewal ITRS ORTC Technology Trend Pre-Summary (cont.)
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Technology Pacing Cross-TWG Study Group (CTSG) work preparationfor 2012 Update:
2011 Renewal ITRS ORTC Technology Trend Summary (cont.)
IRC Equivalent Scaling Graphic Update Included in 2011 Update: Parallel bulk and SOI pathways; and Clarification of gate mobility
materials pathway Proposals for pull-in placement of MuGFET [2012 Update work] and III/V Ge Timing [consider
in 2013 ITRS work] (one IDM or Foundry company may lead technology production ramp)
PIDS and FEP Memory Survey Proposal Updates Additional acceleration will be monitored
FEP and Design and System Drivers Logic Monitor Monitor MPU and Leading Edge Logic technology trends
A&P/Design Power Model Possible proposals for Power Dissipation "hot spot" model rather than chip area basis
PIDS/Design Max On-chip Frequency vs Intrinsic Modeling Included in 2011 Update: New Max Chip Frequency trends (reset to 3.6Ghz/2010
plus 4% CAGR trend) TBD PIDS Intrinsic Transistor and Ring Oscillator model Changes to 8% [from
unchanged 2011 13% trend] PIDS Updates include MASTAR static modeling near-term and TCAD dynamiclong-term modeling
Also equivalent scaling tradeoffs (FDSOI, MuGFET, III-V/Ge) with dimensionalscaling
YE Defect Density Modeling New ORTC Defect Density model work moved to 2012 Update due to loss of
modeling resources
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More than Moore: Diversification
MoreMoore:
Miniaturization
BaselineCMOS:CP
U,
Memory,
Logic
BiochipsSensors
ActuatorsHV
PowerAnalog/RF Passives
130nm
90nm
65nm
45nm
32nm
22nm
16 nm...V
InformationProcessing
Digital contentSystem-on-chip
(SoC)
Beyond CMOS
Interacting with people and environment
Non-digital contentSystem-in-package
(SiP)
Source: 2011 ITRS - Exec. Summary Fig. 4
Figure 4 The Concept of Moores Law and More
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More Poly Dense Lines added in 2010 ITRS Update[Note: The ITRS does not utilize any single-product node designation reference; FlashPoly and DRAM M1 half-pitch are still Lithography drivers; however, other product
technology trends may be drivers on individual TWG tables]
Source: 2011 ITRS - Exec. Summary Fig. 1
MetalPitch
Typical DRAM/MPU/ASIC
Metal Bit Line
DRAM Pitch= DRAM Metal Pitch/2
MPU/ASIC M1 Pitch= MPU/ASIC M1 Pitch/2
Typical flash
Un-contacted Poly
FLASH Poly Silicon Pitch= Flash Poly Pitch/2
32-64 Lines
Poly
Pitch
Exec. Summary - Figure 1 Definition of Half-Pitch
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8Months
0-24
Alpha
Tool
12 24-12
Development Production
Beta
Tool
Production
Tool
First
Conf.
Papers
Proposal: First 1-2Companies
Reaching
CombinedProduction
(work in Progress)2
20
200
2K
20K
200K
AdditionalLead-time:ERD/ERM
Research andPIDS Transfer
Volume(Wafers/Month)
Source: 2009 ITRS - Exec. Summary Fig. 2a
Figure 2a- (within an established wafer generation*)
- *see also Figure 2a for ERD/ERM Research and PIDS Transfer timing; and also- Figure 6 (450mm topic) for Typical Wafer Generation Pilot and Production Ramp Curves
Production Ramp-up Model and Technology/Cycle Timing
Proposal
For 2012Update Note:Fewer leadingIDM CompaniesRequiresAdaption ofDefinitionTo allow one
IDM CompanyOr a FoundryRepresentingMany FablessCompaniesTo Lead aTechnology
ProductionRamp Timing
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Months
Alpha
Tool
Development Production
Beta
Tool
Product
Tool
Volume(Wafers/Month)
2
20
200
2K
20K
200KResearch
-72 0 24-48 -24-96
Transfer toPIDS/FEP(96-72mo
Leadtime)
FirstTech. Conf.
Device PapersUp to ~12yrs
Prior to Product
20192017201520132011 2021Hi-m Channel
Example:
1st2 Cos
Reach
Product
FirstTech. Conf.
Circuits PapersUp to ~ 5yrs
Prior to Product
Hi-m Channel Proposal - for 2013 ITRS work
Source: 2011 ITRS - Exec. Summary Fig. 2b; plus:
Figure 2b A Typical Technology Production Ramp Curve forERD/ERM Research and PIDS Transfer timing- including an example for III/V Hi-Mobility Channel Technology Timing Scenario- Acceleration to 2015 Scenario for the 2012 Update work
[http://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-option]
http://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-optionhttp://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-option -
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2012 ITRS Update* 450mm Production Ramp-up Model[2011 ITRS Executive Summary Fig. 6 -A Typical Wafer Generation Pilot Line and Production Ramp Curve]
Source: 2011 ITRS - Executive Summary Fig. 6
*Note: the IRC recommended updating the ITRS 450mm Timing Graphic for use in the 2011 ITRS Special Topic and 2012 UpdateRoadmap guidance; based on SEMATECH guidance
Volu
me
Years
Alpha
Tool
Beta
Tool
Silicon is supporting developmentusing partially-patterned andprocessed test wafers ------ IDM & Foundry ------
Pilot Lines
Manufacturing
Demonstrationsfocus on1xnm M1 half-pitchcapable tools
Development Production
Increasing450mm Silicon Demand
From DemonstrationsBeta
Tool
Production
Tool
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1
10
100
1000
1995 2000 2005 2010 2015 2020 2025 2030
Nanometers(1
e-9)
Year of Production
2011 ITRS - Technology Trends
2011 ITRS Flash Pitch (nm) (un-contacted Poly) -[2-yr cycle to 2009; then 8-yr cycle to 2020; then 3-yr cycle to 2022/8nm; then flat]
2011 ITRS DRAM Pitch (nm) (Contacted M1) -[2.5-yr cycle to 2008; 45nm pull-in to 2009; then 3-yrcyc le to 2026]
2011 ITRS: 2011-2026
3D - 8 layers
3D - 128 layers
PIDS 3DFlash :Looser Poly
half-pitch2016-18/32;
Then2019-21/28;
Then2022-25/24
Then2025-26/18nm
~5.5-yr
Cycle
Long-Term 19-26
16nm
2011 ITRS Figure 11ORTC Table 1 Graphical Trends Memory Half Pitch[With 2011 Flash 3D Scenario Overlay]
Source: 2011 ITRS - Executive Summary Fig 3
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1
10
100
1000
1995 2000 2005 2010 2015 2020 2025 2030
Nanometers(1e-9)
Year of Production
2011 ITRS - Technology Trends
2009/10/11 ITRS MPU/ASIC Metal 1 (M1) Pitch (nm)[historical trailing at 2-yr cycle; extended to 2013; then 3-yr cycle]
2009/10/11 ITRS MPU Printed Gate Length (GLpr) (nm)[3-yr cycle from 2011/35.3nm]
2009/10/11 ITRS MPU Physical Gate Length (nm) [begin
3.8-yr cyc le from 2009/29.0nm]
2011 ITRS: 2011-2026
Long-Term 19-26
16nm
2011 ITRS Figure 4ORTC Table 1 Graphical TrendsLogic (MPU and high-performance ASIC) Half Pitch and Gate Length
Source: 2011 ITRS - Executive Summary Fig 4
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2011 ITRS Figure 5 Equivalent Scaling Roadmap for Logic (MPU and high performance ASIC)Figure 5 ORTC Table 1 Graphical Trends (including overlay of 2009 industry logic nodes and ITRS trends
for comparison); also including proposals for MugFET and III/V Ge accelerationfor 2012 ITRS Update work
Metal
High kGate-stack
material
2009 2012 2015 2018 2021
Bulk
FDSOI
Multi-gate
(on bulk or SOI)Structure
(electrostatic
control)
Channel
material
Metal
High k
2nd generation
Si + Stress
S D
High-
InGaAs; Ge
S D
PDSOI
Metal
High k
nth generation
PossibleDelay
PossiblePull -in
13
68nm 45nm 32nm 22nm 16nm2011 ITRS DRAM M1 :
2011 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm 19nm 13nm
MPU/hpASIC Node: 45nm 32nm 22nm 16nm 11nm 8nm
2011 ITRS hi-perf GLph : 32nm 29nm 29nm 27nm 24nm 22nm 20nm 15nm 12nm
2011 ITRS hi-perf GLpr : 54nm 47nm 47nm 41nm 35nm 31nm 28nm 20nm 14nm
45nm 32nm 11nm2011 ITRS Flash Poly : 54nm
2011 ITWG Table Timing: 2007 2010 2013 2016 2019 2021
Proposals - for 2012 Update work
22-248nm
20248nm
22nm15nm
11nm
Source: 2011 ITRS - Executive Summary Fig 5
Proposal - for 2013 ITRS work
2011 ITRS Figure 4 ORTC Table 1 Graphical Trends
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1
10
100
1000
1995 2000 2005 2010 2015 2020 2025 2030
Nanometers(1e-9)
Year of Production
2011 ITRS - Technology Trends
2009/10/11 ITRS MPU/ASIC Metal 1 (M1) Pitch (nm)[historical trailing at 2-yr cycle; extended to 2013; then 3-yr cycle]
2009/10/11 ITRS MPU Printed Gate Length (GLpr) (nm)[3-yr cycle from 2011/35.3nm]
2009/10/11 ITRS MPU Physical Gate Length (nm) [begin
3.8-yr cyc le from 2009/29.0nm]
2011 ITRS: 2011-2026
Long-Term 19-26
16nm
2011 ITRS Figure 4ORTC Table 1 Graphical TrendsLogic (MPU and high-performance ASIC) Half Pitch and Gate Length
Source: 2011 ITRS - Executive Summary Fig 4
2009/2010 ITRS Unchanged (except extend to new end period): 2011 ITRS:2011-2026; also ncludes 2012 Update Equivalent Scaling Proposals
Equiv.Scaling
Trade-off
Strain
HK/MG
MuG-FET
Hi-u,(tbd)
ITRS 1999
P. GarginiEquivalent
ScalingConcept
FDSOI
PDSOI
2011
ITRS:ExtendM1;
& GLpr;to 2026
on3-yearCycle
1995->2015Nodes
360-11(10)
ITRS M1 hp303-21nm
ITRS GLph95-99-03-15360nm-90nm
90nm-45nm45nm-17nm
Gate Length+
EquivalentScaling
=Power &
Performance
Half-Pitch+
Design
FactorScaling
[6t SRAM =60f2;
4t Logic =175f2]
EnablesMoores
Law
Functions/chip
Also III/V; Ge from 2019-> 2015?
Proposal for 2013 ITRSWork
MugFET from 2015 -> 2011;Proposal for 2012 ITRS
Work
Updated Equivalent
Scaling Proposal
- for 2012 work
2011 ORTC Figure 6
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1.00E-06
1.00E-05
1.00E-04
1.00E-03
1.00E-02
1.00E-01
1.00E+00
1.00E+01
1.00E+02
1.00E+03
1.00E+04
1995 2000 2005 2010 2015 2020 2025 2030
SquareMillim
eters
Year of Production
2011 ITRS - Function Size
2009 DRAM Cell area per bit (1 bits/cell) (um2)
2009 Flash SLC area per bit (1 bits/cell) [SLC cell area/1] (um2)
2009 Flash MLC Ave area per bit (2 bits/cell) [SLC cell area/2] (um2)2009 Flash MLC Ave area per bit (3 bits/cell) [SLC cell area/3] (um2)
2009 Flash MLC Ave area per bit (4 bits/cell) [SLC cell area/4] (um2)
2011 SRAM Cell (6-transistor) Area (um2)
2011 Logic Gate (4-transistor) Area (um2)
Long-Term 19-26
2011 ITRS: 2011-2026
2011 ORTC Figure 6Product Function
Size Trends
[transistor + capacitor]
Source: 2011 ITRS - Executive Summary Fig 6
PIDS NAND Fl h
Pl Sh ll Di i l2011 ORTC Figure 6
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1.00E-06
1.00E-05
1.00E-04
1.00E-03
1.00E-02
1.00E-01
1.00E+00
1.00E+01
1.00E+02
1.00E+03
1.00E+04
1995 2000 2005 2010 2015 2020 2025 2030
SquareMillim
eters
Year of Production
2011 ITRS - Function Size
2009 DRAM Cell area per bit (1 bits/cell) (um2)
2009 Flash SLC area per bit (1 bits/cell) [SLC cell area/1] (um2)
2009 Flash MLC Ave area per bit (2 bits/cell) [SLC cell area/2] (um2)2009 Flash MLC Ave area per bit (3 bits/cell) [SLC cell area/3] (um2)
2009 Flash MLC Ave area per bit (4 bits/cell) [SLC cell area/4] (um2)
2011 SRAM Cell (6-transistor) Area (um2)
2011 Logic Gate (4-transistor) Area (um2)
Long-Term 19-26
2011 ITRS: 2011-2026
3D - 8 layers/16
3D - 128 layers/ 25
2016/32nm
0.0039 um2
2025/18nm0.000965 um2
2016-202532nm-18nm
= -6.193% CARRDimensional
= -12.00%CARR Area= 0.8800x/yr
0.5/5.5yrs =0.3165/9years
3D Equiv.2016-2025
1 - 128layers 41.674% CARR
Area= 0.5833x/yr
x0.8800/yr= 0.5133x/year
2016/32nm0.00048 um2
2025/32nm0.0030 um2
MPU/ASIC
AlignmentDesign TWGActual SRAM [60f2]
& Logic Gate [175f2]
DRAM4f2
AddedWAS:Begin in
2011IS: Delayed
To 2013
Flash [4f2]1) 2-yr CycleExtended to 2010;2) 3 bits/cell added2009-2011[and
extended to 2020in the 2011 ITRS];3) 4 bits/cell movedfrom 2012 [to 2021in the 2011 ITRS]
PIDS NAND FlashMulti-Layer 3D Model
Plus Shallow Dimensional
Reduction Rate Trend
2011 ORTC Figure 6Product* FunctionSize Trends; plus
[transistor + capacitor]
Source: 2011 ITRS - Executive Summary Fig 6
Fi 7 2011 ITRS P d t T h l T d
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0.01
0.10
1.00
10.00
100.00
1000.00
10000.00
1995 2000 2005 2010 2015 2020 2025 2030
Gigabits(1e9)andSquareMillimeters
Year of Production
2009 ITRS - Functions/chip and Chip Size
2011 ITRS DRAM Functions per chip (Gbits)
2011 ITRS Flash (Gbits) SLC [2-year cycle]
2011 ITRS Functions per chip (Gbits) MLC (2 bits/cell)
2011 ITRS Functions per chip (Gbits) MLC (3 bits/cell)
2011 Functions per chip (Gbits) MLC (4 bits/cell)
2011 Flash Chip size at production (mm2)
2011 DRAM Chip size at production (mm2)
Flash"Hwang's
Law"~ 2x/1yr
Flash~ 2x/3yrs
Flash MLCExceeds1Tera-bit
Average "Moore'sLaw" = 2x/2yrs
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18
10
100
1000
10000
100000
1000000
10000000
1995 2000 2005 2010 2015 2020 2025 2030
Million
Transistors(1e6)andSqua
reMillimeters
Year of Production
2011 ITRS - Functions/chip and Chip Size
2011 ITRS Cost-Performance MPU Functions perchip at production (Mtransistorst)
2011 ITRS High-Performance MPU Functions perchip at production (Mtransistors)
2011 Cost-Performance MPU Chip s ize at
production (mm2)
2011 High-Performance MPU Chip s ize atproduction (mm2)
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ORTC Table 5 Update: Litho TWG model for Mask Count
MPU survey-based, mask counts peak 2014/(54 masks peak) EUV
expected 2015
DRAM referenced to MPU, mask counts peak 2012/(41 masks peak)EUV expected 2013
Flash survey-based, mask counts peak 2012/(43 masks peak) EUVexpected 2013
Sidewall image transfer technology IEDM papers should be evaluated
Table 5 also includes NEW IC Knowledge (ICK)www.icknowledge.com modeled comparison targeting ITRS 2011Litho EUV timing; but extended out through 2024 using 2009-10 ITRS(www.itrs.net ) assumptions
Limited YE Defect Density modeling resources requires delay ofupdate response to 2012 ITRS Update work
19
Fig 7a Litho 2011 Survey vs ICK 2011 ITRS based* Model
http://www.icknowledge.com/http://www.itrs.net/http://www.itrs.net/http://www.icknowledge.com/ -
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Fig 7a - Litho 2011 Survey vs ICK 2011 ITRS-based* Model[*extended to 2024 based on 2009-24 ITRS www.itrs.net]
20
30
40
50
60
70
80
1995 2000 2005 2010 2015 2020 2025
DRAM
Flash
MPU
SEMATECHSurvey
EUV timing:MPU
in 2015;
DRAM& Flash in
2013
LithoMaskCountb
yProductCategory
Actual < - > Forecast
Source: 2011 ITRS - Executive Summary Fig. 7a
450mm2015-2016
Fig 7b Litho 2011 Survey vs ICK 2011 ITRS based* Model ( t )
http://www.itrs.net/http://www.itrs.net/ -
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Fig. 7b - Litho 2011 Survey vs ICK 2011 ITRS-based Model (cont.)[*extended to 2024 based on 2009-24 ITRS www.itrs.net]
20
30
40
50
60
70
80
1995 2000 2005 2010 2015 2020 2025
DRAM
Flash
MPU
ICK StrategicModel*
*Based onITRS
2009-10 editions
EUV timing:MPU
in 2015;
DRAM &Flash EUV in
2013
FlashCharge Trap
in 2012;Multi-layer 3D
begins2016
MPUDelay EUV to
2017
LithoM
askCountbyP
roductCatego
ry
Actual < - > Forecast
Source: 2011 ITRS - Executive Summary Fig. 7b
450mm2015-2016
http://www.itrs.net/http://www.itrs.net/ -
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ORTC Table 4: Design TWG Model for On-Chip Frequency
Lower model starting point 2010/3.6Ghz
4% growth rate through 2026
*Unchanged 2011 ITRS 13% PIDS targetmodel Intrinsic Transistor Frequency Growth;
*However, proposal for 2012 ITRS 8% PIDStarget model Intrinsic Transistor Growth(work preparation in 2011)
22
Table ORTC-4 Performance and Packaged Chips
Trends
Year of Production 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026
Chip Frequency (MHz)
WAS On-chip local clock [2] 5.454 5.875 6.329 6.817 7.344 7.911 8.522 9.180 9.889 10.652 11.475 12.361 13.315 14.343 15.451 16.640Design
/ISOn-chip local clock [2] 3.462 3.600 3.744 3.894 4.050 4.211 4.380 4.555 4.737 4.927 5.124 5.329 5.542 5.764 5.994 6.234 6.483 6.743
Ghz
Table FreqTopic tbd -2011 Chip Frequency Model Trend vs.2009/2010 ITRS Frequency
Source: 2011 ITRS - Executive Summary Table tbd
Fig 8a - PIDS 2009/11 ITRS CV/I Trends vs. 2012 ITRS MUG-FET 4-year Pull-In and Lower Intrinsic Freq. Trend Proposals
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Fig 8a PIDS 2009/11 ITRS CV/I Trends vs. 2012 ITRS MUG FET 4 year Pull In and Lower Intrinsic Freq. Trend Proposals
0.10
1.00
2000
2005
2010
2015
2020
2025
2030
Extended Planar Bulk
UTB FDSOI
Multiple Gate 2010 ITRS;
2011 ITRS Unchanged
Multiple Gate Pull-in
Scenario - 2012 ITRSCV/I(ps)
Year of Production Ramp
PIDS Table 2: CV/I 2009-2011 ITRS Unchanged
100
1000
2000
2005
2010
2015
2020
2025
2030
Extended Planar Bulk
UTB FDSOI
Multiple Gate 2010 ITRS;
2011 ITRS Unchanged
Multiple Gate Pull-in
Scenario - 2012 ITRS
1/(CV/I)(Ghz)
Year of Production Ramp
Note: 1/(CV/I) frequency is reduced by a factor of 1/22.4in a PIDS model of a Ring Oscillator (inverter chain) 101stages; 1001 stages, etc.;FO 1 (capacitance example .1pf);FO 4 (capacitance example .4pf)
Note: 1/(CV/I) frequency is reduced by a factor of 1/22.4in a PIDS model of a Ring Oscillator (inverter chain) 101stages; 1001 stages, etc.;FO 1 (capacitance example .1pf);FO 4 (capacitance example .4pf)
1/(CV/I) (Ghz) ~~ 13%CAGR
PIDS 2012FDSOI Scenario:15/294 26/[email protected]% CAGR
2011 ITRS2011 - 2026
PIDS 2011 ITRS Table:1/(CV/I) (Ghz) =11/156 26/1000@ ~ 13% CAGR
11/ 313 26/686 @ 5.4%CAGR MugFET Trend
[2012 Proposal: MugFET4-year Leading Co.pull-in]
PIDS 2011 ITRS Table:CV/I) (ps) =11/0.64 26/0.10@ ~ -12% CAGR
11/ 0.319 26/0.146 @- 4.8% CAGR MugFETTrend
[2012 Proposal: MugFET4-year Leading Co.pull-in]
CV/I (ps) ~~ -12%CAGR
PIDS 2012 FDSOIScenario:15/0.340 - 26/0.146-7.4% CAGR
Figure 8a 2012 Update Model Trend versus 2009/2011 ITRS PIDS TWG Transistor Intrinsic Frequency (1/(CV/I)) Performance Trends
Source: 2011 ITRS - Executive Summary Fig. 8a
Fig. 8b - ORTC Table 4:On Chip Local Clock Frequency Trend Comparisons to PIDS
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Fig. 8b ORTC Table 4:On Chip Local Clock Frequency Trend Comparisons to PIDS
vs. 2012 ITRS MUG-FET 4-year Pull-In and Lower Intrinsic Freq. Trend Proposals
Figure 8b Design On-Chip Frequency vs. PIDS Intrinsic Transistor and Ring Oscillator Model Frequency
2011 ITRS2011 - 2026
0.1
1
10
100
1995 2000 2005 2010 2015 2020 2025
Intel ActualAMD Actual
IBM Actual
2005 ITRS (18%)
2007 ITRS (8%)
2011 ITRS (4%)
Source: ITRS Test TWG compilation, ca 4Q 2010; 2011 ITRS PIDS, Design TWGs
2012 Update Scenario:FDSOI
at 8% CAGR
ORTC Table 4:On-Chip Local Clock Frequency:
2011 Design TWG trend:at 4% CAGR
2009/11 PIDS/FEPRing Oscillator Model
101 invertor stagesWith equivalent Fan-out 4
Capacitance load;Results in Frequency of
~ 1/22 x 1/(CV/I)
at ~13% CAGR
DesignHroom
~ 1/22
2009/11 ITRS PIDS/FEPIntrinsic Transistor Frequency
1/(CV/I) at 13% CAGR
2007 Des TWGActual History of
Average On-Chip1999 - 2007
1Ghz 4.9Ghz~22% CAGR
On-Chip Clock Frequency:Performance Improvement tradeoffsbetween dimensional EOT and Gate Lengthwith Equivalent Scaling, both process-related(ie Strain, FDSOI, MugFET, III/V Ge, etc);and also Including design-related tradeoffs:
-Multi-Core Architecture
-Memory Architecture-Software Power Management-etc.]
1Thz
2012 Update Scenario: MugFET :4yr Pull-in 1/(CV/I) to 2011; then 5% CAGR
2012 Update Scenario:MugFET
at 5% CAGR
2012 Update Scenario FDSOI:Beginning 2015 at 8% CAGR
Co.A Actual
Co.B Actual
Co.C Actual
Source: 2011 ITRS - Executive Summary Fig 8b