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Lecture 12
Time/space trade offs Adders
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Time vs. speed: Linear chain
8-input OR function with 2-input gates
Gates: 7Max delay: 7
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Time vs. speed: Tree
Gates:7
Max delay: 3
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Modified circuit
Calculate the OR of the first 2 inputs, the OR of the first 3, and so on, up to the OR of all 8
Gates: 7Max delay: 7
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0-1
0-3
0-2 0-4
0-5
0-7
0-6
Parallel version
Gates: 12
Max delay: 3
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Binary half adder
1-bit half adder Computes sum, carry-out
No carry-in Sum = A'B + AB' = A xor B Cout = AB
A B S Cout
0 0 0 00 1 1 01 0 1 01 1 0 1
AB Cout
SumHalfAdder
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Binary full adder
1-bit full adder Computes sum, carry-out
Carry-in allows cascaded adders
Sum = Cin xor A xor B Cout = ACin + BCin + AB
A B Cin S Cout
0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
AB
CinCoutSumFull
Adder
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Full adder: Using 2 half adders
Multilevel logic Slower Fewer gates: 5 vs. 6
2 XORs, 2 ANDs, 1 OR
Sum = (A B) CinCout = ACin + BCin + AB
= (A B)Cin + AB
A B Cin S Cout Cout
0 0 0 0 0 00 0 1 1 0 00 1 0 1 0 00 1 1 0 1 11 0 0 1 0 01 0 1 0 1 11 1 0 0 1 11 1 1 1 1 1
Distributive law?
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Full adder: Using 2 half adders
Ci+1Ci
Ai
Bi
Ai
BiSi
40
OR237
AND2
39
AND2
36
XOR
38
XOR
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4-bit ripple-carry adder
A B
Cout
Sum
Cin
0 1
0 = Add1 = Subtract
A0 B0 B0'
Sel
Overflow
A B
Cout
Sum
Cin
A1 B1 B1'
Sel
A B
Cout
Sum
Cin
A2 B2 B2'
Sel 0 1 0 10 1
A B
Cout
Sum
Cin
A3 B3 B3'
Sel
S3 S2 S1 S0
Also subtracts! Twos complement: A – B = A + (–B) = A +
B' + 1
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Problem: Ripple-carry delay
Carry propagation limits adder speed
0111+ 0001
---------????0110
111
010000001000
A0B0
C0
S0
A1B1
C1
S1
A2B2
C2
S2
A3B3
C3
S3Cout
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Ripple-carry delay
CinSum
BA
33
XOR32
XOR
A
B
Cin
ACout
Cin
B
13
AND2
12
AND2
14
OR3
11
AND2
@0
@0
Cout takes two gate delays
@0
@2N
@0
@2N
@0
@0
@2N@2N+1
Except when N=0
@2N+2
Cin arrives late
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Ripple-carry delay
A0B0
C0
S0 @2
A1B1
C1 @2
S1 @3
A2B2
C2 @4
S2 @5
A3B3
C3 @6
S3 @7Cout @8
CinSum
B
A
33
XOR32
XOR
A
B
Cin
ACout
Cin
B
13
AND2
12
AND2
14
OR3
11
AND2
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Can we be more clever?
Let’s compute all the carries in parallel Derive carries from the data
inputs Not from intermediate carries Use two-level logic
Compute all sums in parallel
How do we do that???
A0B0
Cin
S0
A1B1
C1
S1
A2B2
C2
S2
A3B3
C3
S3
C4 C4
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Call this PROPAGATECall this GENERATE
Speeding up the adder
Need to find a way to “predict” Cout for all bits without knowing what Cin is
0+ 1
--------Predict Cout
1+ 1
--------Predict Cout
0+ 0
--------Predict Cout
Cout is always 0Cout is 0 if Cin is 0Cout is 1 if Cin is 1
Cout is always 1 1+ 0
--------Predict Cout
Cout is 0 if Cin is 0Cout is 1 if Cin is 1
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Lookahead logic: Pi and Gi
Step 1: Getting Pi and Gi Carry generate: Gi = AiBi
Generate carry when A = B = 1 Carry propagate: Pi = Ai xor Bi
Propagate carry-in to carry-out when (A xor B) = 1
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Lookahead logic: Sum and carry
Step 2: Calculate Sum and Cout Si = Ai xor Bi xor Ci = Pi xor Ci
Ci+1 = AiBi + Ci(Ai xor Bi) = Gi + CiPi
Gi
Pi
Ci+1Ci
Ai
Bi
Ai
BiSi
40
OR237
AND2
39
AND2
36
XOR
38
XOR
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Lookahead logic: Carries
Step 3: Express all carries in terms of C0, G, and P Derive intermediate results directly from inputs
rather than from carries Allows "sum" computations to proceed in parallel
C1 = G0 + P0C0
C2 = G1 + P1C1 = G1 + P1G0 + P1P0C0
C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0
C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0
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Lookahead logic: Carries
C1C0P0G0
C0P0
G0P1
P1
G1
C2
C0P0
G0P1
P1
G1P2
P2
P2
G2
C3
G3
C0P0
G0P1
P1
G1P2
P2
P2
G2P3
P3
P3
P3
C4
Logic complexity increases with
adder size
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Lookahead logic: Sum
Pi @ 1 gate delay
Ci Si @ 2 gate delays
BiAi
Gi @ 1 gate delay
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Lookahead logic timing
A0B0
C0
S0 @2
A1B1
C1 @2
S1 @3
A2B2
C2 @4
S2 @5
A3B3
C3 @6
S3 @7C4@8
C2 = G1 + P1C1
C3 = G2 + P2C2
@1
P0G0
P1G1
P2G2
P3G3
C4 = G3 + P3C3
= G1 + P1G0 + P1P0C0
@2
= G2 + P2G1 + P2P1G0 + P2P1P0C0
= G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0
C1 = G0 + P0C0
@3
@3
@3
@3
@4
@4
@4
@0
@3
@4
Pi @ 1 gate delay
Ci Si @ 2 gate delays
BiAi
Gi @ 1 gate delay
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Summary: Lookahead logic
Compute all the carries in parallel Derive carries from data inputs
not from intermediate carries Compute all sums in parallel
using two-level logic Cascade simple adders to
make large adders Speed improvement Complex combinational logic
A0B0
Cin
S0 @2
A1B1
C1 @3
S1 @4
A2B2
C2 @3
S2 @4
A3B3
C3 @3
S3 @4
C4 @3 C4 @3