dofes w13 revision

7/31/2019 DofES W13 Revision

1/92

Revision

Design of Electronic SystemsELEE1129

MSc Electronics & Communications Engineering

MSc Electrical & Electronic Engineering

MSc Electrical Power Engineering

Term 1 Week 13

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Topics Super Capacitors

Alternative Energy Sources (Solar Cell)

Fuel Cells

Batteries

Primar Batteries

Secondary Batteries

EMC

Compliance

Design Low Power Systems

Power saving methods

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SuperCapacitorsEssentially a chemical version of a capacitor, butwith much higher capacitance values.

3

Charge accumulates on the metalplates, separated by an insulator


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Discharging Curve for a Capacitor

vc(t)

vC(t)

t=0

RC

4

0 t5

t

CC evtv

= )0()(


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Super Capacitor

Linear Discharge Approximation

Calculation

(i) Using linear approximation

Use Average Current

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(ii) Check using stored Energy

( CV2)


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Capacitor StackSupercapacitor maximum working voltage ~2.3V, so often create

stack to realise total capacitance(example in Assignment 1 feedback)

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Solar Cell Comprised of a semi-conductor such a Silicon.

Light, in the form of photons, hitting the atoms, knock free electrons.

Adding electrical contact to the silicon creates a complete circuit.

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Semi-Conductor Materials UsedCrystalline Silicon ( =20-25%)

Large Single Crystal. Most efficient /Most expensive.

Polycrystalline Silicon (( = 15-20%)

Molten Silicon is poured into moulds to form thin layers

Amorphous Silicon (( = 8-12%)

Suited to mass production / Cheapest / Least efficient

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Power from Solar CellsSingle Cell 0.5V For higher voltages add cells in series

As the temperature increased the voltage decreases:

20C then cell voltage = 0.50V55C then cell voltage = 0.43V

Typical operating temperature in full sunshine is 55C.Therefore:

T = 85% @ 55C

T temperature in Centigrade.

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CurrentMaximum sunlight power (anywhere): P = 1.0 1.4 kWm-2

If crystalline cell of radius R = 5.0cm.

Area of cell = R2

Silicon Efficiency s = 25%

= 2

11

s

= 0.25 x 0.85 x 1000 x 3.14 x 25x10-4

= 1.67W

Assuming cell voltage is 0.43V (@55C) then cell current is 3.87 A.

Current is approximately proportional to light intensity.


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Fuel Cell

Every fuel cell has an electrolyte, which carries

electrically charged particles from one electrode tothe other, and a catalyst, which accelerates the

reactions at the electrodes.

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Alkaline Fuel Cell

Similar chemicalreaction to a

battery, chemical

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reaction releaseselectrons at the

electrodes


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Operation

Potassium Hydroxide in water produces ions.

KOH K+ + OH-

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,

O2 + 2H2O + 4e- 4 OH-

At the negative electrode with hydrogen:

2H2 + 4 OH- 4H2O + 4e

-


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Approximate energy distribution

60% emitted as heat vaporising the water

40% available as electricity

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Vnominal = 1.0V Energy density = 100 Whkg-1

(although efficiencies can be much higher)


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Typical Fuel Cell Characteristic

1.0Region of Activation Polarization

(Reaction Rate Loss)

Ideal Voltage

ge

Power Density

Increasing Efficiency Increasing Power

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0.5

Region of Ohmic Polarization

(Resistance Loss)Region of Concentration

Polarization

(Gas Transport Loss)

Operating

VoltageCellVo

lt

Current Density (mA/cm2)


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Batteries

Capacity Energy Stored

Energy (J) = Power (W) x Time (Seconds)

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= x x

Assume constant voltage

E = V x (Amp-Hours)

Quote Current Capacity in Ah equivalent to energy!


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Batteries Internal ResistanceA battery has a 24 V output on open circuit, which drops to 21.5

V with a load current of 2.5 A. Determine the internal resistance?

R = (Voc-Vload)/I = (24V-21.5V)/2.5A = 1 Ohm

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A discharged storage battery of six identical cells connectedtogether in series, has an open circuit voltage of 1.9 V per cell.

Each cell has an internal resistance of 0.05 . What is the

minimum voltage of a charging system that will produce an initial

charging current of 10 A?

Total Voc = 6x1.9 = 11.4V.

Voltage drop across 6x0.05 . x 10A = 3V,

Minimum Charging voltage =11.4V+3V = 14.4Vmin


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Batteries CapacityA car starter motor takes 65 A from a 12 V battery.

(a) If the starter motor operates for 5.0 s, what energy has

been used?

E = VI t = 12*65*5 = 3900J

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(b) The generator in the car delivers a maximum of 4.0 A.How long will it take to re-place the lost energy? Assume

there are no losses.

T = E/P = 3900 /(4*12) = 81.25 s


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Battery Capacity - Discharge

Time

dtCC =

22

tVIC =


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Battery Capacity

Linear DischargeIf a 2Ah battery discharges linearly from 12V to 9V, how long

can it supply a circuit that requires a 10V to 14V supply and

draws 50mA?

The battery can supply 50 mA for 2Ah/50mA = 40h

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However the circuit ceases to operate when the voltage falls

below 10V. The time taken for this is given by

T = 40h * (12V-10V) / (12V-9V) =26.67h


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Typical Carbon-Zinc Discharge Curve

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Union Carbide D-Size Starting Current of 667mA


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Typical Alkaline Manganese Discharge

Curve

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Mallory Duracell 1.5 PX825 (300mAh


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Typical Button Cells Silver Oxide -Zinc Based 1.55V

Alkaline Based 1.5V

Lithium Based 3V

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Silver-Oxide offers high

energy density and flat

discharge ideal for small

size battery applications(Hearing Aids)

1.8

1.0

1.4

V

625

2.56mA

Duration of Discharge (hrs)

0 50 100

Union Carbide S41

1000

1.6mA


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Comparison of Primary CellsTest Load

()

Duty Cycle Carbon-

Zinc

Zinc

Chloride

Alkaline

Motor

Toy

2.2 Continuous

to 8V

100% 300% 1100%

Cassette 10 4hrs/day to 100% 250% 570%

27

0.9V

Flashlight 2.2 4min/hr

8hr/day to

0.9V

100% 200% 460%

Radio 24 4hr/day to

0.9V

100% 180% 405%

Ratio typically 2:3:5 depends on load and usage


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Discharge and Charge Characteristics

(Lead Acid Cell)

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Lead Acid Battery

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Chemical Reactions Sulphuric acid ionises in water

H2SO4 2H+

+ SO4--

The SO4-- ions combine with both electrodes.

Pb + SO4-- PbSO4 + 2e

-

with the electrons being deposited on the negative

electrode.

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Lead-Acid Discharge Curve

32I20 = 1/20th

Capacity current

Crompton-ParkinsonSealed Lead-acid cells


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NiCd Discharge CurveEveready

Cylindrical

6V, 0.5Ah

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Lithium Ion Discharge A relatively flat discharge voltage allows the production of a

stable power throughout the discharge period of the battery

Cell voltage

4.0

3.5

3.0

Capacity 80% 100% 34


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Secondary Battery SummaryType Nominal voltage

(Volts)Imax(peak

Best)

Energy density(Wh/Kg)

Lead Acid 2 5C0.2C

30-50

NiCD 1.2 5C 40-60

.

NiMH 1.2 5C

0.5C

60-80

Lithium Ion 3.6 2C

1C or lower

110-160

Lithium Poly 3.6 2C

1C or lower

100-130

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Comparisons

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Low Power Systems Digital semiconductor technologies

TTL

ECL

CMOS

ower osses n

Leakage

Sub-threshold

Switching

Short circuit

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CMOS Inverter By placing an N type MOSFET in series with a P type MOSFET,

a CMOS Switch is created.

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CMOS Inverter By placing an N type MOSFET in series with a P type MOSFET,

a CMOS Switch is created.

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DC Losses 1: Leakage Currents Reverse bias parasitic diode current

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DC Losses 2:

Sub-threshold leakage current Although the depletion layer is modelled to

only be present at gate voltages above thethreshold, it starts to appear at any voltageover zero.

This causes a sub-threshold current to flowand is equivalent to a resistance, Roff.

Power dissipation due to Sub-threshold

leakagePsub = n V

2/Roff

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AC Losses 1: Switching Current

The Gate construction is effectively a small

capacitor. Typically 0.1pF

A typical gate capacitance, C, is 0.1 pF. The power consumed when a sine wave is

applied can be approximated with

Pswitch = A n f C V2

Where

A fraction of transistor switching

(a typical value is 0.1)

f Equivalent frequency of switching.n number of transistor switches.

C equivalent gate capacitance.

V Supply voltage

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AC Losses 2: Short Circuit Current

For non-ideal CMOS switches, turn on and turn off do

not occur instantaneously so a pulse of current can occur when

both FETs are partially on.The following empirical formula is used to calculate short

circuit power loss (Pshort).

Pshort = [An (Vcc - 2Vth)3 ton]/12 tp

Where

gain factor

Vcc supply voltage

Vth threshold voltage

ton turn on timetp period of pulse t

Off

Switch state

On

ton

toff

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t

Rsupply

Mid-point of

switching

Supply

current

t


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Summary Power losses Four types of power loss in a CMOS switch

DC effects:- reverse bias current leakage occurring between the p-type an n-type

diffused regions and the device substrate.

ny npu vo age a ove zero can su - res o curren ea age

between the source and drain of the switch.

AC effects dependent on the switching frequency:- The gate construction gives rise to capacitance between the gate and

the semiconductor material.

Short Circuit, during the output transition from low to high or high to

low both devices are on at once

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Power Saving Methods

The Best power saving choices are designed in from the

beginning.

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System Design

Reduce system complexity and size

Psys proportional to N Fsys VDD2

Psys = System Power

=ran

Fsys = Clock FrequencyVDD = supply voltage

What other factors?

IP , memory management, Floating point arithmetic

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Tutorial 2 This program is executed by amicroprocessor with an FPU.

The FPU contains 300,000

transistor.

The microprocessor contains200,000 transistors, has a 5.0V

while (1){

if(input0==1)portB=input0/5.6;

elsertB=in t * .

supply and operates with a10MHz clock.

Assume the microprocessor willoperate down to 3.3V and 1MHz.What is the maximum powerreduction possible?

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if(input1==1)portA=input1/10.3;else

portA=input1*9.4;

}


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Tutorial 2 (Solution) Reduce the supply voltage to 3.3V

Reduce Clock Frequency to 1MHz Rewrite program to remove need for FPU

Assuming:

Psys proportional to N (no. Of transistors)

Psys proportional to FsysPsys proportional to VDD

2

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Tutorial 2 (Solution)Then

Psys proportional to N Fsys VDD2

.

Reduction Factor = 0.017

Power reduced to 1.7% of origional!

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Architecture DesignTo implement some of the system design power savings, architecturedesign decision have to be made.

Reducing the Supply Voltage

we already know that:

sys sys

Psys System powerVsys System voltage

However, when Vsys is reduced, switching propagation delays increase andhence maximum system frequency decreases.

Fsys VsysThis leads to a reduction in system performance.

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Voltage Islands

To achieve

maximum power

reduction yetmaintain system

speed, voltage

Voltage

level shifterPower

Domain 2(2.4V)

Power

Domain 1(3.3V)

used.

Power Domain 3 (1.2V)

Voltage

level

shifter

Voltage

level

shifter

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Tutorial 3 A microprocessor has a FPU containing 300,000 transistors. The

microprocessor contains 200,000 transistors, has a 3.3V supply andoperates with a 5MHz clock. It is proposed to divide this system into three

power blocks:Block 1 3.3V

150,000 CPU transistors

,

Block 2 2.5V200,000 FPU transistors

Block 3 1.8V

50,000 CPU transistors

Q1 Determine the reduction in power consumption.

Q2 Determine the change in the average number of instructionsexecuted per second.

State any assumptions made.

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Tutorial 3 Reduction in power Psys (Vsys)

2

Pnew / Pold = (250x3.32 + 150x2.52+50x1.82) / (500x3.32)

= 0.5 + 0.4 * (2.5/3.3)2 + 0.1 * (1.8/3.3)2

= 0.76

There is a 24% saving (assuming no power loss in level shifting)

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Tutorial 3 Reduction in Average Number of Instructions Clock Frequency Fsys Vsys

If the 3.3V circuit operates at 5 MHz 2.5 V clock = 5 x 2.5/3.3 = 3.79MHz

1.8 V clock = 5 x 1.8/3.3 = 2.73 MHz

Assume : No of instructions N (No. of Transistors) x ClockFrequency

Nnew/Nold = (250*5 + 200*3.79 + 50*2.73) / (500 * 5)

= 0.86

A 14% reduction in the number of instructions per second

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P S l ti


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Processor Selection

Reducing the supply voltage and the system

clock significantly reduce power

consumption. But the processor selected

must have the ability to work under these

conditions.

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Sleep ModeIn some applications such as climate control orsecurity systems, the microcontroller spendsmost of it time doing nothing or just waiting for akey press

If during these times of inactivity the processorclock is stopped power requirements can bedramatically reduced, Obviously a method of

switching back from sleep is required (usually aninterrupt).

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Ci it D i P ll U R i t


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Circuit Design: Pull-Up Resistors

When PC0-3 = VOH

PR

= (5.0 4.0)2 / 4.7 x 103

= 0.21 mW

All four resistors consume 0.84mW

When PC0-3 = VOL

PR = (5.0 0.6)2 / 4.7 x 103

= 4.12 mW

All four resistors consume 16.48mW

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Reducing Pull-Up Resistor Power

Use a higher value of pull-up resistor (this

reduces the effectiveness of the pull-up) Remove pull-ups completely (PICs are

-

ups)

Use programmable pull-ups (PIC Port B has

weak pull-ups > 40 K that can beprogrammed on or off).

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Examples of Pull up: I2C bus


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Examples of Pull-up: I2C-bus The two bus lines are driven by open collector or

open drain outputs, and are therefore active low.

External pull up resistors (R1 & R2) provide the idle

high condition.

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R d i E t l C t


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Reducing External Components

Each component in a circuit consumes some

power. Removing them reduces power consumption.

e.g.

Remove External Buffers

Move device function into software.

7 segment decoder.

Keypad scanning.

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Power Down


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Power Down

Power down devices

when not in use.

Memory

I/O

Turning off the MOSFET

should remove power

from the external device

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Power Saving: Summary High frequencies lead to high powers

Lower supply voltages reduce power

More transistors mean more functionality but

also more ower

Reduce external components Power down devices when not needed

Put processors to sleep when idle

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-

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Conducted Interference

Equipment

1

Equipment

2

Equipment 2 receives unwantedsignals from equipment 1 via directelectrical connection

Note - via power line, signal bus or earth loops

EMI

Radiated Interference


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Radiated Interference

Equipment

1

Equipment

2

EMI

Equipment 2 receives unwantedradiated EM energy from equipment

1

Note - Equipment 1 / Equipment 2 may or may not be Radios!

EN 50 081 part 1: 1992


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EN 50 081 part 1: 1992

Generic Emission Standard for residential, commercial and

light industry environment

EN 55 022 Radiated Emissions in range 30-1000 MHz

EN55 022 Conducted Emissions 150 kHz to 30 MHz on a.c.

port class B

Discontinuous interference on mains at spot frequencies

EN 60 555 Mains Harmonic Emission

EN 50 082 part 1: 1992


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EN 50 082 part 1: 1992

Generic Immunity Standard for residential, commercial and

light industry environment

IEC 801 part 2 Electrostatic (air) Discharge (8kV)

IEC 801 part 3 Radiated Field 27-500MHz 3V/m

IEC 801 part 4 electrical fast transients (pulses) applied on ports

...plus magnetic field (50Hz at 3A/m), conducted ESD (4kV),50Hz, 10V common mode on signal ports, mains surge (1kV)

Radiated Emissions Test


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Radiated Emissions Test

Device Under

Test

Antenna

Spectrum

Analyser Conductive

Shield

Load Simulator

Power Supply

Artificial Network

RFAbsorber

Material

From CISPR 25 IEC 2002

Radiated Immunity Testing


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Radiated Immunity Testing

Need to radiate high power RF!Must be done in enclosed space:

Anechoic Chamber

TEM Cell

Reverberation Chamber

Radiated Immunity Testing 1


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Anechoic Chamber Measurement

Set-up for substitution method

Question


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Question

Do we expect the field to vary?G

K

73.9=

Antenna factor is proportional to frequencyIf antenna gain is constant, then field varies

Need to set RF Power at each frequency!

Radiated Immunity Testing 1


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Substitution Method

Field probes are placed at selected places in thetest chamber

strength in the test areaThe probes are removed and the EUT is placed in

the calibrated test area

EUT is substituted for the calibrated probe


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-

75

Designing for EMC


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Designing for EMC

Eliminate

Source of EMI

e uce

EMI Conducted EMI

Radiated EMI

SOURCES OF EMI


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SOURCES OF EMI

1. Switching Signals

2. Spurious / Noise3. RF signals

Conducted EMI


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Co ducted

FilteringEarthing

oops

Cable screens

split ground planes

Balanced Lines

Conducted EMI


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Partitioned System Layout

Circuit 1

Most

Sensitive

Identify Sub-circuits and add

filtering to reduce EMI

Circuit 2

Conducted EMI


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Common-mode noise Ground

Circuit 1 and Circuit 2 have a non-zero

impedance common ground

Conducted EMI


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The Single Ground

Digital

Analogue

High Power Power Supply

Use Single ground point for all circuits to

prevent common earth paths

Conducted EMI


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Balanced CircuitsSignal

Vn

Vn

Vs

Noise Vn

Use differential mode signals

rejection of common-mode noise

Radiated Energy = Antenna


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Equipment

1

Equipment

2

Antenna reciprocity Electromagnetic structure works as

both transmitting and receiving

To prevent radiation of EMI or susceptibility to radiated EMIequipment should not act like an antenna!

Wire Antennas


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PCBTrack

Ground

Area

Wire carrying current that is not proximate to a ground currentcan form an antenna can be track on same PCB!

Radiated EMI


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Ground Plane (Microstrip )

Field

Lines

Cross-sectional

view

Field contained principally between track and ground plane

restricts radiation.

Ground Plane

Dielectric

(for PCB)

Radiated EMI


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Multi-layer PCBsCircuit 1 Layer

Ground Layer

Power Layer

0.4mm

0.4mm

0.8mm Dielectric

Circuit 2 Layer

Modern PCB design uses Multi-layer construction,

having a number of printed circuits bonded on top of each

other. A typical construction is shown. One layer isessentially a solid copper layer to provide a common

ground for all circuits. This reduces both common mode

EMI and radiated EMI.

Conducted EMI


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Example of Multi-Layer PCB

Topside RFCircuit

Bottom side

MicroprocessorCircuit

Radiated EMI

h ld


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Shielding

Track

ShieldEnclosing

Circuit

Cross-sectional

view

Fully enclosed circuit by conductive shield, connected to ground.

Electric field constrained within shield no radiation (perfect case).In practice apertures in shield for input/output connections and

manufacture

(ground

potential) Dielectric

Conducted EMI

Shi ldi GSM H d


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Shielding on GSM HandsetMulti-layer PCB with additional

shielding provided by screening

cans soldered in place overcircuit.

-

shielded individually. This reduces

radiated EMI between functions,

as well as to the exterior.

Past Papers


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Last years paper on Moodle. (in Course Details)

Further sample questions can be found in past papers

for

ELEE1106 Advanced Electronic Systems

Note was a 3 hour Exam (4 questions out of 5) DofES

will be a 2 hour Exam (3 questions out of 4)

90

Lab TODAY H022


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Assignment 2 Group 1 11:00 12:30

Tuesday (20th December 2010) 23:59 p.m.


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EXAM

09:30-11:30 a.m. (2hrs)

Thursday

12th January 2011

PK011

dofes w13 revision

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