investigation of program saturation in scaled interpoly dielectric floating-gate memory devices

1698 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 8, AUGUST 2009

Investigation of Program Saturation in ScaledInterpoly Dielectric Floating-Gate Memory Devices

M. Florian Beug, Member, IEEE, Nigel Chan, Timm Hoehr,Lars Mueller-Meskamp, and Michael Specht, Member, IEEE

Abstract—This paper investigates the program saturation in ag-gressively scaled interpoly dielectric (IPD) floating-gate (FG) cellsfor NAND application. To describe the program saturation in IPDstacks containing thick suboxides (≥ 4 nm), a simple model wasdeveloped, directly yielding the maximum reachable programmedthreshold voltage level for a given FG cell geometry. The presentedmodel agrees very well to program saturation measurements car-ried out on a 48 nm FG NAND technology with an IPD composed ofSiO2 and Al2O3. By extending the considerations to an arbitraryIPD, this paper represents the first attempt to quantify the IPDcurrent blocking ability required for future scaled FG memorycells.

Index Terms—FG memory devices, Floating-gate (FG) interfer-ence, interpoly dielectric (IPD), NAND scaling, parasitic coupling,program saturation.

I. INTRODUCTION

THE continued demand for higher floating-gate (FG) NAND

flash densities drives the semiconductor industry to ag-gressively scale down the feature size of FG memory cells.With reduced geometries, two key issues become critical. Thefirst is the dielectric breakdown between neighboring wordlines (WLs) as the spacing between them becomes smaller.This breakdown limits the maximum programming voltage thatcan be applied in the array. The second issue is that the gatecoupling ratio is reduced with smaller feature sizes [1]. Thisis due to the increased cell-to-cell and parasitic couplings atsmaller dimensions. The loss in gate coupling ratio results ina corresponding loss in program-and-erase performance, whichmust be compensated by other means. Geometric changes thatincrease the interpoly dielectric (IPD) area to increase thecoupling ratio are the simplest solution. However, geometrychanges can only be achieved with an increased cell size orincreased process complexity. Therefore, a change in layerthickness or composition is generally preferred over geometricones. Tunnel oxide scaling is not a solution due to the reliabilityconcerns of stress-induced leakage current. It is therefore leftto the aggressive scaling of the IPD to both lower the volt-ages required for programming and maintain cell performance.

Manuscript received February 24, 2009; revised May 18, 2009. First pub-lished June 19, 2009; current version published July 22, 2009. This workwas supported in part by the EFRE fund of the European Community withinthe scope of technology development and in part by the State Saxony of theFederal Republic of Germany. The review of this paper was arranged by EditorG.-T. Jeong.

M. F. Beug, T. Hoehr, and L. Mueller-Meskamp are with Qimonda GmbH &Co. OHG, 01099 Dresden, Germany (e-mail: [email protected]).

N. Chan is with Infineon Technologies, 85579 Munich, Germany.M. Specht is with Qimonda AG, 85579 Munich, Germany.Digital Object Identifier 10.1109/TED.2009.2024020

However, the scaling of the IPD is also critical for the retentionperformance of the FG cells [2].

In this paper, we present a detailed analysis of the programsaturation issue in scaled FG memory cells. Program satu-ration means that the programmed threshold voltage cannotbe increased beyond a certain value since electrons injectedinto the FG directly tunnel through the IPD out of the FG.This can be observed in planar FG cells [3], which results ininsufficient program characteristics. The 3-D-field-simulation-based considerations in Section II will show that programsaturation becomes critical for aggressive IPD scaling. A simpleprogram saturation model will be derived, and different IPDconstructions to avoid program saturation will be considered.Section III will compare the experimental results to the programsaturation model.

II. SIMULATED IPD ELECTRICAL FIELD AND CURRENT

DENSITY CONDITIONS

The FG cell works on the premise that the IPD allowssufficient coupling of the FG to the control gate (CG) whilestill serving as an effective barrier against electrical tunnelingcurrents. On one hand, an electrically thin IPD is preferablefor improved coupling, while a physically thick IPD is prefer-able as a tunneling barrier. In technologies with feature sizesdown to 50 nm, an IPD of 12 nm equivalent oxide thickness(EOT) is acceptable to provide sufficient gate coupling, andconventional oxide–nitride–oxide layers can be used for theIPD. In highly scaled technologies at 30 nm and below, anEOT less than 7 nm is required—which is even smaller thanthe EOT of the tunnel oxide. With these dimensions, a criticalissue is suppressing the electron current from the FG to theCG at the end of programming. To understand the behaviorof FG cells at different technology nodes, the coupling ratiosof four different cells were simulated with a 3-D field solver.This simulation includes the FG–FG coupling to the neighbor-ing cells [4], which reduces the effective gate coupling ratio(αg). Table I summarizes the key parameters of the cells. Anaggressive FG height is given for the smaller feature sizes,which increases the gate coupling ratio but also increases theprocess complexity. In highly scaled technologies, there is notenough space between adjacent FGs in the WL direction toallow for a CG plug. For this reason, a 30 nm planar cell isalso proposed. Fig. 1 shows the resulting gate coupling ratiosof the cells for varied IPD EOT values. It can be seen thatthe planar FG results in a significantly reduced gate couplingratio.

0018-9383/$25.00 © 2009 IEEE

BEUG et al.: INVESTIGATION OF PROGRAM SATURATION IN SCALED IPD FLOATING-GATE MEMORY DEVICES 1699

TABLE IFG CELL DIMENSION FOR GATE COUPLING SIMULATION

Fig. 1. Gate coupling ratio for different technology generations as a functionof IPD EOT thickness obtained from 3-D field simulations.

As the cell scales, the EOT must also be scaled to keepthe same coupling ratio (and, therefore, the same programand erase performance). The programming voltage required toreach a multilevel-cell-capable threshold voltage of ΔVt can beexpressed as

Vpp(ΔVt) = 1.3V

nm· dTOX

αg+ ΔVt (1)

where dTOX is the tunnel oxide thickness. The value of1.3 V/nm (or 13 MV/cm) for programming to Vt = 0 V was ad-justed to the experimental program performance of a sub-50 nmFG technology and also accounts for short tp = 20 μs programpulses. This calibration will be seen in the good agreementbetween the simulated and the extracted gate coupling ratiofor the 48 nm FG cell in Fig. 10(b). Using the coupling ratioscalculated by 3-D simulation and assuming an ideal IPD, whichhas zero tunneling current, the CG programming voltages toachieve a threshold voltage shift of ΔVt = 4 V is shown inFig. 2. In smaller nodes, the loss of coupling ratio dictatesthe use of either higher voltages or a thinner IPD. However, itis clearly seen that for planar FG cells, the program voltagescannot be maintained in the same voltage region as that forconventional FG NAND cells with a CG wrapped around theFG. Higher voltages are not a favorable solution since they

Fig. 2. Program voltage required to reach a threshold voltage of 4 V fordifferent technology generations as a function of IPD EOT thickness.

Fig. 3. Electric field condition in the suboxide of the IPD at a thresholdvoltage of Vt = 4 V.

require larger periphery devices and make the isolation betweenneighboring WLs more challenging.

A. IPD Scaling (Thick-Suboxide IPD)

The field in the tunnel oxide at the end of programmingis self-limiting by the charge that is stored on the FG and isassumed to be 13 MV/cm. Again, assuming that the IPD acts asa perfect barrier to electrons, Fig. 3 shows the field in the SiO2

at the end of programming. The electric field in the suboxide ofthe IPD under this condition was calculated from

EIPD,end(ΔVt) =1.3 V

nm

(dTOX

αg− dTOX

)+ ΔVt

dIPD_EOT. (2)

Below the 50 nm node, the normalized SiO2 field in the IPDapproaches and can even significantly surpass the field in thetunnel oxide at the end of programming. For the planar cell,the field in the IPD can be in the range of two times higherdue to the poor coupling ratio. In this case, the assumptionof an ideal IPD without any tunneling current does not hold.Before these extreme field conditions can be reached, a cur-rent will flow through the IPD, resulting in program satura-tion. Additionally, a strong degradation of the memory cell isexpected due to the high current passing through the entirestack.


Fig. 4. Electrical field condition in the tunnel oxide (ETOX) and the sub-oxide of the IPD (ESubOx) and the programmed Vt shift as a function ofthe programming CG voltage VCG. The parameters used in the calculationswere dTOX = 8.5 nm, dIPD_EOT = 7 nm (dSubOx = 4 nm and dAl2O3

=

7 nm), and αg = 0.7, corresponding to the 3-D field simulation for the 40 nmcell (see Table I).

Details of the field condition in the tunnel oxide and in theIPD suboxide (for the case of 4 nm SiO2 and 7 nm Al2O3),together with the programmed threshold voltage shift, areshown in Fig. 4 as a function of the programming gate voltageVCG. This combination of suboxide and high-k dielectric waspresented to be a potential candidate for a scaled IPD [5],[6]. For the gate coupling ratio value αg = 0.7 taken from the3-D field simulation of the 40 nm FG generation with a tunneloxide thickness of dTOX = 8.5 nm and an IPD EOT value ofdIPD_EOT = 7 nm from Table I, the program characteristic canbe determined. Fig. 4 details the electrical field increase in tun-nel oxide and IPD suboxide according to the gate coupling ratiountil at ETOX = 13 MV/cm or VCG = 15.8 V [as describedby (1)], the programming of the FG starts, as described above.For higher programming CG voltages, the floating negative gatecharge is increased until the tunnel oxide field of 13 MV/cmis reached. Vt accordingly increases until program saturationstarts. The onset of this saturation can be calculated if it isassumed that equal fields in the tunnel oxide and the bottomoxide of the IPD result in equal currents. This assumptionholds under the condition that the conduction mechanismis dominated by Fowler–Nordheim (FN) tunneling, which isvalid for IPD stacks containing a thick bottom oxide greaterthan 4 nm.

Equating the fields between the tunnel oxide and IPD, themaximum reachable threshold voltage under program condi-tions is given by

Vt,max = 1.3V

nm

(dIPD_EOT + dTOX − dTOX

αg

). (3)

This expression directly delivers the Vt saturation pointwhere ETOX and EBotOx in Fig. 4 are merging. This is ex-actly the point where the incremental-step-pulse-programming(ISPP) slope changes from one to a value significantly lowerthan one. The further Vt increase beyond the program saturationpoint (dashed line) does not represent realistic operation con-ditions of an FG memory cell since huge currents are passingthrough the whole cell stack. These strong CG currents are in-

Fig. 5. Program saturation level Vt,max as a function of the IPD EOT fordifferent FG cell generations.

dicated by an ISPP slope < 1 and cause a strong degradation ofthe memory cells, as already mentioned. Equation (3) directlyshows that the maximum programmable Vt level is reducedwhen the IPD EOT value is scaled down. This also holds trueeven if the gate coupling ratio value is kept constant.

Fig. 5 shows the maximum threshold voltage that can beachieved as a function of the IPD EOT and the technologynode. Shown are the values of the saturation point Vt,max ascalculated from (3). Smaller nodes and thinner EOT valuesresult in the reduction of the achievable threshold voltage.

Below the 50 nm node, which can program to a thresholdhigher than 8 V, it becomes increasingly difficult to use a thickbottom oxide due to program saturation. In the case of the30 nm planar cell, a thick bottom oxide does not work at allsince the currents in the IPD during programming exceed thecurrents in the tunnel oxide and result in a negative thresholdvoltage shift.

B. IPD Scaling (Arbitrary IPD)

In the more generalized case, the point of program saturationoccurs when the IPD current is significant when compared tothat of the tunnel oxide. For our analysis, the point where theIPD current equals the tunnel oxide current is taken as thepoint of program saturation. Since FN tunneling currents arestrongly field dependent, this assumption can be used to gaininsight into different IPD layer constructions. Arbitrary IPDlayers can be analyzed with respect to program saturation aslong as the current–voltage (Ig–Vg) characteristic of the layersis known or can be measured. Alternatively, starting with atarget programmed threshold voltage of 4 V, a specification ofthe current density can be derived for the IPD stack to avoidprogram saturation.

In Fig. 6, the ratio of the required IPD current density (whichallows programming to Vt = 4 V) to the tunnel oxide currentdensity is shown.

As long as this ratio is less than one, in principle, an IPDwith a thick bottom oxide can be used. In other words, at athreshold voltage of 4 V, the SiO2 field in the IPD is less thanthe SiO2 field in the tunnel oxide. For reliable operation of theFG cells, however, a certain margin to the JIPD = JTOX caseshould be kept. It can be seen that down to 40 nm, the ratio


Fig. 6. Required IPD current reduction ability (JIPD/JTOX) to preventprogram saturation up to Vt = 4 V as a function of the IPD EOT value.

Fig. 7. Simulated tunnel currents through an IPD consisting of a SiO2 subox-ide and an Al2O3 top oxide using the WKB approximation compared to mea-surements of tunneling through an IPD (1 nm SiO2 suboxide +7 nm Al2O3)from this paper and dielectrics consisting of 1 nm SiO2 suboxide +3.6 nm and6 nm Al2O3, respectively, from [7].

of current densities can be kept well below unity (with severalorders of margin). For the 30 nm cell, the ratio approaches orexceeds one, even for relatively thick IPD EOT values. Thisdirectly means that a conventional thick suboxide (4 nm andthicker) cannot be used in the IPD. Instead, a high-k materialshould be introduced in place of the suboxide to increase theeffective tunneling barrier and obtain a programmable memorycell due to a reduced IPD tunneling current for a given fieldcondition. Alternatively, a monolayer of pure high-k IPD couldbe introduced to reduce the IPD current. To achieve a functional30 nm planar cell, the IPD current density must be reducedby approximately six to seven orders of magnitude comparedto SiO2.

In case of Al2O3 as high-k IPD base material, the IPDcurrent density for different suboxide thicknesses was simu-lated using the Wentzel–Kramers–Brillouin (WKB) tunnelingapproximation, neglecting trap-assisted tunneling contributionsto the tunnel current. Fig. 7 shows the simulated currentdensities as a function of the electrical field in the suboxide(SiO2) in comparison to the current density in a pure SiO2.The used simulation parameters were meff(Al2O3) = 0.45,meff(SiO2) = 0.42, φB(Al2O3) = 2.7 eV, and φB(SiO2) =3.15 eV, as given in [7]. For suboxide thicknesses of 3 nmand thicker, the current densities exactly follow the one of pureSiO2 for electrical field conditions that are relevant for programsaturation (above 10 MV/cm). This confirms the assumptions

made in the thick-suboxide section and the derivation of theequations in Section II-A.

The 2 nm suboxide IPD stack shows, in the field range above10 MV/cm, increased current densities compared to the pure-SiO2 layer, which can be explained by the VARIOT effect [8],[9] when the electrons directly tunnel from the silicon conduc-tion band into the conduction band of Al2O3. Similar increasedcurrent densities can be observed for the higher suboxidethicknesses at a lower field and current density condition whenthe VARIOT conditions for the specific suboxide thicknessesapply.

Significantly reduced current densities compared to the pure-SiO2 curve can only be seen in the simulations for 1 nm and0.5 nm suboxides and the pure Al2O3. For the latter case, thefields are scaled with respect to an (imaginary) SiO2 suboxide.To fulfill the current reduction requirement for a planar FGcell, as shown in Fig. 6, only Al2O3 IPD with less than0.5 nm suboxide is an option when the simulated curves aretaken into account. Current density measurements for Al2O3

high-k layers with 1 nm suboxide from our own measurementsand the literature [7] show significantly increased currentscompared to simulations. These increased tunneling currentdensities, particularly for electrical fields below 10 MV/cm, arecaused by trap-assisted tunneling [7].

Following this kind of considerations, it is possible to de-termine the functionality of a given IPD layer or stack oflayers for a specific FG cell geometry. The principal field-dependent current density measurement for this determinationin a first step can be done on planar IPD capacitors. Forpromising IPD candidates, these layers can be integrated in afull FG cell process of the target cell geometry. However, theconsideration done in precedent sections is the first attempt toquantify the needed IPD current blocking ability for scaled FGmemory cells. In particular, for fully planar FG cells, which aresometimes touted as the memory cell of the future, it seems tobe very tough and rather unlikely to fulfill the IPD requirementsfor a programmable memory cell with a suitable threshold volt-age window. It also results from presented considerations thatall FG cell programming data with ISPP slopes significantlysmaller than one indicate an insufficient IPD layer. Only smalldeviations from one can result from poly-Si depletion effects,as presented in [10].

III. EXPERIMENTAL PROGRAM SATURATION RESULTS

To evaluate the validity of the presented program saturationmodel, we will compare measurements of program satura-tion to the prediction of the program saturation model (3)in this section. To do so, it will be necessary to determinethe gate coupling ratio αg , which is the only parameterin (3) that cannot easily be determined. The other param-eters in (3)—the tunnel oxide thickness (dTOX) and the IPDEOT value (dIPD_EOT)—can be measured from transmis-sion electron microscope (TEM) cross sections or simplecapacitance–voltage measurements on planar capacitors, yield-ing an electrical thickness.

The experimental investigation of program saturation wasdone on a 48-nm FG NAND technology [10]. Different types


Fig. 8. Cross sections along the WL for different CG-plug depths. (a) Thedeepest CG plug represents the split group Plug++. (b) The medium plugbelongs to the group Plug0. (c) The highest CG-plug position is from thePlug−− group.

Fig. 9. ISPP curves for W = 48 nm and L = 200 nm FG single cells withan IPD stack consisting of 6 nm SiO2 and 7 nm Al2O3 and different CG-plugdepths. A deep CG-plug position (Plug++) leads to reduced program voltagesand a higher program saturation level compared to a high CG-plug position(Plug−−).

of samples were used. The first one is a typical NAND stringwith 32 FG cells per string. The half-pitch in both the bit-line(BL) and WL directions is 48 nm. The second type of FGdevice is a 200 nm-long single cell. The device looks, in the WLdirection, exactly like a cell in the NAND array and only differsin the gate etch. The active-area and silicon-trench-isolationformation, FG height, and CG plug are identical for both devicetypes. All investigated FG cells had a tunnel oxide thickness ofdTOX = 8.5 nm and an FG height of 80 nm.

The set of memory device samples for the program sat-uration investigations consists of FG cells with differentCG-plug depths, as shown in Fig. 8. Overall, five differ-ent CG-plug depths were investigated. The deepest CG-plugposition is shown in Fig. 8(a). Fig. 8(b) and (c) shows themedium and the highest CG-plug position. In this set of sam-ples, all FG cell devices had the same IPD stack, consisting of6 nm SiO2 suboxide and 7 nm Al2O3, which results in amoderate IPD EOT of dIPD_EOT = 9 nm. The CG-plug depthvariation is useful to study program saturation, because the gatecoupling ratio αg can be varied in a wide range for a constantIPD layer with fixed current–voltage behavior.

ISPP measurement curves for different plug depth groups areshown in Fig. 9. It can be seen that FG cells with deeper CG

Fig. 10. (a) Required program voltage to program the 200 nm-long FG cell toVt,pgm = 3.5 V and the target 48 nm FG cell to Vt,pgm = 2.5 V as a functionof the CG-plug depth. (b) For the long and the target FG cells, the gate couplingratio (αg) was determined by different methods as a function of the CG-plugdepth. (i) From the required program voltage in (a), αg was determined with thehelp of (1). (ii) From 3-D field simulations using the geometrical dimensionsseen in TEM pictures (Fig. 8), the gate coupling ratio was calculated. For thelong FG cell, αg could additionally be extracted with help of a CG-to-FGcontacted reference cell and the back-bias extraction method [11], [12].

plugs and, therefore, higher gate coupling ratios show fasterprogramming and higher program saturation levels, as expectedfrom (3).

The ISPP measurements are shown for the 200 nm-long and48 nm-wide FG single-cell devices. Due to the lack of nextneighbors in the BL direction, these devices have a highergate coupling ratio than the target 48 nm-long and 48 nm-wideFG cells in the NAND string. As a result, the long cells needsignificantly lower program voltages for programming to adefined ΔVt level, as can be seen in Fig. 10(a). The differenttarget program Vt levels (Vt,pgm) take into account that theinitial Vt (or UV Vt level) is 1 V higher for the long FGcell. The resulting threshold voltage shift ΔVt is accordinglythe same.

For a comparison of the predicted Vt saturation level from themodel in (3) with the measured saturation point (as shown inFig. 9), the gate coupling ratio αg is needed for all split groupsof the long cell and the 48 nm target FG cell, as mentionedbefore. By transposing (1) with respect to αg , the gate couplingratio can be determined from the ISPP measurement

αg = 1.3V

nm· dTOX

Vpp − ΔVt. (4)

The resulting αg values for the long and the target 48 nmcell are shown in Fig. 10(b). Additionally, the gate couplingratio was calculated with the help of a 3-D field simulator[“simulated αg” in Fig. 10(b)]. The geometrical dimensionswere taken from TEM cross sections, as shown in Fig. 8.


Fig. 11. Comparison of the measured program saturation point (Vt,max) andthe maximum reachable threshold voltage Vt,max from the program saturationmodel in (3). ISPP measurements and the Vt,max determination with help ofthe αg values shown in Fig. 10(b) were done for the 200 nm-long and the target48 nm FG cell as a function of the CG-plug depth.

For the 200 nm-long FG cells, the gate coupling ratio couldalso be extracted by measurements. The extraction was donewith the back-bias gate coupling ratio extraction method [11],[12], which uses the memory cell itself and a CG-to-FG con-tacted reference transistor. On the 200 nm FG cell, this contactcould be done together with the string select transistors. Fora 48 nm ground rule, a contact between the CG and the FGin the array is not possible. The extracted αg values for the200 nm-long FG cells are also plotted in Fig. 10(b) and show agood agreement with the simulated and target programming αg

values.The comparison between the measured program saturation

and the program saturation described by (3) is shown in Fig. 11.It is seen again that a deep CG-plug position shows a muchhigher saturation level than a high CG-plug. The trends of themeasured program saturation point for both the 200 nm-longcell and the 48 nm target cell are in very good agreement withthe saturation model.

The analysis of the measured program saturation point(Vt,max) is done by the first and second derivative of theISPP measurement. In the Vt,max extraction, the point wasextracted where the ISPP slope drops from one to a valuesignificantly below one, which results in the minimum ofthe second derivative of the ISPP curve. The offset betweenthe saturation model and the measured saturation point couldbe explained by the simple assumption in the model, wherethe same current densities in the tunnel oxide and IPD areassumed. In this case, program saturation would already startbefore the equality of currents, and therefore, the model wouldpredict slightly higher saturation values. However, the offsetcould also be the result of the calibration of the gate cou-pling ratio extracted from ISPP measurements to the 3-D fieldsimulation values. Considering the simplicity of the presentedsaturation model, the agreement to the experiments is verygood. Starting from an existing technology, the model is effec-tive in predicting trends and relative changes of the programsaturation.

IV. CONCLUSION

In this paper, a simple model to describe the program satu-ration in scaled IPD FG memory cells has been presented. The

model for a thick-suboxide IPD allows direct determination ofthe highest achievable threshold voltage level and uses only thetunnel oxide thickness, the EOT value of the IPD layer, andthe gate coupling ratio for the assumed FG cell geometry asinput variables. Based on this model, the description of programsaturation can be extended to arbitrary IPDs, which allow theanalysis of FG cell geometries based on IPD current–voltagemeasurements from simple large-area capacitors.

Based on the presented considerations, this paper representsthe first attempt to quantify the needed IPD current blockingability for future scaled FG memory cells. With regard to this,it seems very questionable that a pure planar FG cell, withidentical IPD and TOX areas, can be programmable for knownhigh-k dielectrics.

Compared to the experimental data of a 48 nm FG NAND

technology with a SiO2 suboxide/Al2O3 high-k IPD stack, theprogram saturation model has shown good agreement and isvery useful in predicting the relative changes of the highestreachable programmed threshold voltage level for changes ofthe IPD or the cell geometry.

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M. Florian Beug (M’08) was born in 1972. Hereceived the Diploma degree in physics and the Ph.D.degree in electrical engineering from the Universityof Hannover, Hannover, Germany, in 1998 and 2004,respectively.

From 1999 to 2000, he was with the Institut for So-lar Energy Research, Hameln/Emmerthal, Germany.From 2000 to 2004, he was with the Institute forSemiconductor Devices and Electronic Materials,University of Hannover. From 2004 to 2005, he waswith the Tyndall National Institute, Cork, Ireland.

From 2005 to 2006, he was with the Flash Predevelopment Team, InfineonTechnologies, Dresden, Germany. He is currently with the Flash Department,with Qimonda GmbH & Co. OHG, Dresden, Germany, working on the devel-opment of NROM, floating-gate, and charge-trapping NAND technologies. Heis the author or a coauthor of more than 20 publications. His research activitiesinclude the analysis of tunneling oxide degradation and the development ofnew capacitive coupling coefficient extraction methods for nonvolatile memorydevices.

Nigel Chan received the B.A.Sc. degree in electricalengineering from the University of Toronto, Toronto,ON, Canada, in 2005.

From 2005 to 2008, he was with TechnologyDevelopment Group, Actel Corporation, MountainView, CA, focusing on cell development for em-bedded flash-based field-programmable gate arrays.In 2008, he was with Qimonda Dresden GmbH,Dresden, Germany, where he worked on NAND flashcell development. He is currently with the AdvancedTechnology Management Group, Infineon Technolo-

gies, Munich, Germany, working on embedded flash memory.

Timm Hoehr received the Dipl.-Phys. degree fromthe University of Konstanz, Konstanz, Germany,in 2000 and the Ph.D. degree from the Institutfür Integrierte Systeme, Eidgenoessische TechnischeHochschule (ETH) Zürich, Zürich, Switzerland, in2005, where he did research on the modeling ofquantization effects and related transport phenomenain MOS devices.

From 2005 to 2008, he was with Infineon/Qimonda, Dresden, Germany, where he worked onthe development of memory cells for several genera-

tions of NROM and floating-gate technologies. He is currently with QimondaGmbH & Co. OHG, Dresden, Germany, working on process and devicesimulation for DRAM periphery devices.

Lars Mueller-Meskamp was born in Bremen,Germany, in 1978. He received the Diploma de-gree in electrical engineering and information tech-nology and the Ph.D. degree from RWTH AachenUniversity, Aachen, Germany, in 2004 and 2008,respectively.

During his Ph.D., he was with the Institute forSolid State Research, Forschungszentrum Jülich,Jülich, Germany, concentrating on the character-ization of building blocks for future molecularelectronic circuits. In 2007, he joined the Flash Tech-

nology Development Team, Qimonda GmbH & Co. OHG, Dresden, Germany,where he was involved in process and structural development of NAND flashmemories. He recently moved to the Device Engineering Team for DRAM.

Michael Specht (M’08) received the Diploma de-gree in physics from the University of Hamburg,Hamburg, Germany, in 1994 and the Ph.D. degree inphysics from the University of Grenoble, Grenoble,France, in 1998.

He was with the research divisions DRFMC andLETI, CEA, Grenoble, for two years as a Postdocto research on very short Si-MOSFETs until 2000.Afterward, he joined the Central Research Labora-tory, Infineon Technologies, where he worked onnew devices (planar SOI and FinFET), particularly

in the field of nonvolatile memories for five years. In 2005, he joined theProduct Development and Innovation Group, Infineon/Qimonda, where hewas involved in flash memory activities covering technological aspects anddesign technology interface topics. Since 2008, he has been involved in DRAMpredevelopment topics with Qimonda AG, Munich, Germany. He is the authoror a coauthor of about 50 publications. He is the holder of more than 15 patents.

Dr. Specht has served as member on the technical program committee of theInternational Electron Device Meeting from 2007 to 2008.

investigation of program saturation in scaled interpoly dielectric floating-gate memory devices

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