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Trench Isolation Technology for High Performance Complementary Bipolar Devices

Kevin C. Brown, Chris Bracken, Rashid Bashir, Kuiwant Egan, Joe DeSantis,Abul Ehsanul Kabir, Wipawan Yindeepol, Joel McGregor, S. J. Prasad, Reda Razouk

National Semiconductor CorporationAnalog Process Technology Development

Santa Clara, CA 95052-8090

Victor V. Boksha, Juan C. ReyTechnology Modeling Associates

Palo Alto, CA 94303-4605

ABSTRACT

A trench isolation architecture for a low voltage (<15V), high frequency, complementary bipolar processtechnology has been developed. This technology features shallow and deep trench isolation with a minimumdesign rule of 1.Oji, along with a zero encroachment deposited field oxide. Trench etch process results suggest amechanism whereby, depending on the amount of exposed silicon, the plasma can either be considered "silicondeficient" or "oxygen deficient." Black silicon formation during trench etching has been eliminated with an in-situ removal of the photoresist after the hardmask oxide has been defined. Terrain isolation processsimulation results are shown to be more accurate in depicting actual wafer processing structures than Tsuprem-4.Initial bipolar device characteristics are reported that illustrate the integration of the introduced PlaTOxdevice isolation architecture. Realized t/rnax are 6.3/9.5 GHz for NPN, and 3.8/8.2 GHz for PNP transistors.

Keywords: trench etch, device isolation planarization, process simulation, complementary bipolar IC's

1.0 INTRODUCTION

Analog and mixed-signal circuits are an integral part of any electronic system in use today. High performancecomplementary bipolar technologies are in increasing demand for applications such as operational amplifiersrequiring high speed and low distortion. As transistor geometries continue to decrease in size to give therequired gains in product performance demanded by even more complex and sophisticated circuitry, deviceisolation technology must continue to keep pace. Semi-recessed local oxidation of silicon (LOCOS)' has beenthe conventional method for isolating neighboring devices for many years. However, this technique suffersfrom lateral encroachment of the growing oxide into the device active area, creating stress and consumingvaluable real estate. Field oxide thinning and bird's beak punch-through are additional problems encounteredas patterned device isolation and active area regions, respectively, are reduced in size.

Many variations to LOCOS have been introduced over the years in an attempt to solve these problems. Forexample, fully recessed LOCOS (ROx)2 gives improved global planarity, but disadvantages include additionalprocessing required to remove the bird's head, plus increased stress. Poly-buffered LOCOS (PBL)3'4 utilizes apoly or amorphous silicon layer in between the nitride and pad oxide to reduce stress and field oxideencroachment. But subsequent removal of the poiy can create pinholes in the pad oxide leading to degradationof active area quality. Sidewall masked isolation (SWAMI)5'6 gives adequate local and global planarity witha reduced active area encroachment, but the large amount of processing required makes production controldifficult. Fundamentally, most if not all device isolation techniques based on LOCOS suffer from some degree oflateral encroachment, in addition to the thermal budget required for oxide growth.

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Oxide or polysilicon filled silicon trenches, employed as device isolation for bipolar7, CMOS8, and BICMOS9devices, and as storage capacitors for DRAM10, do not have such limitations. Field oxide encroachment intoactive areas does not exist, permitting higher device packing density. Bipolar substrate-collector capacitancesare decreased in addition to greater breakdown voltages. Furthermore, integration of shallow and deep trenchisolation reduces base-collector capacitance and extrinsic-to-intrinsic base resistance11. Latchup resistance ofCMOS devices improves. The use of low temperature oxide instead of po1y as the fill material reduces stress(no capping oxidation is required), improves trench capacitances even further'2, and eliminates any parasiticMOS transistors along the vertical sidewall of the trench13.

Planarization of deep and shallow trench device isolation has been accomplished by resist etchback (REB)with oxide "dummy" fillers'3, more complicated REB with two coats separated by a sputtered oxide'4, REBwith chemical-mechanical polishing (CMP)15, and CMP alone16, among other techniques. REB suffers from thevery tight uniformity tolerances required, in addition to problems controlling loading across the wafer duringthe etchback process. Issues with CMP include process control, dishing, uniformity, and repeatability of theprocess as consumables age and deteriorate.

A schematic representation of the newly developed PIaTOx (inarized trench and field ide) deviceisolation process is presented in Fig. 1 (patent pending). Shallow trenches are 1.4.t deep, while deep trenchdesign rules are ip. wide by lOj.t deep. Benefits of the novel isolation scheme include simultaneous fill of theshallow and deep trenches by low temperature PECVD oxide, conserving thermal budget. Planarization isaccomplished without CMP or REB by using approximately 1.5j wide polysilicon "spacers" as buffer materialaround the active areas with an overlapping, non-critically aligned, reverse-masked resist pattern to protectlow-lying topography during removal of oxide over device regions. The planarization etch includes threediscrete process steps. The first step removes exposed poly spacer material at the same rate as the oxide. Twothirds of the oxide is targeted for removal (Fig. if). The second step etches the remaining oxide, stopping onthe poly. In the last step of the sequence, the poly over active is removed, selective to nitride (Fig. ig). Theremaining portions of the poly spacers are removed later with KOH. All processing utilized is common tostandard wafer fabrication facilities. The technology as-developed, can be applied to CMOS and BiCMOSprocesses, as well as the high performance complementary bipolar process demonstrated here.

Additional features of the low voltage (BV's > i2V) process include super-sell-aligned vertical NFN and PNPtransistors with tungsten silicide cladded poly extrinsic base electrodes for low base resistance, and self-aligned nitride spacers for realization of submicron poly emitters. The 26-mask process comprises high-Qpolycide-to-Mi MOS capacitors; dual-valued, low-parasitic, poly resistors; and a two-level metal backendwith SOG planarization.

Though Tsuprem-4'7 is one of the oldest and most advanced commercial TCAD process simulators for ionimplantation, oxidation, and diffusion, its design includes only basic models for etch and deposition of thinfilms. Terrain18, however, includes specific models for all significant deposition and etch processes. Amongthem, physical vapor deposition (PVD)'9; low/atmospheric pressure, and plasma erthanced chemical vapordeposition (LPCVD, APCVD, PECVD)20'21; high density plasma deposition (HDP)21'22; and wet/dry etchingwith variable lateral and vertical etch rates. Deposition models account for the vapor transport, adsorption,re-emission, re-deposition, and sputtering of material at the structure surface. Etch processes are simulatedthrough models that account for anisotropic and/or isotropic erosion of all interfaces of the structure as well asflux integration for ions and active radicals. For dry etching, PECVD, and HDP, Terrain incorporates ionangular and energy distributions for capacitively-coupled plasma discharges.

Resulting structures for the physical processes modeled by Terrain are approximated using the Level Setalgorithm for moving a surface through a fixed, finite, differential mesh3. For fast, simplified, processing ofeither etching or deposition, Terrain uses computational geometry techniques to keep a boundary-only

SPIE Vol. 2875 149


representation of the complete structure. For more complicated time-dependent structures, Terrain calculatesfluxes for etch and/or deposition rates to compute the actual position of the surface at a new instant in time.

The issues associated with the integration of the trench isolation process into the low voltage complementarybipolar technology will be presented. Trench etch details as well as topographic planarity will be discussed interms of actual silicon processing compared to simulation results. Device performance will also be covered.

2.0 EXPERIMENTAL PROCEDURE

All processing utilized 125mm, P<100>, 12-15 a-cm starting material. A magnetically enhanced reactive ionetch system (MERlE) defined the deep trenches utilizing an HBr/NF3/He-02 plasma chemistry. The primarybenefit of an azimuthally rotating magnetic field parallel to the wafer surface is enhancement of ionizationrate by induction of electrons into helical trajectories between collision allowing lower pressure operationwithout loss of etch rate. The shallow trenches and planarization etch processes were obtained in a 13.56MHzconfigured triode system. The "hollow anode" source, a perforated grounded grid plate, provides enhanced iondensities at low pressures with independent generation and extraction of reactive species resulting in high etchrates with low substrate damage.

Trenches were filled with the plasma enhanced thermal decomposition of tetraethylorthosilicate (TEOS).Wafers were patterned with an i-line stepper featuring exclusive automatic dual alignment. This alignmentsystem incorporates a through-the-lens, direct-reticle referencing, laser illumination system which providesfor excellent alignment precision and overlay. Optically measured film thicknesses were characterized by aNanospec 4150 AFT with UV capability, while physical topography was quantified with a Dektak 3STprofilometer.

3.0 RESULTS AND DISCUSSION

Fig. 2 shows the dependence of silicon and hardmask oxide etch rate and non-uniformity on the percentage Siexposed. Silicon etch rate decreases from approximately 8500 to 5000 A/mitt as the exposed Si increases fromabout 1% to almost 90%. As the amount of silicon exposed increases, etch rate decreases due to lack of reactantspecies availability at the surface of the wafer due to mass transport limitations. Similarly, etch rateuniformity degrades as the reactants can no longer be delivered to all portions of the wafer surface at the samerate. Decreased Si etch rates25, and increased Si etch non-uniformity with increased exposed area26, have alsobeen observed by other researchers using HBr-based trench etch chemistries.

Oxide etch rate, however, first decreases to a point at which deposition occurs, then reverses to increase withincreasing silicon area exposed. This can be explained as, initially, the chemistry is "silicon deficient." Inother words, as the percentage of exposed Si first begins to increase, any additional Si contained within theetch byproducts reacts with oxygen from the feed gas and oxygen being liberated from the sputtered/etchedhardmask material to give deposition. From about 3% to 16% exposed Si, the net effect is deposition. But atapproximately 10% exposed, oxide etching begins to dominate as the remaining oxide exposed decreases withincreasing exposed silicon, reducing necessary oxygen from the deposition reaction mechanism. 02 availabilityfor 5i02 deposition is also limited by increased exposed Si sidewall area available as a chemical sink foroxygen and as a vertical surface available for additional sidewall passivation deposition27. This latter part ofthe curve can be thought of as "oxygen deficient," as there is no longer enough 02 present to react with all of thesilicon being removed from the wafer surface. The gaseous Si-containing fluorine and bromine reactionbyproducts are then removed from the etch system with no chance for further reaction. The following chemicalreactions summarize this mechanism26'27:

50/SPIE Vol. 2875


Si (wafer surface) +Si02 (hardmask) HBr + NF —> SiBr SiF + SiFBr* 02 -- N2 (1 < a < 4, f = 4- c)SiBr ÷ SiF ÷ SiFBra* 02 + He-02 + NF3 -> Si02 + 02 (sidewall deposition/adsorption) + N2 + S1F4 ÷ He

This reaction mechanism is consistent with previously published mechanisms by Engeffiardt6 and Vasquez27.In fact, this mechanism can also explain Engelhardt's 5i02 etch rate observations in HBr/NF3/He-02 andHBr/He-02 systems. For HBr/NF3/He-02, it was observed that increasing He-02 flow, gave consistentlydecreasing oxide etch rates. More Si02 deposition occurred with increased 02 availability, hence, decreasingnet oxide etch rate. Without NF3 in the gas mixture, Si02 etch rate decreased with additional He-02 only forlow He-02 flows, then remained constant. However, it is also known that silicon etch rate in HBr-onlychemistries is quite low (< 800 A/mm), while addition of fluorine-containing gases increases Si etch rate(> 6000 A/min)28. So with HBr/NF3/He-02 in this case, the system is "oxygen deficient" in that any additionof 02 gives decreased oxide etch rate as the deposition rate increases. While with the HBr/He-02 system, thereduced amount of Si in the reaction byproducts gave a reduced etch rate of Si02 for only small increases in theabsolute amount of He-02. As more He-02 is added, the system becomes "silicon deficient," allowing no moreincrease in Si02 deposition rate (or reduction of oxide etch rate) because there aren't enough gaseous Si-containing species present. (Unfortunately, comparable Si etch rates were not presented in the original work totest this hypothesis26.)

These observations are confirmed in Fig. 3, as silicon and oxide etch rates are observed in both "Si deficient"(1% exposed silicon) and "O deficient" (11% and 22.5% exposed) regimes for increasing amounts of He-02 gas.Note the shift in the oxide etch rate curve from 11% to 22.5% exposed, at the same levels of He-02. With moreexposed silicon, the reduced amount of oxygen being liberated from the reduced amount of oxide present can becompensated for by increasing the amount of He-02 in the plasma. Based on Fig. 2, 11% exposed was thought tohave been the cusp between the two regimes, but because of the lack of a mask layer percentage between theprevious point of —4% and 11%, the cusp is probably closer to 7% to 8% exposed Si. As expected, at 1% exposed,there is not enough Si contained with the reaction byproducts to sustain the deposition of additional dioxidewith further additions of oxygen, so the etch rate flattens out and never becomes deposition. Oxide etch non-uniformity increasing with decreasing etch rate, also confirms previous results26. Increased silicon non-uniformity with small additions of 02 is possibly due to a minimum amount of oxygen necessary for mixingand/or dilution of the glow discharge, stabilizing uniformity across the wafer.

Some experiments were also conducted to understand the formation of "black" silicon during the trench etchprocess. Black Si is the micromasking of silicon during the etch process resulting in a darkened appearanceafter etch due to the reduction in reflectivity caused by the presence of "spires" or stalagmites on the wafersurface. The following table presents these results:

Hardmask Photoresist Removal Process Black Si?Piranha Clean then 10:1 HF (recirculated bath) SomePiranha Clean WorsePiranha Clean then 10:1 HF (static bath) WorstIn-Situ Oxygen Plasma Ash None

The best process does not include any sort of wet processing: sulfuric acid/hydrogen peroxide or solvent.Throughput, and hence, wafer cost, are improved. Figs. 4a and b are an optical and SEM photograph,respectively, of black silicon observed for the piranha clean with a via mask (approximately 30% exposed).Unlike previous observations6, with the optimized in-situ process, no evidence of black silicon could beproduced by either increasing oxygen flow or with large amounts of exposed silicon.

SPIEVo!. 2875/Si


Optimization of the photolithography surrounding the PlaTOx device isolation planarization process isillustrated in Fig. 5. The original design rule for the reverse planar mask to active area was a simple x andyoffset of 1.Oji (Fig. 5a). However, the distance between the corner of active, and the corner of planar, was thenl.41i (square root of 2 x 1.02). The x and y offset were changed to 1.5j, while with the additional rounding ofthe composite areas after TEOS trench-fill, the planar-to-active distance maintains a constant value of 1.5iaround the corners (Fig. 5b). A SEM cross-section of the structure before the planarization etch process is shownin Fig. 5c. Note the placement of the resist edge within the confines of the poly spacers.

IiAOld Design Rule

The optimization of the first step of the planarization etch (Fig. if), is presented in Fig. 6. The graph showsthat a range of oxide to poiy etch selectivities are available by increasing the amount of SF6 in a SF6/C2F6plasma etch chemistry. To mimic the actual structure present during the planarization etch process, oxide andpoly etch rates were performed with different masks. Much less poly is exposed under the edges of resist aroundthe oxide covered active regions. Fig. 7 gives an example of a SEM cross-section of a completed device. The dipin field oxide adjacent to the active areas is simpiy the replication of the conformality of the trench-fill TEOSdeposition over the corner of the composite region.

The major purpose for simulation of the PlaTOx process was to qualitatively demonstrate significant impact ofthe choice of the most appropriate simulator on the specific important features of the structure. While it waspossible to simulate basic topography with Tsuprem-4 (Fig. 8a,b -the dip in field oxide next to active areas),Terrain was needed to model trench bottom rounding, voids formation during TEOS trench filling, TEOS stepcoverage, and polysilicon spacer shape. By applying a combination of Terrain's PECVD/LPCVD, anisotropicetch, and conformal deposition models, for example, the residual oxide spikes produced in the Tsuprem-4simulation (which are not present in the final actual device structure), were eliminated (Fig. 8c,d). This is dueto the thinner sidewall step coverage of TEOS giving a more vertical profile rather than the undersidecurvature of the poly spacers produced by Tsuprem-4. Terrain also more accurately modeled the curvature of thedip in field oxide adjacent to active.

Even without the extensive calibration efforts typically required for proper comparison of process simulation toexperimental data24, careful comparison with SEM photographs shows good quantitative agreement betweenthe two:

Measured Parameter Terrain ActualActive Area Sidewall TEOS Step Coverage 60% 61%Trench Sidewall TEOS Step Coverage 0.28j. 0.26kTrench Bottom TEOS Step Coverage 0.39jt O.34iiSidewall/Bottom Ratio 0.72 0.76

Preliminary electrical results from the high performance complementary bipolar technology are summarized inthe following table:

52 / SPIE Vol. 2875

New Design Rule


Parameter NPN I PNP

Emitter Size 0.9 x 19.9 ji2 0.9 x 19.9 ji2

Current Gain, J3 90 45

Early Voltage, V, 86V 52V13 x V2 7740V 2340V

BVcep 14V 18V

BVth 32V 24V

BV,0 22V 18VExtrinsic Base Sheet p 2.5 2/D 2.5 /DCEB 51fF 65fFCCB 29fF 34fF

C 48fF 45fFTransition Frequency, f 6.3GHz 3.8GHz

Maximum Frequency, m2x 9.5GHz 8.2GHzCurrent Density @ peak 80p.A/j.i2 85pA/p.2

IrLitial characteristic plots of Ic vs. Vce are shown for NPN and PNP transistors, respectively, in Figs. 9a and b.Work is now in progress to reduce PNP collector current leakage due to P+ buried layer defects caused byinsufficient annealing of boron ion-implant damage prior to epitaxial growth. In addition, optimization of theplasma etch process during patterning of the extrinsic base electrode stack, and improvement of the pre-cleanprior to emitter poly deposition, are thought to reduce the high levels of emitter-base recombination currentand leakage at the emitter periphery present for both NPN and PNP transistors.

4.0 SUMMARY AND CONCLUSIONS

A novel trench isolated device planarization architecture specifically applied to a low voltage, highperformance complementary bipolar device technology has been developed. The effects of percentage exposedarea on trench silicon and hardmask oxide etch rates and uniformities has been described. A reactionmechanism pathway has been suggested that possibly explains observations here as well as those publishedelsewhere. The resist removal process after the hardmask etch has been characterized for "black silicon"formation. Tsuprem-4 and Terrain process simulations show that Terrain more accurately represents the resultsseen with actual processing in terms of device structure features. Finally, preliminary device results have beenillustrated that show the successful integration of the new isolation planarization technology. It is envisionedthat the PlaTOx process is as applicable to CMOS-based devices as for the low voltage bipolar flowdemonstrated here.

5.0 ACKNOWLEDGMENTS

Special thanks again to the Advanced Technology Group's analytical SEM characterization lab, especiallyJack Mah; Diana Iran of SCVD for wafer processing; Evelyn Puchta at TMA for technical sales support;Francois Hebert (now at Spectrian) and Datong Chen for initial process technology concepts; and Ruth Bucknellat Applied Materials for useful discussions.

6.0 REFERENCES

[11 E. Kooi, J.G. van Lierop, W.H.C.G. Verkuijlen, R. de Werdt, "LOCOS Devices," Philips Research Reports,26 (1971) 166.

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[2] K.D. Beyer, M.R. Poponiak, M. Revitz, "Recessed Oxide Isolation Process," IBM Technical DisclosureBulletin, 20 (1997) 999.

[3] R.H. Havemann, G.P. Pollack, "Method for Integrated Circuit Device Isolation," U.S. Patent 4,541,167(1985).

[4] K.C. Brown, C. Li, N. Narahari, D.M. Rossman, M. Shenasa, "Poly-Buffered LOCOS Isolation PatternDefinition," ECS Extended Abstracts, 94-1 (1994) 291.

[5] K.Y. Chiu, J.L. Moll, J. Manoliu, "A Bird's Beak Free Local Oxidation Technology Feasible for VLSICircuits Fabrication," IEEE Trans. on Electron Devices, ED-29 (1982) 536.

[6] C. Claeys, J. Vanhellemont, T. Cavioni, F. Gualandris, "Structural and Electrical Characterization ofSWAMI Techniques for Submicron Technologies," J. Electrochem Soc., 136 (1989) 2619.

[7] D.D. Tang, P.M. Solomon, T.H. Ning, R.D. Isaac, R.E. Burger, "1.25 urn Deep-Groove-Isolated Self-AlignedBipolar Circuits," IEEE J. Solid-State Circuits, SC-17 (1982) 925.

[8] RD. Rung, H. Momose, Y. Nagakubo, "Deep Trench Isolated CMOS Devices," IEDM Tech. Dig., (1982) 237.[9] M. Kerber, E. Bertagnolli, R. Mahnkopf, J. Popp, A. felder, H.M. Rein, A. Weisgerber, H. Kiose, "A High

Performance BiCMOS Process Featuring 40 Ghz/2lps," IEDM Tech. Dig., (1992) 449.[10] G.K. Herb, D.J. Rieger, K. Shields, "Silicon Trench Etch in a Hex Reactor," Solid State Tech., Oct. (1987)

109.[11] T. linuma, N. Itoh, H. Nakajima, K. Inou, S. Matsuda, C. Yoshino, Y. Tsuboi, Y. Katsumata, H. Iwai, "Sub-

20 ps High Speed ECL Bipolar Transistor with Low Parasitic Architecture," IEEE Trans. on ElectronicDevices, 42 (1995) 399.

[12] P.F. Lu, CT. Chuang, "On the Scaling Property of Trench Isolation Capacitance for Advanced High-Performance ECL Circuits," IEEE Trans. on Electron Devices, 37 (1990) 2270.

[13] H. Mikoshiba, T. Homma, K. Hamano, "A New Trench Isolation Technology as a Replacement ofLOCOS," IEDM Tech. Dig., (1984) 578.

[14} G. Fuse, H. Ogawa, K. Tateiwa, I. Nakao, 5, Odanaka, M. Fukumoto, H. Iwasaki, T. Ohzone, "A PracticalTrench Isolation Technology with a Novel Planarization Process," IEDM Tech. Dig., (1987) 732.

[15] B. Davari, C.W. Koburger, R. Schulz, J.D. Warnock, T. Furukawa, M. Jost, Y. Taur, W.G. Schwittek, J.K.DeBrosse, M.L. Kerbaugh, J.L. Mauer, "A New Planarization Technique Using a Combination of RIE andChemical-Mechanical Polish (CMP)," IEDM Tech. Dig., (1989) 61.

[16] J.M. Pierce, P. Rentein, W.R. Burger, S.T. Aim, "Oxide-Filled Trench Isolation Planarized UsingChemical-Mechanical Polishing," Proc. 3rd mt. Symp. on ULSI Sci. and Tech., 91-11 (1991) 650.

[17] "TMA Tsuprem-4: Two-Dimensional Process Simulation Program (v. 6.3)," Technology ModelingAssociates, Inc., Sunnyvale, CA.

[18] "Terrain: Deposition and Etch Simulation (v. 1.0)," Technology Modeling Associates, Inc., Sunnyvale, CA.[19] Alberta Microelectronic Center, "SIMBAD: Thin Film Process Simulator," (1996) verson 1.4.[20] J.P. McVittie, J.C. Rey, A.J. Bariya, M.M. Islam Raja, L.Y. Cheng, S. Ravi, K.C. Saraswat, "SPEEDIE: A

Profile Simulator for Etching and Deposition," SPIE, 1392 (1990) 126.[21] J. Li, "Topography Simulation of Intermetal Dielectric Deposition and Interconnection Metal Deposition

Processes," Ph.D. Dissertation, StanfordUniversity, March 1996.[22] D. Adalsteinsson, J.A. Sethian, J.C. Rey, "High Density Plasma Deposition Modeling Using Level Set

Methods," DUMIC, (1996) 116.[23] D. Adalsteinsson, J.A. Sethian, J.C. Rey, "Etching and Deposition Modeling Using Level Set Methods,"

VMIC, (1996) 224.[24] Sematech, "Technology Computer-Aided Design (TCAD) Roadmap," 1995.[25] K. Cooper, B.-Y. Nguyen, J.-H. Lin, B. Roman, P. Tobin, W. Ray, "Magnetically Enhanced RIE Etching of

Submicron Silicon Trenches," SPIE, 1392 (1990) 253.[26] M. Engelhardt, "Optimized High Rate Deep Silicon Trench Etching for Dielectric Isolation in Smart

Power Devices," ECS Extended Abstracts, 94-1 (1994) 336.[27] B. Vasquez, H. G. Tompkins, P. Fejes, T.Y. Lee, L. Smith, "Characterization of Sidewall Passivation

Material Deposited During Trench Etch," SPIE, 1185 (1989) 148.[28] Y. Lii, H. Ng, D.A. Danner, "Magnetic Enhanced RIE of Silicon DeepTrench," ECS Extended Abstracts, 90-

1 (1990) 178.

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Figure laPad Oxide GrowthNitride and Poly DepositionActive Area MaskShallow Trench EtchPETEOS Deposition

Figure lcDeep Trench EtchSacrificial Oxide GrowthStrip Sac Ox / Hard MaskLining Oxide Growth

Figure idPETEOS Fill

Poly DepositionPoly Spacer Etch

Figure igRemaining Oxide EtchPoly (over Nitride) Etch

SPIE Vol. 2875/55

Figure lbTrench MaskOxide Etch

Figure le Figure lfPhotoresist Mask Oxide and Poly Etch (1:1)

Figure 1:Schematic Cross-SectionRepresentation of PLATOXProcess Flow

Figure lhResist StripPoly Removal (KOH)


Figure 2. Hardmask Oxide and Silicon Etch Rates and Non-Uniformity vs. Percent Si Exposed

Figure 3. Hardmask Oxide and Silicon Etch Rates and Non-Uniformity vs. He-O2 Feed Gas Input

56 / SPIE Vol. 2875

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SP!E Vol. 2875 157

Figure 4a. Optical Photograph of "Black Silicon"


58 / SPIE Vol. 2875

Figure 5a.Planar ResistMask over PolySpacers aroundActive Areas,1.Oji x/y Offset

Figure 5b.Constant 1.5Planar-to-ActiveOffset

Figure 5c.Cross-Section ofStructure BeforePlanarization Etch


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SPIE Vol. 2875 159

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60 1 SPIE Vol. 2875

Figure 8. TSUPREM-4 Output after Poly Spacer Etchback (a) and Complete Structure (b);TERRAIN Output (c) and (d)

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SPIE Vol. 2875 161

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